opcodes: blackfin: constify register names
Constify the array itself since it need not be writable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger
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@ -1,3 +1,11 @@
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2011-02-11 Mike Frysinger <vapier@gentoo.org>
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* bfin-dis.c (reg_names): Add const.
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(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
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decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
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decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
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decode_counters, decode_allregs): Likewise.
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2011-02-09 Michael Snyder <msnyder@vmware.com>
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* i386-dis.c (OP_J): Parenthesize expression to prevent
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@ -1,5 +1,6 @@
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/* Disassemble ADI Blackfin Instructions.
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Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
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Free Software Foundation, Inc.
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This file is part of libopcodes.
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@ -258,7 +259,7 @@ enum reg_class
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LIM_REG_CLASSES
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};
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static const char *reg_names[] =
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static const char * const reg_names[] =
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{
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"R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
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"R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
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@ -289,7 +290,7 @@ static const char *reg_names[] =
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#define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
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/* RL(0..7). */
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static enum machine_registers decode_dregs_lo[] =
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static const enum machine_registers decode_dregs_lo[] =
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{
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REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
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};
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@ -297,7 +298,7 @@ static enum machine_registers decode_dregs_lo[] =
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#define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
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/* RH(0..7). */
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static enum machine_registers decode_dregs_hi[] =
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static const enum machine_registers decode_dregs_hi[] =
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{
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REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
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};
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@ -305,7 +306,7 @@ static enum machine_registers decode_dregs_hi[] =
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#define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
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/* R(0..7). */
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static enum machine_registers decode_dregs[] =
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static const enum machine_registers decode_dregs[] =
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{
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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};
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@ -313,7 +314,7 @@ static enum machine_registers decode_dregs[] =
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#define dregs(x) REGNAME (decode_dregs[(x) & 7])
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/* R BYTE(0..7). */
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static enum machine_registers decode_dregs_byte[] =
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static const enum machine_registers decode_dregs_byte[] =
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{
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REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
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};
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@ -321,7 +322,7 @@ static enum machine_registers decode_dregs_byte[] =
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#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
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/* P(0..5) SP FP. */
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static enum machine_registers decode_pregs[] =
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static const enum machine_registers decode_pregs[] =
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{
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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};
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@ -334,7 +335,7 @@ static enum machine_registers decode_pregs[] =
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#define accum(x) REGNAME (decode_accum[(x) & 1])
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/* I(0..3). */
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static enum machine_registers decode_iregs[] =
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static const enum machine_registers decode_iregs[] =
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{
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REG_I0, REG_I1, REG_I2, REG_I3,
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};
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@ -342,7 +343,7 @@ static enum machine_registers decode_iregs[] =
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#define iregs(x) REGNAME (decode_iregs[(x) & 3])
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/* M(0..3). */
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static enum machine_registers decode_mregs[] =
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static const enum machine_registers decode_mregs[] =
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{
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REG_M0, REG_M1, REG_M2, REG_M3,
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};
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@ -352,7 +353,7 @@ static enum machine_registers decode_mregs[] =
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#define lregs(x) REGNAME (decode_lregs[(x) & 3])
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/* dregs pregs. */
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static enum machine_registers decode_dpregs[] =
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static const enum machine_registers decode_dpregs[] =
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{
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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@ -361,7 +362,7 @@ static enum machine_registers decode_dpregs[] =
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#define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
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/* [dregs pregs]. */
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static enum machine_registers decode_gregs[] =
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static const enum machine_registers decode_gregs[] =
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{
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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@ -370,7 +371,7 @@ static enum machine_registers decode_gregs[] =
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#define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
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/* [dregs pregs (iregs mregs) (bregs lregs)]. */
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static enum machine_registers decode_regs[] =
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static const enum machine_registers decode_regs[] =
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{
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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@ -381,7 +382,7 @@ static enum machine_registers decode_regs[] =
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#define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
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/* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
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static enum machine_registers decode_regs_lo[] =
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static const enum machine_registers decode_regs_lo[] =
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{
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REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
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REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
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@ -391,7 +392,7 @@ static enum machine_registers decode_regs_lo[] =
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#define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
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/* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
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static enum machine_registers decode_regs_hi[] =
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static const enum machine_registers decode_regs_hi[] =
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{
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REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
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REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
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@ -401,7 +402,7 @@ static enum machine_registers decode_regs_hi[] =
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#define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
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static enum machine_registers decode_statbits[] =
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static const enum machine_registers decode_statbits[] =
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{
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REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
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REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
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@ -416,7 +417,7 @@ static enum machine_registers decode_statbits[] =
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#define statbits(x) REGNAME (decode_statbits[(x) & 31])
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/* LC0 LC1. */
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static enum machine_registers decode_counters[] =
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static const enum machine_registers decode_counters[] =
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{
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REG_LC0, REG_LC1,
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};
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@ -426,7 +427,7 @@ static enum machine_registers decode_counters[] =
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/* [dregs pregs (iregs mregs) (bregs lregs)
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dregs2_sysregs1 open sysregs2 sysregs3]. */
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static enum machine_registers decode_allregs[] =
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static const enum machine_registers decode_allregs[] =
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{
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
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REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
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