Re-do load/store operations so that they work for both 32 and 64 bit
ISAs. Enable tx39 as igen again.
This commit is contained in:
Andrew Cagney
parent
7cdd6cac82
commit
69d5a56645
@ -78,7 +78,7 @@ Things-to-lose:
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Do-last:
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r5900_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen"
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r5900_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen r5900.igen tx.igen"
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if ( echo $* | grep keep\-r5900 > /dev/null ) ; then
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for i in $r5900_files ; do
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@ -140,7 +140,7 @@ case "${target}" in
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;;
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# end-sanitize-tx19
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mipstx39*-*-*) sim_default_gen=IGEN
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sim_use_gen=NO
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sim_use_gen=IGEN
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sim_igen_filter="32,f"
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sim_igen_machine="-M r3900"
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;;
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@ -82,9 +82,7 @@ char* pr_uword64 PARAMS ((uword64 addr));
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/* Get the simulator engine description, without including the code: */
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#if (WITH_IGEN)
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#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
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#else
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#if !(WITH_IGEN)
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#define SIM_MANIFESTS
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#include "oengine.c"
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#undef SIM_MANIFESTS
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@ -1626,7 +1624,7 @@ load_memory (SIM_DESC sd,
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uword64* memvalp,
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uword64* memval1p,
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int CCA,
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int AccessLength,
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unsigned int AccessLength,
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address_word pAddr,
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address_word vAddr,
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int IorD)
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@ -1653,9 +1651,9 @@ load_memory (SIM_DESC sd,
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if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
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{
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/* In reality this should be a Bus Error */
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sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
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sim_io_error (sd, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
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AccessLength,
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(LOADDRMASK + 1) << 2,
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(LOADDRMASK + 1) << 3,
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pr_addr (pAddr));
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}
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@ -1717,13 +1715,13 @@ load_memory (SIM_DESC sd,
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(int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
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#endif /* DEBUG */
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/* See also store_memory. */
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if (AccessLength <= AccessLength_DOUBLEWORD)
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/* See also store_memory. Position data in correct byte lanes. */
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if (AccessLength <= LOADDRMASK)
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{
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if (BigEndianMem)
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/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
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shifted to the most significant byte position. */
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value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
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value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
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else
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/* For little endian target, byte (pAddr&LOADDRMASK == 0)
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is already in the correct postition. */
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@ -1758,7 +1756,7 @@ store_memory (SIM_DESC sd,
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sim_cpu *cpu,
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address_word cia,
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int CCA,
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int AccessLength,
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unsigned int AccessLength,
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uword64 MemElem,
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uword64 MemElem1, /* High order 64 bits */
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address_word pAddr,
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@ -1774,7 +1772,10 @@ store_memory (SIM_DESC sd,
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#endif /* WARN_MEM */
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if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
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sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
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sim_io_error (sd, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
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AccessLength,
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(LOADDRMASK + 1) << 3,
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pr_addr(pAddr));
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#if defined(TRACE)
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dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
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@ -1784,13 +1785,13 @@ store_memory (SIM_DESC sd,
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printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
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#endif /* DEBUG */
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/* See also load_memory */
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if (AccessLength <= AccessLength_DOUBLEWORD)
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/* See also load_memory. Position data in correct byte lanes. */
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if (AccessLength <= LOADDRMASK)
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{
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if (BigEndianMem)
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/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
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shifted to the most significant byte position. */
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MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
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MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
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else
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/* For little endian target, byte (pAddr&LOADDRMASK == 0)
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is already in the correct postition. */
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@ -1954,7 +1955,7 @@ signal_exception (SIM_DESC sd,
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code = (instruction >> 6) & 0xFFFFF;
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sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
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code, pr_addr(cia));
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code, pr_addr(cia));
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}
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break;
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@ -824,15 +824,22 @@ decode_coproc (SD, CPU, cia, (instruction))
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#define AccessLength_DOUBLEWORD (7)
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#define AccessLength_QUADWORD (15)
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#if (WITH_IGEN)
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#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
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? AccessLength_DOUBLEWORD /*7*/ \
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: AccessLength_WORD /*3*/)
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#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
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#endif
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int address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
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#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
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address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
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void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
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void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
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#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
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load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
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void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
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void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
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#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
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store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
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45
sim/mips/tx.igen
Normal file
45
sim/mips/tx.igen
Normal file
@ -0,0 +1,45 @@
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// -*- C -*-
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//
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// toshiba specific instructions.
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//
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011100,5.RS,5.RT,5.RD,00000000000:MMINORM:::MADD
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"madd r<RS>, r<RT>":RD == 0
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"madd r<RD>, r<RS>, r<RT>"
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*r3900
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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signed64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
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+ ((signed64) EXTEND32 (GPR[RT])
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* (signed64) EXTEND32 (GPR[RS])));
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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LO = EXTEND32 (prod);
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HI = EXTEND32 (VH4_8 (prod));
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TRACE_ALU_RESULT2 (HI, LO);
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if(RD != 0 )
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GPR[RD] = LO;
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}
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011100,5.RS,5.RT,5.RD,00000000001:MMINORM:::MADDU
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"maddu r<RS>, r<RT>":RD == 0
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"maddu r<RD>, r<RS>, r<RT>"
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*r3900
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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unsigned64 prod = (U8_4 (VL4_8 (HI), VL4_8 (LO))
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+ ((unsigned64) VL4_8 (GPR[RS])
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* (unsigned64) VL4_8 (GPR[RT])));
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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LO = EXTEND32 (prod);
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HI = EXTEND32 (VH4_8 (prod));
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TRACE_ALU_RESULT2 (HI, LO);
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if(RD != 0)
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GPR[RD] = LO;
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}
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