2000-08-28 Dave Brolley <brolley@redhat.com>
* cgen-ibld.in (cgen_put_insn_int_value): New function. (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. * cgen-dis.in (read_insn): New static function. (print_insn): Use read_insn to read the insn into the buffer and set up for disassembly. (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is in the buffer. * fr30-asm.c: Regenerated. * fr30-desc.c: Regenerated. * fr30-desc.h Regenerated. * fr30-dis.c: Regenerated. * fr30-ibld.c: Regenerated. * fr30-opc.c: Regenerated. * fr30-opc.h Regenerated. * m32r-asm.c: Regenerated. * m32r-desc.c: Regenerated. * m32r-desc.h Regenerated. * m32r-dis.c: Regenerated. * m32r-ibld.c: Regenerated. * m32r-opc.c: Regenerated.
This commit is contained in:
parent
bf830eae8f
commit
6bb95a0ff8
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@ -1,3 +1,28 @@
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2000-08-28 Dave Brolley <brolley@redhat.com>
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* cgen-ibld.in (cgen_put_insn_int_value): New function.
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(insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
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(insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
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(extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
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* cgen-dis.in (read_insn): New static function.
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(print_insn): Use read_insn to read the insn into the buffer and set
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up for disassembly.
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(print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
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in the buffer.
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* fr30-asm.c: Regenerated.
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* fr30-desc.c: Regenerated.
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* fr30-desc.h Regenerated.
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* fr30-dis.c: Regenerated.
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* fr30-ibld.c: Regenerated.
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* fr30-opc.c: Regenerated.
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* fr30-opc.h Regenerated.
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* m32r-asm.c: Regenerated.
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* m32r-desc.c: Regenerated.
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* m32r-desc.h Regenerated.
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* m32r-dis.c: Regenerated.
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* m32r-ibld.c: Regenerated.
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* m32r-opc.c: Regenerated.
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2000-08-28 Kazu Hirata <kazu@hxi.com>
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* tic30-dis.c: Fix formatting.
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@ -187,6 +187,48 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
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}
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}
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/* Subroutine of print_insn. Reads an insn into the given buffers and updates
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the extract info.
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Returns 0 if all is well, non-zero otherwise. */
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static int
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read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
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CGEN_CPU_DESC cd;
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bfd_vma pc;
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disassemble_info *info;
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char *buf;
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int buflen;
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CGEN_EXTRACT_INFO *ex_info;
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unsigned long *insn_value;
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{
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int status = (*info->read_memory_func) (pc, buf, buflen, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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ex_info->dis_info = info;
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ex_info->valid = (1 << buflen) - 1;
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ex_info->insn_bytes = buf;
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switch (buflen)
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{
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case 1:
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*insn_value = buf[0];
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break;
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case 2:
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*insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
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break;
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case 4:
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*insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
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break;
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default:
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abort ();
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}
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return 0;
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}
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/* Utility to print an insn.
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BUF is the base part of the insn, target byte order, BUFLEN bytes long.
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The result is the size of the insn in bytes or zero for an unknown insn
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const CGEN_INSN_LIST *insn_list;
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CGEN_EXTRACT_INFO ex_info;
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ex_info.dis_info = info;
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ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1;
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ex_info.insn_bytes = buf;
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switch (buflen)
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{
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case 1:
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insn_value = buf[0];
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break;
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case 2:
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insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
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break;
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case 4:
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insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
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break;
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default:
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abort ();
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}
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int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
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if (rc != 0)
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return rc;
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/* The instructions are stored in hash lists.
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Pick the first one and keep trying until we find the right one. */
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machine insn and extracts the fields. The second pass prints
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them. */
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#if CGEN_INT_INSN_P
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/* Make sure the entire insn is loaded into insn_value. */
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if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize)
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{
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unsigned long full_insn_value;
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int rc = read_insn (cd, pc, info, buf,
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CGEN_INSN_BITSIZE (insn) / 8,
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& ex_info, & full_insn_value);
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if (rc != 0)
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return rc;
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length = CGEN_EXTRACT_FN (cd, insn)
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(cd, insn, &ex_info, full_insn_value, &fields, pc);
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}
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else
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#endif
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length = CGEN_EXTRACT_FN (cd, insn)
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(cd, insn, &ex_info, insn_value, &fields, pc);
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/* length < 0 -> error */
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@ -57,6 +57,9 @@ static int extract_normal
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static int extract_insn_normal
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PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
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static void put_insn_int_value
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PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
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/* Operand insertion. */
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if (length == 0)
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return NULL;
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#if 0
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if (CGEN_INT_INSN_P
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&& word_offset != 0)
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abort ();
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#endif
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if (word_length > 32)
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abort ();
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@ -237,9 +242,9 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
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int shift;
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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shift = (word_offset + start + 1) - length;
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else
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shift = word_length - (start + length);
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shift = total_length - (word_offset + start + length);
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*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
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}
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#if CGEN_INT_INSN_P
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*buffer = value;
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put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
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CGEN_FIELDS_BITSIZE (fields), value);
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#else
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return NULL;
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}
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/* Cover function to store an insn value into an integral insn. Must go here
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because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
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static void
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put_insn_int_value (cd, buf, length, insn_length, value)
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CGEN_CPU_DESC cd;
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CGEN_INSN_BYTES_PTR buf;
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int length;
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int insn_length;
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CGEN_INSN_INT value;
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{
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/* For architectures with insns smaller than the base-insn-bitsize,
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length may be too big. */
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if (length > insn_length)
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*buf = value;
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else
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{
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int shift = insn_length - length;
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/* Written this way to avoid undefined behaviour. */
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CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
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*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
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}
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}
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/* Operand extraction. */
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return 1;
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}
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#if 0
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if (CGEN_INT_INSN_P
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&& word_offset != 0)
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abort ();
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#endif
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if (word_length > 32)
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abort ();
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/* Does the value reside in INSN_VALUE? */
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if (word_offset == 0)
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if (CGEN_INT_INSN_P || word_offset == 0)
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{
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/* Written this way to avoid undefined behaviour. */
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CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
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if (CGEN_INSN_LSB0_P)
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value = insn_value >> ((start + 1) - length);
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value = insn_value >> ((word_offset + start + 1) - length);
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else
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value = insn_value >> (word_length - (start + length));
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value = insn_value >> (total_length - ( word_offset + start + length));
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value &= mask;
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/* sign extend? */
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if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
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@ -398,7 +398,7 @@ parse_insn_normal (cd, insn, strp, fields)
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first char after the mnemonic part is a space. */
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/* FIXME: We also take inappropriate advantage of the fact that
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GAS's input scrubber will remove extraneous blanks. */
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if (*str == CGEN_SYNTAX_CHAR (* syn))
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if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
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{
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#ifdef CGEN_MNEMONIC_OPERANDS
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if (* syn == ' ')
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else
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{
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/* Syntax char didn't match. Can't be this insn. */
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/* FIXME: would like to return something like
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"expected char `c'" */
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return _("syntax error");
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static char msg [80];
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/* xgettext:c-format */
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sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
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*syn, *str);
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return msg;
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}
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continue;
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}
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{
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const char *start;
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CGEN_INSN_LIST *ilist;
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const char *tmp_errmsg = NULL;
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/* Skip leading white space. */
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while (isspace (* str))
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{
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const CGEN_INSN *insn = ilist->insn;
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#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
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#ifdef CGEN_VALIDATE_INSN_SUPPORTED
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/* not usually needed as unsupported opcodes shouldn't be in the hash lists */
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/* Is this insn supported by the selected cpu? */
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if (! fr30_cgen_insn_supported (cd, insn))
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continue;
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/* Allow parse/insert handlers to obtain length of insn. */
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CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
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if (! CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields))
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{
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/* ??? 0 is passed for `pc' */
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if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0)
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!= NULL)
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continue;
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/* It is up to the caller to actually output the insn and any
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queued relocs. */
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return insn;
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}
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tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
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if (tmp_errmsg != NULL)
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continue;
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/* Try the next entry. */
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/* ??? 0 is passed for `pc' */
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tmp_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
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(bfd_vma) 0);
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if (tmp_errmsg != NULL)
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continue;
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/* It is up to the caller to actually output the insn and any
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queued relocs. */
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return insn;
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}
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/* FIXME: We can return a better error message than this.
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Need to track why it failed and pick the right one. */
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/* Make sure we leave this with something at this point. */
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if (tmp_errmsg == NULL)
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tmp_errmsg = "unknown mnemonic";
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{
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static char errbuf[100];
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static char errbuf[150];
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#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
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/* if verbose error messages, use errmsg from CGEN_PARSE_FN */
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if (strlen (start) > 50)
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/* xgettext:c-format */
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sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
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else
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/* xgettext:c-format */
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sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
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#else
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if (strlen (start) > 50)
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/* xgettext:c-format */
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sprintf (errbuf, _("bad instruction `%.50s...'"), start);
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else
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/* xgettext:c-format */
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sprintf (errbuf, _("bad instruction `%.50s'"), start);
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#endif
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*errmsg = errbuf;
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return NULL;
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@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#include "fr30-desc.h"
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#include "fr30-opc.h"
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#include "opintl.h"
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#include "libiberty.h"
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/* Attributes. */
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@ -59,7 +60,7 @@ static const CGEN_ATTR_ENTRY ISA_attr[] =
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const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
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{
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{ "MACH", & MACH_attr[0] },
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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@ -71,7 +72,7 @@ const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
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const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
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{
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{ "MACH", & MACH_attr[0] },
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "PC", &bool_attr[0], &bool_attr[0] },
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@ -81,7 +82,7 @@ const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
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const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
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{
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{ "MACH", & MACH_attr[0] },
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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@ -96,7 +97,7 @@ const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
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const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
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{
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{ "MACH", & MACH_attr[0] },
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ALIAS", &bool_attr[0], &bool_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
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@ -114,130 +115,137 @@ const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
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/* Instruction set variants. */
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static const CGEN_ISA fr30_cgen_isa_table[] = {
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{ "fr30", 16, 16, 16, 48, },
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{ 0 }
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{ "fr30", 16, 16, 16, 48 },
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{ 0, 0, 0, 0, 0 }
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};
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/* Machine variants. */
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static const CGEN_MACH fr30_cgen_mach_table[] = {
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{ "fr30", "fr30", MACH_FR30 },
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{ 0 }
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{ 0, 0, 0 }
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};
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static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
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{
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{ "r0", 0 },
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{ "r1", 1 },
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{ "r2", 2 },
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{ "r3", 3 },
|
||||
{ "r4", 4 },
|
||||
{ "r5", 5 },
|
||||
{ "r6", 6 },
|
||||
{ "r7", 7 },
|
||||
{ "r8", 8 },
|
||||
{ "r9", 9 },
|
||||
{ "r10", 10 },
|
||||
{ "r11", 11 },
|
||||
{ "r12", 12 },
|
||||
{ "r13", 13 },
|
||||
{ "r14", 14 },
|
||||
{ "r15", 15 },
|
||||
{ "ac", 13 },
|
||||
{ "fp", 14 },
|
||||
{ "sp", 15 }
|
||||
{ "r0", 0, {0, {0}}, 0, 0 },
|
||||
{ "r1", 1, {0, {0}}, 0, 0 },
|
||||
{ "r2", 2, {0, {0}}, 0, 0 },
|
||||
{ "r3", 3, {0, {0}}, 0, 0 },
|
||||
{ "r4", 4, {0, {0}}, 0, 0 },
|
||||
{ "r5", 5, {0, {0}}, 0, 0 },
|
||||
{ "r6", 6, {0, {0}}, 0, 0 },
|
||||
{ "r7", 7, {0, {0}}, 0, 0 },
|
||||
{ "r8", 8, {0, {0}}, 0, 0 },
|
||||
{ "r9", 9, {0, {0}}, 0, 0 },
|
||||
{ "r10", 10, {0, {0}}, 0, 0 },
|
||||
{ "r11", 11, {0, {0}}, 0, 0 },
|
||||
{ "r12", 12, {0, {0}}, 0, 0 },
|
||||
{ "r13", 13, {0, {0}}, 0, 0 },
|
||||
{ "r14", 14, {0, {0}}, 0, 0 },
|
||||
{ "r15", 15, {0, {0}}, 0, 0 },
|
||||
{ "ac", 13, {0, {0}}, 0, 0 },
|
||||
{ "fp", 14, {0, {0}}, 0, 0 },
|
||||
{ "sp", 15, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_gr_names =
|
||||
{
|
||||
& fr30_cgen_opval_gr_names_entries[0],
|
||||
19
|
||||
19,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
|
||||
{
|
||||
{ "cr0", 0 },
|
||||
{ "cr1", 1 },
|
||||
{ "cr2", 2 },
|
||||
{ "cr3", 3 },
|
||||
{ "cr4", 4 },
|
||||
{ "cr5", 5 },
|
||||
{ "cr6", 6 },
|
||||
{ "cr7", 7 },
|
||||
{ "cr8", 8 },
|
||||
{ "cr9", 9 },
|
||||
{ "cr10", 10 },
|
||||
{ "cr11", 11 },
|
||||
{ "cr12", 12 },
|
||||
{ "cr13", 13 },
|
||||
{ "cr14", 14 },
|
||||
{ "cr15", 15 }
|
||||
{ "cr0", 0, {0, {0}}, 0, 0 },
|
||||
{ "cr1", 1, {0, {0}}, 0, 0 },
|
||||
{ "cr2", 2, {0, {0}}, 0, 0 },
|
||||
{ "cr3", 3, {0, {0}}, 0, 0 },
|
||||
{ "cr4", 4, {0, {0}}, 0, 0 },
|
||||
{ "cr5", 5, {0, {0}}, 0, 0 },
|
||||
{ "cr6", 6, {0, {0}}, 0, 0 },
|
||||
{ "cr7", 7, {0, {0}}, 0, 0 },
|
||||
{ "cr8", 8, {0, {0}}, 0, 0 },
|
||||
{ "cr9", 9, {0, {0}}, 0, 0 },
|
||||
{ "cr10", 10, {0, {0}}, 0, 0 },
|
||||
{ "cr11", 11, {0, {0}}, 0, 0 },
|
||||
{ "cr12", 12, {0, {0}}, 0, 0 },
|
||||
{ "cr13", 13, {0, {0}}, 0, 0 },
|
||||
{ "cr14", 14, {0, {0}}, 0, 0 },
|
||||
{ "cr15", 15, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_cr_names =
|
||||
{
|
||||
& fr30_cgen_opval_cr_names_entries[0],
|
||||
16
|
||||
16,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
|
||||
{
|
||||
{ "tbr", 0 },
|
||||
{ "rp", 1 },
|
||||
{ "ssp", 2 },
|
||||
{ "usp", 3 },
|
||||
{ "mdh", 4 },
|
||||
{ "mdl", 5 }
|
||||
{ "tbr", 0, {0, {0}}, 0, 0 },
|
||||
{ "rp", 1, {0, {0}}, 0, 0 },
|
||||
{ "ssp", 2, {0, {0}}, 0, 0 },
|
||||
{ "usp", 3, {0, {0}}, 0, 0 },
|
||||
{ "mdh", 4, {0, {0}}, 0, 0 },
|
||||
{ "mdl", 5, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_dr_names =
|
||||
{
|
||||
& fr30_cgen_opval_dr_names_entries[0],
|
||||
6
|
||||
6,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
|
||||
{
|
||||
{ "ps", 0 }
|
||||
{ "ps", 0, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_h_ps =
|
||||
{
|
||||
& fr30_cgen_opval_h_ps_entries[0],
|
||||
1
|
||||
1,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
|
||||
{
|
||||
{ "r13", 0 }
|
||||
{ "r13", 0, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_h_r13 =
|
||||
{
|
||||
& fr30_cgen_opval_h_r13_entries[0],
|
||||
1
|
||||
1,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
|
||||
{
|
||||
{ "r14", 0 }
|
||||
{ "r14", 0, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_h_r14 =
|
||||
{
|
||||
& fr30_cgen_opval_h_r14_entries[0],
|
||||
1
|
||||
1,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
|
||||
{
|
||||
{ "r15", 0 }
|
||||
{ "r15", 0, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD fr30_cgen_opval_h_r15 =
|
||||
{
|
||||
& fr30_cgen_opval_h_r15_entries[0],
|
||||
1
|
||||
1,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
|
||||
|
@ -273,7 +281,7 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
|
|||
{ "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ 0 }
|
||||
{ 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
|
||||
};
|
||||
|
||||
#undef A
|
||||
|
@ -285,6 +293,7 @@ const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
|
|||
const CGEN_IFLD fr30_cgen_ifld_table[] =
|
||||
{
|
||||
{ FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } } },
|
||||
{ FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } } },
|
||||
{ FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } } },
|
||||
|
@ -324,7 +333,7 @@ const CGEN_IFLD fr30_cgen_ifld_table[] =
|
|||
{ FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
|
||||
{ FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
|
||||
{ FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } } },
|
||||
{ 0 }
|
||||
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
|
||||
};
|
||||
|
||||
#undef A
|
||||
|
@ -483,7 +492,7 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
|
|||
/* ilm: interrupt level mask */
|
||||
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
|
||||
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
|
||||
{ 0 }
|
||||
{ 0, 0, 0, 0, 0, {0, {0}} }
|
||||
};
|
||||
|
||||
#undef A
|
||||
|
@ -498,7 +507,7 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
|
|||
/* Special null first entry.
|
||||
A `num' value of zero is thus invalid.
|
||||
Also, the special `invalid' insn resides here. */
|
||||
{ 0, 0, 0 },
|
||||
{ 0, 0, 0, 0, {0, {0}} },
|
||||
/* add $Rj,$Ri */
|
||||
{
|
||||
FR30_INSN_ADD, "add", "add", 16,
|
||||
|
@ -1446,9 +1455,11 @@ static void
|
|||
fr30_cgen_rebuild_tables (cd)
|
||||
CGEN_CPU_TABLE *cd;
|
||||
{
|
||||
int i,n_isas,n_machs;
|
||||
int i,n_isas;
|
||||
unsigned int isas = cd->isas;
|
||||
#if 0
|
||||
unsigned int machs = cd->machs;
|
||||
#endif
|
||||
|
||||
cd->int_insn_p = CGEN_INT_INSN_P;
|
||||
|
||||
|
@ -1490,6 +1501,7 @@ fr30_cgen_rebuild_tables (cd)
|
|||
++n_isas;
|
||||
}
|
||||
|
||||
#if 0 /* Does nothing?? */
|
||||
/* Data derived from the mach spec. */
|
||||
for (i = 0; i < MAX_MACHS; ++i)
|
||||
if (((1 << i) & machs) != 0)
|
||||
|
@ -1498,6 +1510,7 @@ fr30_cgen_rebuild_tables (cd)
|
|||
|
||||
++n_machs;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Determine which hw elements are used by MACH. */
|
||||
build_hw_table (cd);
|
||||
|
@ -1609,7 +1622,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
|
|||
cd->rebuild_tables = fr30_cgen_rebuild_tables;
|
||||
fr30_cgen_rebuild_tables (cd);
|
||||
|
||||
/* Initialise flags. */
|
||||
/* Default to not allowing signed overflow. */
|
||||
cd->signed_overflow_ok_p = 0;
|
||||
|
||||
return (CGEN_CPU_DESC) cd;
|
||||
|
|
|
@ -43,7 +43,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
|
||||
#define CGEN_INT_INSN_P 0
|
||||
|
||||
/* Maximum number of syntax bytes in an instruction. */
|
||||
/* Maximum nymber of syntax bytes in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 15
|
||||
|
||||
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||
|
@ -155,17 +155,17 @@ typedef enum cgen_ifld_attr {
|
|||
|
||||
/* Enum declaration for fr30 ifield types. */
|
||||
typedef enum ifield_type {
|
||||
FR30_F_NIL, FR30_F_OP1, FR30_F_OP2, FR30_F_OP3
|
||||
, FR30_F_OP4, FR30_F_OP5, FR30_F_CC, FR30_F_CCC
|
||||
, FR30_F_RJ, FR30_F_RI, FR30_F_RS1, FR30_F_RS2
|
||||
, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ, FR30_F_CRI
|
||||
, FR30_F_U4, FR30_F_U4C, FR30_F_I4, FR30_F_M4
|
||||
, FR30_F_U8, FR30_F_I8, FR30_F_I20_4, FR30_F_I20_16
|
||||
, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6, FR30_F_DISP8
|
||||
, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10, FR30_F_U10
|
||||
, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9, FR30_F_DIR10
|
||||
, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST, FR30_F_REGLIST_HI_LD
|
||||
, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
|
||||
FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
|
||||
, FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC
|
||||
, FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1
|
||||
, FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ
|
||||
, FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4
|
||||
, FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4
|
||||
, FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6
|
||||
, FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10
|
||||
, FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9
|
||||
, FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST
|
||||
, FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
|
||||
} IFIELD_TYPE;
|
||||
|
||||
#define MAX_IFLD ((int) FR30_F_MAX)
|
||||
|
|
|
@ -324,12 +324,21 @@ fr30_cgen_init_dis (cd)
|
|||
|
||||
static void
|
||||
print_normal (cd, dis_info, value, attrs, pc, length)
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
CGEN_CPU_DESC cd;
|
||||
#else
|
||||
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
PTR dis_info;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
bfd_vma pc;
|
||||
int length;
|
||||
#else
|
||||
bfd_vma pc ATTRIBUTE_UNUSED;
|
||||
int length ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
|
@ -350,12 +359,21 @@ print_normal (cd, dis_info, value, attrs, pc, length)
|
|||
|
||||
static void
|
||||
print_address (cd, dis_info, value, attrs, pc, length)
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
CGEN_CPU_DESC cd;
|
||||
#else
|
||||
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
PTR dis_info;
|
||||
bfd_vma value;
|
||||
unsigned int attrs;
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
bfd_vma pc;
|
||||
int length;
|
||||
#else
|
||||
bfd_vma pc ATTRIBUTE_UNUSED;
|
||||
int length ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
|
@ -380,11 +398,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
|
|||
|
||||
static void
|
||||
print_keyword (cd, dis_info, keyword_table, value, attrs)
|
||||
CGEN_CPU_DESC cd;
|
||||
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
|
||||
PTR dis_info;
|
||||
CGEN_KEYWORD *keyword_table;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
unsigned int attrs ATTRIBUTE_UNUSED;
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
const CGEN_KEYWORD_ENTRY *ke;
|
||||
|
@ -435,6 +453,48 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
|
|||
}
|
||||
}
|
||||
|
||||
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
|
||||
the extract info.
|
||||
Returns 0 if all is well, non-zero otherwise. */
|
||||
static int
|
||||
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
|
||||
CGEN_CPU_DESC cd;
|
||||
bfd_vma pc;
|
||||
disassemble_info *info;
|
||||
char *buf;
|
||||
int buflen;
|
||||
CGEN_EXTRACT_INFO *ex_info;
|
||||
unsigned long *insn_value;
|
||||
{
|
||||
int status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ex_info->dis_info = info;
|
||||
ex_info->valid = (1 << buflen) - 1;
|
||||
ex_info->insn_bytes = buf;
|
||||
|
||||
switch (buflen)
|
||||
{
|
||||
case 1:
|
||||
*insn_value = buf[0];
|
||||
break;
|
||||
case 2:
|
||||
*insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||||
break;
|
||||
case 4:
|
||||
*insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Utility to print an insn.
|
||||
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
|
||||
The result is the size of the insn in bytes or zero for an unknown insn
|
||||
|
@ -453,24 +513,9 @@ print_insn (cd, pc, info, buf, buflen)
|
|||
const CGEN_INSN_LIST *insn_list;
|
||||
CGEN_EXTRACT_INFO ex_info;
|
||||
|
||||
ex_info.dis_info = info;
|
||||
ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1;
|
||||
ex_info.insn_bytes = buf;
|
||||
|
||||
switch (buflen)
|
||||
{
|
||||
case 1:
|
||||
insn_value = buf[0];
|
||||
break;
|
||||
case 2:
|
||||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||||
break;
|
||||
case 4:
|
||||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
|
||||
/* The instructions are stored in hash lists.
|
||||
Pick the first one and keep trying until we find the right one. */
|
||||
|
@ -482,10 +527,14 @@ print_insn (cd, pc, info, buf, buflen)
|
|||
CGEN_FIELDS fields;
|
||||
int length;
|
||||
|
||||
#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
|
||||
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
|
||||
/* not needed as insn shouldn't be in hash lists if not supported */
|
||||
/* Supported by this cpu? */
|
||||
if (! fr30_cgen_insn_supported (cd, insn))
|
||||
continue;
|
||||
{
|
||||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Basic bit mask must be correct. */
|
||||
|
@ -498,6 +547,22 @@ print_insn (cd, pc, info, buf, buflen)
|
|||
machine insn and extracts the fields. The second pass prints
|
||||
them. */
|
||||
|
||||
#if CGEN_INT_INSN_P
|
||||
/* Make sure the entire insn is loaded into insn_value. */
|
||||
if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize)
|
||||
{
|
||||
unsigned long full_insn_value;
|
||||
int rc = read_insn (cd, pc, info, buf,
|
||||
CGEN_INSN_BITSIZE (insn) / 8,
|
||||
& ex_info, & full_insn_value);
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
length = CGEN_EXTRACT_FN (cd, insn)
|
||||
(cd, insn, &ex_info, full_insn_value, &fields, pc);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
length = CGEN_EXTRACT_FN (cd, insn)
|
||||
(cd, insn, &ex_info, insn_value, &fields, pc);
|
||||
/* length < 0 -> error */
|
||||
|
@ -556,7 +621,9 @@ print_insn_fr30 (pc, info)
|
|||
disassemble_info *info;
|
||||
{
|
||||
static CGEN_CPU_DESC cd = 0;
|
||||
static prev_isa,prev_mach,prev_endian;
|
||||
static int prev_isa;
|
||||
static int prev_mach;
|
||||
static int prev_endian;
|
||||
int length;
|
||||
int isa,mach;
|
||||
int endian = (info->endian == BFD_ENDIAN_BIG
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
|
||||
- the resultant file is machine generated, cgen-ibld.in isn't
|
||||
|
||||
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
|
||||
Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and GDB, the GNU debugger.
|
||||
|
||||
|
@ -57,6 +57,9 @@ static int extract_normal
|
|||
static int extract_insn_normal
|
||||
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
|
||||
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
|
||||
static void put_insn_int_value
|
||||
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
|
||||
|
||||
|
||||
/* Operand insertion. */
|
||||
|
||||
|
@ -183,9 +186,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
|
|||
if (length == 0)
|
||||
return NULL;
|
||||
|
||||
#if 0
|
||||
if (CGEN_INT_INSN_P
|
||||
&& word_offset != 0)
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (word_length > 32)
|
||||
abort ();
|
||||
|
@ -203,6 +208,7 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
|
|||
if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
|
||||
{
|
||||
unsigned long maxval = mask;
|
||||
|
||||
if ((unsigned long) value > maxval)
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
|
@ -214,15 +220,19 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
|
|||
}
|
||||
else
|
||||
{
|
||||
long minval = - (1L << (length - 1));
|
||||
long maxval = (1L << (length - 1)) - 1;
|
||||
if (value < minval || value > maxval)
|
||||
if (! cgen_signed_overflow_ok_p (cd))
|
||||
{
|
||||
sprintf
|
||||
/* xgettext:c-format */
|
||||
(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
|
||||
value, minval, maxval);
|
||||
return errbuf;
|
||||
long minval = - (1L << (length - 1));
|
||||
long maxval = (1L << (length - 1)) - 1;
|
||||
|
||||
if (value < minval || value > maxval)
|
||||
{
|
||||
sprintf
|
||||
/* xgettext:c-format */
|
||||
(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
|
||||
value, minval, maxval);
|
||||
return errbuf;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -232,9 +242,9 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
|
|||
int shift;
|
||||
|
||||
if (CGEN_INSN_LSB0_P)
|
||||
shift = (start + 1) - length;
|
||||
shift = (word_offset + start + 1) - length;
|
||||
else
|
||||
shift = word_length - (start + length);
|
||||
shift = total_length - (word_offset + start + length);
|
||||
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
|
||||
}
|
||||
|
||||
|
@ -278,7 +288,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
|
|||
|
||||
#if CGEN_INT_INSN_P
|
||||
|
||||
*buffer = value;
|
||||
put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
|
||||
CGEN_FIELDS_BITSIZE (fields), value);
|
||||
|
||||
#else
|
||||
|
||||
|
@ -308,6 +319,30 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
|
|||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Cover function to store an insn value into an integral insn. Must go here
|
||||
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
|
||||
|
||||
static void
|
||||
put_insn_int_value (cd, buf, length, insn_length, value)
|
||||
CGEN_CPU_DESC cd;
|
||||
CGEN_INSN_BYTES_PTR buf;
|
||||
int length;
|
||||
int insn_length;
|
||||
CGEN_INSN_INT value;
|
||||
{
|
||||
/* For architectures with insns smaller than the base-insn-bitsize,
|
||||
length may be too big. */
|
||||
if (length > insn_length)
|
||||
*buf = value;
|
||||
else
|
||||
{
|
||||
int shift = insn_length - length;
|
||||
/* Written this way to avoid undefined behaviour. */
|
||||
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||||
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
|
||||
}
|
||||
}
|
||||
|
||||
/* Operand extraction. */
|
||||
|
||||
|
@ -439,11 +474,19 @@ static int
|
|||
extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
||||
word_length, total_length, pc, valuep)
|
||||
CGEN_CPU_DESC cd;
|
||||
#if ! CGEN_INT_INSN_P
|
||||
CGEN_EXTRACT_INFO *ex_info;
|
||||
#else
|
||||
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
CGEN_INSN_INT insn_value;
|
||||
unsigned int attrs;
|
||||
unsigned int word_offset, start, length, word_length, total_length;
|
||||
#if ! CGEN_INT_INSN_P
|
||||
bfd_vma pc;
|
||||
#else
|
||||
bfd_vma pc ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
long *valuep;
|
||||
{
|
||||
CGEN_INSN_INT value;
|
||||
|
@ -456,9 +499,11 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
|||
return 1;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (CGEN_INT_INSN_P
|
||||
&& word_offset != 0)
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (word_length > 32)
|
||||
abort ();
|
||||
|
@ -474,15 +519,15 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
|||
|
||||
/* Does the value reside in INSN_VALUE? */
|
||||
|
||||
if (word_offset == 0)
|
||||
if (CGEN_INT_INSN_P || word_offset == 0)
|
||||
{
|
||||
/* Written this way to avoid undefined behaviour. */
|
||||
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||||
|
||||
if (CGEN_INSN_LSB0_P)
|
||||
value = insn_value >> ((start + 1) - length);
|
||||
value = insn_value >> ((word_offset + start + 1) - length);
|
||||
else
|
||||
value = insn_value >> (word_length - (start + length));
|
||||
value = insn_value >> (total_length - ( word_offset + start + length));
|
||||
value &= mask;
|
||||
/* sign extend? */
|
||||
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
|
||||
|
@ -858,7 +903,9 @@ fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
|
|||
case FR30_OPERAND_I20 :
|
||||
{
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & fields->f_i20_4);
|
||||
if (length <= 0) break;
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 16, 0, 16, 16, total_length, pc, & fields->f_i20_16);
|
||||
if (length <= 0) break;
|
||||
{
|
||||
FLD (f_i20) = ((((FLD (f_i20_4)) << (16))) | (FLD (f_i20_16)));
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
#include "symcat.h"
|
||||
#include "fr30-desc.h"
|
||||
#include "fr30-opc.h"
|
||||
#include "libiberty.h"
|
||||
|
||||
/* The hash functions are recorded here to help keep assembler code out of
|
||||
the disassembler and vice versa. */
|
||||
|
@ -42,123 +43,123 @@ static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
|
|||
#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
|
||||
|
||||
static const CGEN_IFMT ifmt_empty = {
|
||||
0, 0, 0x0, { 0 }
|
||||
0, 0, 0x0, { { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_add = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RJ) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_addi = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U4) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_add2 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_M4) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_div0s = {
|
||||
16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
|
||||
16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_div3 = {
|
||||
16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
|
||||
16, 16, 0xffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_OP4) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi8 = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi20 = {
|
||||
16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
|
||||
16, 32, 0xff00, { { F (F_OP1) }, { F (F_I20) }, { F (F_OP2) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi32 = {
|
||||
16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
|
||||
16, 48, 0xfff0, { { F (F_OP1) }, { F (F_I32) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldr14 = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP10) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldr14uh = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP9) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldr14ub = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP8) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldr15 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_UDISP6) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldr15dr = {
|
||||
16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
|
||||
16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RS2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_movdr = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS1) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_call = {
|
||||
16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
|
||||
16, 16, 0xf800, { { F (F_OP1) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_int = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_brad = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_CC) }, { F (F_REL9) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_dmovr13 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR10) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_dmovr13h = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR9) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_dmovr13b = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_copop = {
|
||||
16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
|
||||
16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_copld = {
|
||||
16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
|
||||
16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RJC) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_copst = {
|
||||
16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
|
||||
16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_RIC) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_addsp = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S10) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldm0 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_LD) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldm1 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_LD) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_stm0 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_ST) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_stm1 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_ST) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_enter = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U10) }, { 0 } }
|
||||
};
|
||||
|
||||
#undef F
|
||||
|
@ -175,7 +176,7 @@ static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] =
|
|||
/* Special null first entry.
|
||||
A `num' value of zero is thus invalid.
|
||||
Also, the special `invalid' insn resides here. */
|
||||
{ { 0 } },
|
||||
{ { 0, 0, 0, 0 }, {{0}}, 0, {0}},
|
||||
/* add $Rj,$Ri */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
|
@ -1178,15 +1179,15 @@ static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] =
|
|||
#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi8m = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi20m = {
|
||||
16, 32, 0xff00, { F (F_OP1), F (F_OP2), F (F_RI), F (F_I20), 0 }
|
||||
16, 32, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RI) }, { F (F_I20) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi32m = {
|
||||
16, 48, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), F (F_I32), 0 }
|
||||
16, 48, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { F (F_I32) }, { 0 } }
|
||||
};
|
||||
|
||||
#undef F
|
||||
|
|
|
@ -91,6 +91,7 @@ struct cgen_fields
|
|||
{
|
||||
int length;
|
||||
long f_nil;
|
||||
long f_anyof;
|
||||
long f_op1;
|
||||
long f_op2;
|
||||
long f_op3;
|
||||
|
|
|
@ -406,7 +406,7 @@ parse_insn_normal (cd, insn, strp, fields)
|
|||
first char after the mnemonic part is a space. */
|
||||
/* FIXME: We also take inappropriate advantage of the fact that
|
||||
GAS's input scrubber will remove extraneous blanks. */
|
||||
if (*str == CGEN_SYNTAX_CHAR (* syn))
|
||||
if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn)))
|
||||
{
|
||||
#ifdef CGEN_MNEMONIC_OPERANDS
|
||||
if (* syn == ' ')
|
||||
|
@ -418,9 +418,11 @@ parse_insn_normal (cd, insn, strp, fields)
|
|||
else
|
||||
{
|
||||
/* Syntax char didn't match. Can't be this insn. */
|
||||
/* FIXME: would like to return something like
|
||||
"expected char `c'" */
|
||||
return _("syntax error");
|
||||
static char msg [80];
|
||||
/* xgettext:c-format */
|
||||
sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
|
||||
*syn, *str);
|
||||
return msg;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
@ -486,7 +488,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
|
|||
{
|
||||
const char *start;
|
||||
CGEN_INSN_LIST *ilist;
|
||||
const char *tmp_errmsg;
|
||||
const char *tmp_errmsg = NULL;
|
||||
|
||||
/* Skip leading white space. */
|
||||
while (isspace (* str))
|
||||
|
@ -521,20 +523,25 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg)
|
|||
/* Allow parse/insert handlers to obtain length of insn. */
|
||||
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
||||
|
||||
if (!(tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields)))
|
||||
{
|
||||
/* ??? 0 is passed for `pc' */
|
||||
if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0)
|
||||
!= NULL)
|
||||
continue;
|
||||
/* It is up to the caller to actually output the insn and any
|
||||
queued relocs. */
|
||||
return insn;
|
||||
}
|
||||
tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
|
||||
if (tmp_errmsg != NULL)
|
||||
continue;
|
||||
|
||||
/* Try the next entry. */
|
||||
/* ??? 0 is passed for `pc' */
|
||||
tmp_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
|
||||
(bfd_vma) 0);
|
||||
if (tmp_errmsg != NULL)
|
||||
continue;
|
||||
|
||||
/* It is up to the caller to actually output the insn and any
|
||||
queued relocs. */
|
||||
return insn;
|
||||
}
|
||||
|
||||
/* Make sure we leave this with something at this point. */
|
||||
if (tmp_errmsg == NULL)
|
||||
tmp_errmsg = "unknown mnemonic";
|
||||
|
||||
{
|
||||
static char errbuf[150];
|
||||
|
||||
|
|
|
@ -32,6 +32,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
#include "m32r-desc.h"
|
||||
#include "m32r-opc.h"
|
||||
#include "opintl.h"
|
||||
#include "libiberty.h"
|
||||
|
||||
/* Attributes. */
|
||||
|
||||
|
@ -69,7 +70,7 @@ static const CGEN_ATTR_ENTRY PIPE_attr[] =
|
|||
|
||||
const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
|
||||
{
|
||||
{ "MACH", & MACH_attr[0] },
|
||||
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
|
||||
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
|
||||
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
|
||||
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
|
||||
|
@ -82,7 +83,7 @@ const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
|
|||
|
||||
const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
|
||||
{
|
||||
{ "MACH", & MACH_attr[0] },
|
||||
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
|
||||
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
|
||||
{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
|
||||
{ "PC", &bool_attr[0], &bool_attr[0] },
|
||||
|
@ -92,7 +93,7 @@ const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
|
|||
|
||||
const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
|
||||
{
|
||||
{ "MACH", & MACH_attr[0] },
|
||||
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
|
||||
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
|
||||
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
|
||||
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
|
||||
|
@ -108,8 +109,8 @@ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
|
|||
|
||||
const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
|
||||
{
|
||||
{ "MACH", & MACH_attr[0] },
|
||||
{ "PIPE", & PIPE_attr[0] },
|
||||
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
|
||||
{ "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
|
||||
{ "ALIAS", &bool_attr[0], &bool_attr[0] },
|
||||
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
|
||||
{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
|
||||
|
@ -128,8 +129,8 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
|
|||
/* Instruction set variants. */
|
||||
|
||||
static const CGEN_ISA m32r_cgen_isa_table[] = {
|
||||
{ "m32r", 32, 32, 16, 32, },
|
||||
{ 0 }
|
||||
{ "m32r", 32, 32, 16, 32 },
|
||||
{ 0, 0, 0, 0, 0 }
|
||||
};
|
||||
|
||||
/* Machine variants. */
|
||||
|
@ -137,81 +138,84 @@ static const CGEN_ISA m32r_cgen_isa_table[] = {
|
|||
static const CGEN_MACH m32r_cgen_mach_table[] = {
|
||||
{ "m32r", "m32r", MACH_M32R },
|
||||
{ "m32rx", "m32rx", MACH_M32RX },
|
||||
{ 0 }
|
||||
{ 0, 0, 0 }
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
|
||||
{
|
||||
{ "fp", 13 },
|
||||
{ "lr", 14 },
|
||||
{ "sp", 15 },
|
||||
{ "r0", 0 },
|
||||
{ "r1", 1 },
|
||||
{ "r2", 2 },
|
||||
{ "r3", 3 },
|
||||
{ "r4", 4 },
|
||||
{ "r5", 5 },
|
||||
{ "r6", 6 },
|
||||
{ "r7", 7 },
|
||||
{ "r8", 8 },
|
||||
{ "r9", 9 },
|
||||
{ "r10", 10 },
|
||||
{ "r11", 11 },
|
||||
{ "r12", 12 },
|
||||
{ "r13", 13 },
|
||||
{ "r14", 14 },
|
||||
{ "r15", 15 }
|
||||
{ "fp", 13, {0, {0}}, 0, 0 },
|
||||
{ "lr", 14, {0, {0}}, 0, 0 },
|
||||
{ "sp", 15, {0, {0}}, 0, 0 },
|
||||
{ "r0", 0, {0, {0}}, 0, 0 },
|
||||
{ "r1", 1, {0, {0}}, 0, 0 },
|
||||
{ "r2", 2, {0, {0}}, 0, 0 },
|
||||
{ "r3", 3, {0, {0}}, 0, 0 },
|
||||
{ "r4", 4, {0, {0}}, 0, 0 },
|
||||
{ "r5", 5, {0, {0}}, 0, 0 },
|
||||
{ "r6", 6, {0, {0}}, 0, 0 },
|
||||
{ "r7", 7, {0, {0}}, 0, 0 },
|
||||
{ "r8", 8, {0, {0}}, 0, 0 },
|
||||
{ "r9", 9, {0, {0}}, 0, 0 },
|
||||
{ "r10", 10, {0, {0}}, 0, 0 },
|
||||
{ "r11", 11, {0, {0}}, 0, 0 },
|
||||
{ "r12", 12, {0, {0}}, 0, 0 },
|
||||
{ "r13", 13, {0, {0}}, 0, 0 },
|
||||
{ "r14", 14, {0, {0}}, 0, 0 },
|
||||
{ "r15", 15, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD m32r_cgen_opval_gr_names =
|
||||
{
|
||||
& m32r_cgen_opval_gr_names_entries[0],
|
||||
19
|
||||
19,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
|
||||
{
|
||||
{ "psw", 0 },
|
||||
{ "cbr", 1 },
|
||||
{ "spi", 2 },
|
||||
{ "spu", 3 },
|
||||
{ "bpc", 6 },
|
||||
{ "bbpsw", 8 },
|
||||
{ "bbpc", 14 },
|
||||
{ "cr0", 0 },
|
||||
{ "cr1", 1 },
|
||||
{ "cr2", 2 },
|
||||
{ "cr3", 3 },
|
||||
{ "cr4", 4 },
|
||||
{ "cr5", 5 },
|
||||
{ "cr6", 6 },
|
||||
{ "cr7", 7 },
|
||||
{ "cr8", 8 },
|
||||
{ "cr9", 9 },
|
||||
{ "cr10", 10 },
|
||||
{ "cr11", 11 },
|
||||
{ "cr12", 12 },
|
||||
{ "cr13", 13 },
|
||||
{ "cr14", 14 },
|
||||
{ "cr15", 15 }
|
||||
{ "psw", 0, {0, {0}}, 0, 0 },
|
||||
{ "cbr", 1, {0, {0}}, 0, 0 },
|
||||
{ "spi", 2, {0, {0}}, 0, 0 },
|
||||
{ "spu", 3, {0, {0}}, 0, 0 },
|
||||
{ "bpc", 6, {0, {0}}, 0, 0 },
|
||||
{ "bbpsw", 8, {0, {0}}, 0, 0 },
|
||||
{ "bbpc", 14, {0, {0}}, 0, 0 },
|
||||
{ "cr0", 0, {0, {0}}, 0, 0 },
|
||||
{ "cr1", 1, {0, {0}}, 0, 0 },
|
||||
{ "cr2", 2, {0, {0}}, 0, 0 },
|
||||
{ "cr3", 3, {0, {0}}, 0, 0 },
|
||||
{ "cr4", 4, {0, {0}}, 0, 0 },
|
||||
{ "cr5", 5, {0, {0}}, 0, 0 },
|
||||
{ "cr6", 6, {0, {0}}, 0, 0 },
|
||||
{ "cr7", 7, {0, {0}}, 0, 0 },
|
||||
{ "cr8", 8, {0, {0}}, 0, 0 },
|
||||
{ "cr9", 9, {0, {0}}, 0, 0 },
|
||||
{ "cr10", 10, {0, {0}}, 0, 0 },
|
||||
{ "cr11", 11, {0, {0}}, 0, 0 },
|
||||
{ "cr12", 12, {0, {0}}, 0, 0 },
|
||||
{ "cr13", 13, {0, {0}}, 0, 0 },
|
||||
{ "cr14", 14, {0, {0}}, 0, 0 },
|
||||
{ "cr15", 15, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD m32r_cgen_opval_cr_names =
|
||||
{
|
||||
& m32r_cgen_opval_cr_names_entries[0],
|
||||
23
|
||||
23,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
|
||||
{
|
||||
{ "a0", 0 },
|
||||
{ "a1", 1 }
|
||||
{ "a0", 0, {0, {0}}, 0, 0 },
|
||||
{ "a1", 1, {0, {0}}, 0, 0 }
|
||||
};
|
||||
|
||||
CGEN_KEYWORD m32r_cgen_opval_h_accums =
|
||||
{
|
||||
& m32r_cgen_opval_h_accums_entries[0],
|
||||
2
|
||||
2,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
|
||||
|
@ -240,7 +244,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
|
|||
{ "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
||||
{ 0 }
|
||||
{ 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
|
||||
};
|
||||
|
||||
#undef A
|
||||
|
@ -277,7 +281,7 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
|
|||
{ M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
|
||||
{ M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
|
||||
{ M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
|
||||
{ 0 }
|
||||
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
|
||||
};
|
||||
|
||||
#undef A
|
||||
|
@ -367,7 +371,7 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
|
|||
/* accum: accumulator */
|
||||
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
|
||||
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
|
||||
{ 0 }
|
||||
{ 0, 0, 0, 0, 0, {0, {0}} }
|
||||
};
|
||||
|
||||
#undef A
|
||||
|
@ -382,7 +386,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
|
|||
/* Special null first entry.
|
||||
A `num' value of zero is thus invalid.
|
||||
Also, the special `invalid' insn resides here. */
|
||||
{ 0, 0, 0 },
|
||||
{ 0, 0, 0, 0, {0, {0}} },
|
||||
/* add $dr,$sr */
|
||||
{
|
||||
M32R_INSN_ADD, "add", "add", 16,
|
||||
|
@ -1175,9 +1179,11 @@ static void
|
|||
m32r_cgen_rebuild_tables (cd)
|
||||
CGEN_CPU_TABLE *cd;
|
||||
{
|
||||
int i,n_isas,n_machs;
|
||||
int i,n_isas;
|
||||
unsigned int isas = cd->isas;
|
||||
#if 0
|
||||
unsigned int machs = cd->machs;
|
||||
#endif
|
||||
|
||||
cd->int_insn_p = CGEN_INT_INSN_P;
|
||||
|
||||
|
@ -1219,6 +1225,7 @@ m32r_cgen_rebuild_tables (cd)
|
|||
++n_isas;
|
||||
}
|
||||
|
||||
#if 0 /* Does nothing?? */
|
||||
/* Data derived from the mach spec. */
|
||||
for (i = 0; i < MAX_MACHS; ++i)
|
||||
if (((1 << i) & machs) != 0)
|
||||
|
@ -1227,6 +1234,7 @@ m32r_cgen_rebuild_tables (cd)
|
|||
|
||||
++n_machs;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Determine which hw elements are used by MACH. */
|
||||
build_hw_table (cd);
|
||||
|
@ -1338,7 +1346,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
|
|||
cd->rebuild_tables = m32r_cgen_rebuild_tables;
|
||||
m32r_cgen_rebuild_tables (cd);
|
||||
|
||||
/* Initialise flags. */
|
||||
/* Default to not allowing signed overflow. */
|
||||
cd->signed_overflow_ok_p = 0;
|
||||
|
||||
return (CGEN_CPU_DESC) cd;
|
||||
|
|
|
@ -44,7 +44,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
|
||||
#define CGEN_INT_INSN_P 1
|
||||
|
||||
/* Maximum number of syntax bytes in an instruction. */
|
||||
/* Maximum nymber of syntax bytes in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 15
|
||||
|
||||
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||
|
|
|
@ -263,12 +263,21 @@ m32r_cgen_init_dis (cd)
|
|||
|
||||
static void
|
||||
print_normal (cd, dis_info, value, attrs, pc, length)
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
CGEN_CPU_DESC cd;
|
||||
#else
|
||||
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
PTR dis_info;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
bfd_vma pc;
|
||||
int length;
|
||||
#else
|
||||
bfd_vma pc ATTRIBUTE_UNUSED;
|
||||
int length ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
|
@ -289,12 +298,21 @@ print_normal (cd, dis_info, value, attrs, pc, length)
|
|||
|
||||
static void
|
||||
print_address (cd, dis_info, value, attrs, pc, length)
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
CGEN_CPU_DESC cd;
|
||||
#else
|
||||
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
PTR dis_info;
|
||||
bfd_vma value;
|
||||
unsigned int attrs;
|
||||
#ifdef CGEN_PRINT_NORMAL
|
||||
bfd_vma pc;
|
||||
int length;
|
||||
#else
|
||||
bfd_vma pc ATTRIBUTE_UNUSED;
|
||||
int length ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
|
@ -319,11 +337,11 @@ print_address (cd, dis_info, value, attrs, pc, length)
|
|||
|
||||
static void
|
||||
print_keyword (cd, dis_info, keyword_table, value, attrs)
|
||||
CGEN_CPU_DESC cd;
|
||||
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
|
||||
PTR dis_info;
|
||||
CGEN_KEYWORD *keyword_table;
|
||||
long value;
|
||||
unsigned int attrs;
|
||||
unsigned int attrs ATTRIBUTE_UNUSED;
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
const CGEN_KEYWORD_ENTRY *ke;
|
||||
|
@ -374,6 +392,48 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length)
|
|||
}
|
||||
}
|
||||
|
||||
/* Subroutine of print_insn. Reads an insn into the given buffers and updates
|
||||
the extract info.
|
||||
Returns 0 if all is well, non-zero otherwise. */
|
||||
static int
|
||||
read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
|
||||
CGEN_CPU_DESC cd;
|
||||
bfd_vma pc;
|
||||
disassemble_info *info;
|
||||
char *buf;
|
||||
int buflen;
|
||||
CGEN_EXTRACT_INFO *ex_info;
|
||||
unsigned long *insn_value;
|
||||
{
|
||||
int status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ex_info->dis_info = info;
|
||||
ex_info->valid = (1 << buflen) - 1;
|
||||
ex_info->insn_bytes = buf;
|
||||
|
||||
switch (buflen)
|
||||
{
|
||||
case 1:
|
||||
*insn_value = buf[0];
|
||||
break;
|
||||
case 2:
|
||||
*insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||||
break;
|
||||
case 4:
|
||||
*insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Utility to print an insn.
|
||||
BUF is the base part of the insn, target byte order, BUFLEN bytes long.
|
||||
The result is the size of the insn in bytes or zero for an unknown insn
|
||||
|
@ -392,24 +452,9 @@ print_insn (cd, pc, info, buf, buflen)
|
|||
const CGEN_INSN_LIST *insn_list;
|
||||
CGEN_EXTRACT_INFO ex_info;
|
||||
|
||||
ex_info.dis_info = info;
|
||||
ex_info.valid = (1 << (cd->base_insn_bitsize / 8)) - 1;
|
||||
ex_info.insn_bytes = buf;
|
||||
|
||||
switch (buflen)
|
||||
{
|
||||
case 1:
|
||||
insn_value = buf[0];
|
||||
break;
|
||||
case 2:
|
||||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
|
||||
break;
|
||||
case 4:
|
||||
insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
|
||||
/* The instructions are stored in hash lists.
|
||||
Pick the first one and keep trying until we find the right one. */
|
||||
|
@ -441,6 +486,22 @@ print_insn (cd, pc, info, buf, buflen)
|
|||
machine insn and extracts the fields. The second pass prints
|
||||
them. */
|
||||
|
||||
#if CGEN_INT_INSN_P
|
||||
/* Make sure the entire insn is loaded into insn_value. */
|
||||
if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize)
|
||||
{
|
||||
unsigned long full_insn_value;
|
||||
int rc = read_insn (cd, pc, info, buf,
|
||||
CGEN_INSN_BITSIZE (insn) / 8,
|
||||
& ex_info, & full_insn_value);
|
||||
if (rc != 0)
|
||||
return rc;
|
||||
length = CGEN_EXTRACT_FN (cd, insn)
|
||||
(cd, insn, &ex_info, full_insn_value, &fields, pc);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
length = CGEN_EXTRACT_FN (cd, insn)
|
||||
(cd, insn, &ex_info, insn_value, &fields, pc);
|
||||
/* length < 0 -> error */
|
||||
|
@ -499,7 +560,9 @@ print_insn_m32r (pc, info)
|
|||
disassemble_info *info;
|
||||
{
|
||||
static CGEN_CPU_DESC cd = 0;
|
||||
static prev_isa,prev_mach,prev_endian;
|
||||
static int prev_isa;
|
||||
static int prev_mach;
|
||||
static int prev_endian;
|
||||
int length;
|
||||
int isa,mach;
|
||||
int endian = (info->endian == BFD_ENDIAN_BIG
|
||||
|
|
|
@ -57,6 +57,9 @@ static int extract_normal
|
|||
static int extract_insn_normal
|
||||
PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
|
||||
CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
|
||||
static void cgen_put_insn_int_value
|
||||
PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT));
|
||||
|
||||
|
||||
/* Operand insertion. */
|
||||
|
||||
|
@ -183,9 +186,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
|
|||
if (length == 0)
|
||||
return NULL;
|
||||
|
||||
#if 0
|
||||
if (CGEN_INT_INSN_P
|
||||
&& word_offset != 0)
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (word_length > 32)
|
||||
abort ();
|
||||
|
@ -237,9 +242,9 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length,
|
|||
int shift;
|
||||
|
||||
if (CGEN_INSN_LSB0_P)
|
||||
shift = (start + 1) - length;
|
||||
shift = (word_offset + start + 1) - length;
|
||||
else
|
||||
shift = word_length - (start + length);
|
||||
shift = total_length - (word_offset + start + length);
|
||||
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
|
||||
}
|
||||
|
||||
|
@ -283,7 +288,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
|
|||
|
||||
#if CGEN_INT_INSN_P
|
||||
|
||||
*buffer = value;
|
||||
cgen_put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
|
||||
CGEN_FIELDS_BITSIZE (fields), value);
|
||||
|
||||
#else
|
||||
|
||||
|
@ -313,6 +319,30 @@ insert_insn_normal (cd, insn, fields, buffer, pc)
|
|||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Cover function to store an insn value into an integral insn. Must go here
|
||||
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
|
||||
|
||||
void
|
||||
cgen_put_insn_int_value (cd, buf, length, insn_length, value)
|
||||
CGEN_CPU_DESC cd;
|
||||
CGEN_INSN_BYTES_PTR buf;
|
||||
int length;
|
||||
int insn_length;
|
||||
CGEN_INSN_INT value;
|
||||
{
|
||||
/* For architectures with insns smaller than the base-insn-bitsize,
|
||||
length may be too big. */
|
||||
if (length > insn_length)
|
||||
*buf = value;
|
||||
else
|
||||
{
|
||||
int shift = insn_length - length;
|
||||
/* Written this way to avoid undefined behaviour. */
|
||||
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||||
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
|
||||
}
|
||||
}
|
||||
|
||||
/* Operand extraction. */
|
||||
|
||||
|
@ -444,11 +474,19 @@ static int
|
|||
extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
||||
word_length, total_length, pc, valuep)
|
||||
CGEN_CPU_DESC cd;
|
||||
#if ! CGEN_INT_INSN_P
|
||||
CGEN_EXTRACT_INFO *ex_info;
|
||||
#else
|
||||
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
CGEN_INSN_INT insn_value;
|
||||
unsigned int attrs;
|
||||
unsigned int word_offset, start, length, word_length, total_length;
|
||||
#if ! CGEN_INT_INSN_P
|
||||
bfd_vma pc;
|
||||
#else
|
||||
bfd_vma pc ATTRIBUTE_UNUSED;
|
||||
#endif
|
||||
long *valuep;
|
||||
{
|
||||
CGEN_INSN_INT value;
|
||||
|
@ -461,9 +499,11 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
|||
return 1;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (CGEN_INT_INSN_P
|
||||
&& word_offset != 0)
|
||||
abort ();
|
||||
#endif
|
||||
|
||||
if (word_length > 32)
|
||||
abort ();
|
||||
|
@ -479,15 +519,15 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length,
|
|||
|
||||
/* Does the value reside in INSN_VALUE? */
|
||||
|
||||
if (word_offset == 0)
|
||||
if (CGEN_INT_INSN_P || word_offset == 0)
|
||||
{
|
||||
/* Written this way to avoid undefined behaviour. */
|
||||
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
||||
|
||||
if (CGEN_INSN_LSB0_P)
|
||||
value = insn_value >> ((start + 1) - length);
|
||||
value = insn_value >> ((word_offset + start + 1) - length);
|
||||
else
|
||||
value = insn_value >> (word_length - (start + length));
|
||||
value = insn_value >> (total_length - ( word_offset + start + length));
|
||||
value &= mask;
|
||||
/* sign extend? */
|
||||
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
|
||||
|
|
|
@ -28,6 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
#include "symcat.h"
|
||||
#include "m32r-desc.h"
|
||||
#include "m32r-opc.h"
|
||||
#include "libiberty.h"
|
||||
|
||||
/* The hash functions are recorded here to help keep assembler code out of
|
||||
the disassembler and vice versa. */
|
||||
|
@ -42,131 +43,131 @@ static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
|
|||
#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
|
||||
|
||||
static const CGEN_IFMT ifmt_empty = {
|
||||
0, 0, 0x0, { 0 }
|
||||
0, 0, 0x0, { { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_add = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_add3 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_and3 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_or3 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_addi = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_addv3 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bc8 = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bc24 = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_beq = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_beqz = {
|
||||
32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
|
||||
32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_cmp = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_cmpi = {
|
||||
32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_cmpz = {
|
||||
16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_div = {
|
||||
32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_jc = {
|
||||
16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ld24 = {
|
||||
32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 }
|
||||
32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi16 = {
|
||||
32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_machi_a = {
|
||||
16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
|
||||
16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_mvfachi = {
|
||||
16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_mvfachi_a = {
|
||||
16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
|
||||
16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_mvfc = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_mvtachi = {
|
||||
16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_mvtachi_a = {
|
||||
16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
|
||||
16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_mvtc = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_nop = {
|
||||
16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_rac_dsi = {
|
||||
16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
|
||||
16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_seth = {
|
||||
32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 }
|
||||
32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_slli = {
|
||||
16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 }
|
||||
16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_st_d = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_trap = {
|
||||
16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 }
|
||||
16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_satb = {
|
||||
32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
|
||||
32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
#undef F
|
||||
|
@ -183,7 +184,7 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
|
|||
/* Special null first entry.
|
||||
A `num' value of zero is thus invalid.
|
||||
Also, the special `invalid' insn resides here. */
|
||||
{ { 0 } },
|
||||
{ { 0, 0, 0, 0 }, {{0}}, 0, {0}},
|
||||
/* add $dr,$sr */
|
||||
{
|
||||
{ 0, 0, 0, 0 },
|
||||
|
@ -1000,147 +1001,147 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
|
|||
#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
|
||||
|
||||
static const CGEN_IFMT ifmt_bc8r = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bc24r = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bl8r = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bl24r = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bcl8r = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bcl24r = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bnc8r = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bnc24r = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bra8r = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bra24r = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bncl8r = {
|
||||
16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
|
||||
16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_bncl24r = {
|
||||
32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
|
||||
32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ld_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ld_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldb_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldb_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldh_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldh_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldub_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldub_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_lduh_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_lduh_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_pop = {
|
||||
16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
|
||||
16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi8a = {
|
||||
16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
|
||||
16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_ldi16a = {
|
||||
32, 32, 0xf0ff0000, { F (F_OP1), F (F_OP2), F (F_R2), F (F_R1), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_rac_d = {
|
||||
16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
|
||||
16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_rac_ds = {
|
||||
16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
|
||||
16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_rach_d = {
|
||||
16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
|
||||
16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_rach_ds = {
|
||||
16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
|
||||
16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_st_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_st_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
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||||
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||||
static const CGEN_IFMT ifmt_stb_2 = {
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16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_stb_d2 = {
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||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
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||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
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||||
|
||||
static const CGEN_IFMT ifmt_sth_2 = {
|
||||
16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_sth_d2 = {
|
||||
32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 }
|
||||
32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
|
||||
};
|
||||
|
||||
static const CGEN_IFMT ifmt_push = {
|
||||
16, 16, 0xf0ff, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 }
|
||||
16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
|
||||
};
|
||||
|
||||
#undef F
|
||||
|
|
Loading…
Reference in New Issue