x86: correct VFPCLASSP{S,D} operand size handling
With AVX512VL disabled (e.g. when writing code for the Knights family of processors) these insns aren't ambiguous when used with a memory source, and hence should be accepted without suffix or operand size specifier. When AVX512VL is enabled, to be consistent with this as well as other ambiguous operand size handling it would seem better to just warn about the ambiguity in AT&T mode, and still default to 512-bit operands (on the assumption that the code may have been written without AVX512VL in mind yet), but it was requested to leave AT&T syntax mode alone here.
This commit is contained in:
Jan Beulich
parent
ddb56fe600
commit
6c0946d0d2
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@ -1,3 +1,14 @@
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (avx512): New (at file scope), moved from
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(check_VecOperands): ... here.
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(process_suffix): Add [XYZ]MMword operand size handling.
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* testsuite/gas/i386/avx512dq-inval.s: Add VFPCLASS tests.
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* testsuite/gas/i386/noavx512-2.s: Add Intel syntax VFPCLASS
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tests.
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* testsuite/gas/i386/avx512dq-inval.l,
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testsuite/gas/i386/noavx512-2.l: Adjust expectations.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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PR gas/24546
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@ -1840,6 +1840,8 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
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return x;
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}
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static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
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#define CPU_FLAGS_ARCH_MATCH 0x1
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#define CPU_FLAGS_64BIT_MATCH 0x2
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@ -5369,7 +5371,6 @@ check_VecOperands (const insn_template *t)
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{
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unsigned int op;
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i386_cpu_flags cpu;
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static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
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/* Templates allowing for ZMMword as well as YMMword and/or XMMword for
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any one operand are implicity requiring AVX512VL support if the actual
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@ -6445,7 +6446,7 @@ process_suffix (void)
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/* Accept FLDENV et al without suffix. */
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&& (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
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{
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unsigned int suffixes;
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unsigned int suffixes, evex = 0;
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suffixes = !i.tm.opcode_modifier.no_bsuf;
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if (!i.tm.opcode_modifier.no_wsuf)
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@ -6459,7 +6460,61 @@ process_suffix (void)
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if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
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suffixes |= 1 << 5;
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/* Are multiple suffixes allowed? */
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/* For [XYZ]MMWORD operands inspect operand sizes. While generally
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also suitable for AT&T syntax mode, it was requested that this be
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restricted to just Intel syntax. */
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if (intel_syntax)
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{
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i386_cpu_flags cpu = cpu_flags_and (i.tm.cpu_flags, avx512);
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if (!cpu_flags_all_zero (&cpu) && !i.broadcast)
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{
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unsigned int op;
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for (op = 0; op < i.tm.operands; ++op)
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{
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if (!cpu_arch_flags.bitfield.cpuavx512vl)
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{
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if (i.tm.operand_types[op].bitfield.ymmword)
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i.tm.operand_types[op].bitfield.xmmword = 0;
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if (i.tm.operand_types[op].bitfield.zmmword)
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i.tm.operand_types[op].bitfield.ymmword = 0;
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if (!i.tm.opcode_modifier.evex
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|| i.tm.opcode_modifier.evex == EVEXDYN)
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i.tm.opcode_modifier.evex = EVEX512;
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}
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if (i.tm.operand_types[op].bitfield.xmmword
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+ i.tm.operand_types[op].bitfield.ymmword
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+ i.tm.operand_types[op].bitfield.zmmword < 2)
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continue;
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/* Any properly sized operand disambiguates the insn. */
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if (i.types[op].bitfield.xmmword
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|| i.types[op].bitfield.ymmword
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|| i.types[op].bitfield.zmmword)
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{
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suffixes &= ~(7 << 6);
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evex = 0;
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break;
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}
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if ((i.flags[op] & Operand_Mem)
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&& i.tm.operand_types[op].bitfield.unspecified)
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{
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if (i.tm.operand_types[op].bitfield.xmmword)
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suffixes |= 1 << 6;
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if (i.tm.operand_types[op].bitfield.ymmword)
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suffixes |= 1 << 7;
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if (i.tm.operand_types[op].bitfield.zmmword)
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suffixes |= 1 << 8;
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evex = EVEX512;
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}
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}
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}
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}
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/* Are multiple suffixes / operand sizes allowed? */
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if (suffixes & (suffixes - 1))
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{
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if (intel_syntax
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@ -6485,6 +6540,8 @@ process_suffix (void)
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if (i.tm.opcode_modifier.floatmf)
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i.suffix = SHORT_MNEM_SUFFIX;
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else if (evex)
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i.tm.opcode_modifier.evex = evex;
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else if (flag_code == CODE_16BIT)
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i.suffix = WORD_MNEM_SUFFIX;
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else if (!i.tm.opcode_modifier.no_lsuf)
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@ -11,3 +11,7 @@
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.*:[0-9]*: Error:.* `vpinsrq' .*
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.*:[0-9]*: Error:.* `vpinsrq' .*
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.*:[0-9]*: Error:.* `vpinsrq' .*
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.*:[0-9]*: Error:.* `vfpclasspd'
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.*:[0-9]*: Error:.* `vfpclassps'
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.*:[0-9]*: Error:.* `vfpclasspd'
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.*:[0-9]*: Error:.* `vfpclassps'
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@ -1,4 +1,4 @@
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# Check AVX512DQ instructions not to be accepted outside of 64-bit mode
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# Check AVX512DQ instructions not to be accepted (in part only outside of 64-bit mode)
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.text
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_start:
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@ -20,3 +20,10 @@ _start:
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vpinsrq xmm0, xmm0, qword ptr [eax], 0
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{evex} vpinsrq xmm0, xmm0, qword ptr [eax], 0
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vfpclasspd k0, [eax], 0
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vfpclassps k0, [eax], 0
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.att_syntax prefix
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vfpclasspd $0, (%eax), %k0
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vfpclassps $0, (%eax), %k0
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@ -101,5 +101,10 @@ GAS LISTING .*
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[ ]*50[ ]+F5
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[ ]*51[ ]+\?\?\?\? 660F58F4 addpd %xmm4, %xmm6
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[ ]*52[ ]+
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[ ]*53[ ]+\?\?\?\? 0F1F00 \.p2align 4
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[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F3FD48 vfpclasspd k0, \[eax], 0
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[ ]*[1-9][0-9]*[ ]+660000
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F37D48 vfpclassps k0, \[eax], 0
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[ ]*[1-9][0-9]*[ ]+660000
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[ ]*[1-9][0-9]*[ ]+
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#pass
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@ -50,4 +50,8 @@
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pabsb %xmm5, %xmm6
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addpd %xmm4, %xmm6
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.intel_syntax noprefix
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vfpclasspd k0, [eax], 0
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vfpclassps k0, [eax], 0
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.p2align 4
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@ -1,3 +1,9 @@
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
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with Unspecified, making the present one AT&T syntax only.
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* i386-tbl.h: Re-generate.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
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@ -4515,12 +4515,14 @@ vextracti64x2, 3, 0x6639, None, 1, CpuAVX512DQ, Modrm|MaskingMorZ|VexOpcode=2|Ve
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vinsertf64x2, 4, 0x6618, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
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vinserti64x2, 4, 0x6638, None, 1, CpuAVX512DQ, Modrm|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
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vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask }
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vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|BaseIndex, RegMask }
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vfpclasspd, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegMask }
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vfpclasspdz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|Unspecified|BaseIndex, RegMask }
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vfpclasspdx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegMask }
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vfpclasspdy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=2|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Qword|Unspecified|BaseIndex, RegMask }
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vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask }
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vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|BaseIndex, RegMask }
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vfpclassps, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegMask }
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vfpclasspsz, 3, 0x6666, None, 1, CpuAVX512DQ, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Dword|Unspecified|BaseIndex, RegMask }
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vfpclasspsx, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegMask }
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vfpclasspsy, 3, 0x6666, None, 1, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Dword|Unspecified|BaseIndex, RegMask }
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@ -56801,13 +56801,29 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2,
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0, 0, 0, 0, 0, 2, 4, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0 },
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0, 0, 0, 0, 0, 2, 4, 0, 0, 7, 0, 0, 0, 0, 1, 0, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
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0, 1, 1, 1, 0, 0 } },
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{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "vfpclasspd", 0x6666, None, 1, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2,
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0, 0, 0, 0, 0, 2, 4, 0, 0, 7, 0, 0, 0, 0, 0, 1, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1,
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0, 1, 1, 1, 1, 0 } },
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{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "vfpclasspdz", 0x6666, None, 1, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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@ -56865,13 +56881,29 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
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0, 0, 0, 0, 0, 2, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0 },
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0, 0, 0, 0, 0, 2, 3, 0, 0, 7, 0, 0, 0, 0, 1, 0, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0,
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0, 1, 1, 1, 0, 0 } },
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{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "vfpclassps", 0x6666, None, 1, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
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0, 0, 0, 0, 0, 2, 3, 0, 0, 7, 0, 0, 0, 0, 0, 1, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0,
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0, 1, 1, 1, 1, 0 } },
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{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "vfpclasspsz", 0x6666, None, 1, 3,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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Reference in New Issue