* gas/tic80/{regops2.d, regops2.lst, regops2.s, regops3.d,
regops3.lst, regops3.s, regops4.d, regops4.lst, regops4.s}: New tests for :m and :s operand modifiers. * gas/tic80/tic80.exp: Run the regops2, regops3, and regops4 tests.
This commit is contained in:
Fred Fish
parent
6757ae582b
commit
6c24f9c190
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@ -1,3 +1,12 @@
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start-sanitize-tic80
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Wed Feb 26 15:16:04 1997 Fred Fish <fnf@cygnus.com>
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* gas/tic80/{regops2.d, regops2.lst, regops2.s, regops3.d,
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regops3.lst, regops3.s, regops4.d, regops4.lst, regops4.s}:
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New tests for :m and :s operand modifiers.
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* gas/tic80/tic80.exp: Run the regops2, regops3, and regops4 tests.
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end-sanitize-tic80
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Tue Feb 25 13:45:55 1997 Ian Lance Taylor <ian@cygnus.com>
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* gas/macros/semi.s: Force the final alignment to use a fill value
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@ -0,0 +1,92 @@
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#objdump: -d
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#name: TIc80 register operands with :m modifier
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.*: +file format .*tic80.*
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Disassembly of section .text:
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00000000 <.text>:
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0: 08 80 b7 02.*
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||||
4: 04 00 9e 02.*
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||||
8: fc 7f 9e 02.*
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||||
c: 00 90 b7 02.*
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||||
10: 78 56 34 12.*
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||||
14: 00 90 b7 02.*
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18: ef be ad de.*
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1c: 08 80 b7 0a.*
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||||
20: 04 00 9e 0a.*
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24: fc 7f 9e 0a.*
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28: 00 90 b7 0a.*
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2c: 78 56 34 12.*
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30: 00 90 b7 0a.*
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34: ef be ad de.*
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38: 04 84 b4 41.*
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3c: 04 a4 b4 41.*
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40: 04 c4 b4 41.*
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44: 04 e4 b4 41.*
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48: 00 94 b4 41.*
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4c: 00 00 00 e0.*
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50: 00 b4 b4 41.*
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54: 00 00 00 e0.*
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58: 00 d4 b4 41.*
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5c: 00 00 00 e0.*
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60: 00 f4 b4 41.*
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64: 00 00 00 e0.*
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68: 04 84 b5 41.*
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6c: 04 a4 b5 41.*
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70: 00 94 b5 41.*
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74: 00 00 00 e0.*
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78: 00 b4 b5 41.*
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7c: 00 00 00 e0.*
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80: 04 84 b6 41.*
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84: 04 a4 b6 41.*
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88: 04 c4 b6 41.*
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8c: 04 e4 b6 41.*
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90: 00 94 b6 41.*
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94: 00 00 00 e0.*
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98: 00 b4 b6 41.*
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9c: 00 00 00 e0.*
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a0: 00 d4 b6 41.*
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a4: 00 00 00 e0.*
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a8: 00 f4 b6 41.*
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ac: 00 00 00 e0.*
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b0: 04 80 b4 41.*
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b4: 04 a0 b4 41.*
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b8: 04 c0 b4 41.*
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bc: 04 e0 b4 41.*
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c0: f0 7f 92 41.*
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c4: f0 ff 92 41.*
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c8: f0 7f 93 41.*
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cc: f0 ff 93 41.*
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d0: 00 90 b4 41.*
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d4: 00 00 00 e0.*
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d8: 00 b0 b4 41.*
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dc: 00 00 00 e0.*
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e0: 00 d0 b4 41.*
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e4: 00 00 00 e0.*
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e8: 00 f0 b4 41.*
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ec: 00 00 00 e0.*
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f0: 04 80 b5 41.*
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f4: 04 a0 b5 41.*
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f8: f0 7f 96 41.*
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fc: f0 ff 96 41.*
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100: 00 90 b5 41.*
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104: 00 00 00 e0.*
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108: 00 b0 b5 41.*
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10c: 00 00 00 e0.*
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110: 04 80 b6 41.*
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114: 04 a0 b6 41.*
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118: 04 c0 b6 41.*
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11c: 04 e0 b6 41.*
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120: 00 7f 9a 41.*
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124: 00 ff 9a 41.*
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128: 00 7f 9b 41.*
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12c: 00 ff 9b 41.*
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130: 00 90 b6 41.*
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134: 00 00 00 e0.*
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138: 00 b0 b6 41.*
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13c: 00 00 00 e0.*
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140: 00 d0 b6 41.*
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144: 00 00 00 e0.*
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148: 00 f0 b6 41.*
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14c: 00 00 00 e0.*
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@ -0,0 +1,96 @@
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MVP MP Macro Assembler Version 1.13 Wed Feb 26 14:32:14 1997
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Copyright (c) 1993-1995 Texas Instruments Incorporated
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regops2.s PAGE 1
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1 00000000 02B78008 dcachec r8(r10:m) ; Register form (modified)
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2 00000004 029E0004 dcachec 4(r10:m) ; Short Immediate form (positive offset) (modified)
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3 00000008 029E7FFC dcachec -4(r10:m) ; Short Immediate form (negative offset) (modified)
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4 0000000C 02B79000 dcachec 0x12345678(r10:m) ; Long Immediate form (positive offset) (modified)
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00000010 12345678
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5 00000014 02B79000 dcachec 0xDEADBEEF(r10:m) ; Long Immediate form (negative offset) (modified)
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00000018 DEADBEEF
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6 0000001C 0AB78008 dcachef r8(r10:m) ; Register form (modified)
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7 00000020 0A9E0004 dcachef 4(r10:m) ; Short Immediate form (positive offset) (modified)
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8 00000024 0A9E7FFC dcachef -4(r10:m) ; Short Immediate form (negative offset) (modified)
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9 00000028 0AB79000 dcachef 0x12345678(r10:m) ; Long Immediate form (positive offset) (modified)
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0000002C 12345678
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10 00000030 0AB79000 dcachef 0xDEADBEEF(r10:m) ; Long Immediate form (negative offset) (modified)
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00000034 DEADBEEF
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11 00000038 41B48404 dld.b r4(r6:m),r8 ; Register form
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12 0000003C 41B4A404 dld.h r4(r6:m),r8 ; Register form
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13 00000040 41B4C404 dld r4(r6:m),r8 ; Register form
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14 00000044 41B4E404 dld.d r4(r6:m),r8 ; Register form
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15 00000048 41B49400 dld.b 0xE0000000(r6:m),r8 ; Long Immediate form
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0000004C E0000000
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16 00000050 41B4B400 dld.h 0xE0000000(r6:m),r8 ; Long Immediate form
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00000054 E0000000
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17 00000058 41B4D400 dld 0xE0000000(r6:m),r8 ; Long Immediate form
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0000005C E0000000
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18 00000060 41B4F400 dld.d 0xE0000000(r6:m),r8 ; Long Immediate form
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00000064 E0000000
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19 00000068 41B58404 dld.ub r4(r6:m),r8 ; Register form
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20 0000006C 41B5A404 dld.uh r4(r6:m),r8 ; Register form
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21 00000070 41B59400 dld.ub 0xE0000000(r6:m),r8 ; Long Immediate form
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00000074 E0000000
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22 00000078 41B5B400 dld.uh 0xE0000000(r6:m),r8 ; Long Immediate form
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0000007C E0000000
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23 00000080 41B68404 dst.b r4(r6:m),r8 ; Register form
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24 00000084 41B6A404 dst.h r4(r6:m),r8 ; Register form
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25 00000088 41B6C404 dst r4(r6:m),r8 ; Register form
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26 0000008C 41B6E404 dst.d r4(r6:m),r8 ; Register form
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27 00000090 41B69400 dst.b 0xE0000000(r6:m),r8 ; Long Immediate form
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00000094 E0000000
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28 00000098 41B6B400 dst.h 0xE0000000(r6:m),r8 ; Long Immediate form
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0000009C E0000000
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29 000000A0 41B6D400 dst 0xE0000000(r6:m),r8 ; Long Immediate form
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000000A4 E0000000
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30 000000A8 41B6F400 dst.d 0xE0000000(r6:m),r8 ; Long Immediate form
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000000AC E0000000
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31 000000B0 41B48004 ld.b r4(r6:m),r8 ; Register form
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32 000000B4 41B4A004 ld.h r4(r6:m),r8 ; Register form
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33 000000B8 41B4C004 ld r4(r6:m),r8 ; Register form
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34 000000BC 41B4E004 ld.d r4(r6:m),r8 ; Register form
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35 000000C0 41927FF0 ld.b -16(r6:m),r8 ; Short Immediate form
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36 000000C4 4192FFF0 ld.h -16(r6:m),r8 ; Short Immediate form
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37 000000C8 41937FF0 ld -16(r6:m),r8 ; Short Immediate form
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38 000000CC 4193FFF0 ld.d -16(r6:m),r8 ; Short Immediate form
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39 000000D0 41B49000 ld.b 0xE0000000(r6:m),r8 ; Long Immediate form
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000000D4 E0000000
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40 000000D8 41B4B000 ld.h 0xE0000000(r6:m),r8 ; Long Immediate form
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MVP MP Macro Assembler Version 1.13 Wed Feb 26 14:32:14 1997
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Copyright (c) 1993-1995 Texas Instruments Incorporated
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regops2.s PAGE 2
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000000DC E0000000
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41 000000E0 41B4D000 ld 0xE0000000(r6:m),r8 ; Long Immediate form
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000000E4 E0000000
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42 000000E8 41B4F000 ld.d 0xE0000000(r6:m),r8 ; Long Immediate form
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000000EC E0000000
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43 000000F0 41B58004 ld.ub r4(r6:m),r8 ; Register form
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44 000000F4 41B5A004 ld.uh r4(r6:m),r8 ; Register form
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45 000000F8 41967FF0 ld.ub -16(r6:m),r8 ; Short Immediate form
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46 000000FC 4196FFF0 ld.uh -16(r6:m),r8 ; Short Immediate form
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47 00000100 41B59000 ld.ub 0xE0000000(r6:m),r8 ; Long Immediate form
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00000104 E0000000
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48 00000108 41B5B000 ld.uh 0xE0000000(r6:m),r8 ; Long Immediate form
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0000010C E0000000
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49 00000110 41B68004 st.b r4(r6:m),r8 ; Register form
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50 00000114 41B6A004 st.h r4(r6:m),r8 ; Register form
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51 00000118 41B6C004 st r4(r6:m),r8 ; Register form
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52 0000011C 41B6E004 st.d r4(r6:m),r8 ; Register form
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53 00000120 419A7F00 st.b -256(r6:m),r8 ; Short Immediate form
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54 00000124 419AFF00 st.h -256(r6:m),r8 ; Short Immediate form
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55 00000128 419B7F00 st -256(r6:m),r8 ; Short Immediate form
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56 0000012C 419BFF00 st.d -256(r6:m),r8 ; Short Immediate form
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57 00000130 41B69000 st.b 0xE0000000(r6:m),r8 ; Long Immediate form
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00000134 E0000000
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58 00000138 41B6B000 st.h 0xE0000000(r6:m),r8 ; Long Immediate form
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0000013C E0000000
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59 00000140 41B6D000 st 0xE0000000(r6:m),r8 ; Long Immediate form
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00000144 E0000000
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60 00000148 41B6F000 st.d 0xE0000000(r6:m),r8 ; Long Immediate form
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0000014C E0000000
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No Errors, No Warnings
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@ -0,0 +1,60 @@
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dcachec r8(r10:m) ; Register form (modified)
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dcachec 4(r10:m) ; Short Immediate form (positive offset) (modified)
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dcachec -4(r10:m) ; Short Immediate form (negative offset) (modified)
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dcachec 0x12345678(r10:m) ; Long Immediate form (positive offset) (modified)
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dcachec 0xDEADBEEF(r10:m) ; Long Immediate form (negative offset) (modified)
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dcachef r8(r10:m) ; Register form (modified)
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dcachef 4(r10:m) ; Short Immediate form (positive offset) (modified)
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dcachef -4(r10:m) ; Short Immediate form (negative offset) (modified)
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dcachef 0x12345678(r10:m) ; Long Immediate form (positive offset) (modified)
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dcachef 0xDEADBEEF(r10:m) ; Long Immediate form (negative offset) (modified)
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dld.b r4(r6:m),r8 ; Register form
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dld.h r4(r6:m),r8 ; Register form
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dld r4(r6:m),r8 ; Register form
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dld.d r4(r6:m),r8 ; Register form
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dld.b 0xE0000000(r6:m),r8 ; Long Immediate form
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dld.h 0xE0000000(r6:m),r8 ; Long Immediate form
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dld 0xE0000000(r6:m),r8 ; Long Immediate form
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dld.d 0xE0000000(r6:m),r8 ; Long Immediate form
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dld.ub r4(r6:m),r8 ; Register form
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dld.uh r4(r6:m),r8 ; Register form
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dld.ub 0xE0000000(r6:m),r8 ; Long Immediate form
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dld.uh 0xE0000000(r6:m),r8 ; Long Immediate form
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dst.b r4(r6:m),r8 ; Register form
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dst.h r4(r6:m),r8 ; Register form
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dst r4(r6:m),r8 ; Register form
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dst.d r4(r6:m),r8 ; Register form
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dst.b 0xE0000000(r6:m),r8 ; Long Immediate form
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dst.h 0xE0000000(r6:m),r8 ; Long Immediate form
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dst 0xE0000000(r6:m),r8 ; Long Immediate form
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dst.d 0xE0000000(r6:m),r8 ; Long Immediate form
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ld.b r4(r6:m),r8 ; Register form
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ld.h r4(r6:m),r8 ; Register form
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ld r4(r6:m),r8 ; Register form
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ld.d r4(r6:m),r8 ; Register form
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ld.b -16(r6:m),r8 ; Short Immediate form
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ld.h -16(r6:m),r8 ; Short Immediate form
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ld -16(r6:m),r8 ; Short Immediate form
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ld.d -16(r6:m),r8 ; Short Immediate form
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ld.b 0xE0000000(r6:m),r8 ; Long Immediate form
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ld.h 0xE0000000(r6:m),r8 ; Long Immediate form
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ld 0xE0000000(r6:m),r8 ; Long Immediate form
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ld.d 0xE0000000(r6:m),r8 ; Long Immediate form
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ld.ub r4(r6:m),r8 ; Register form
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ld.uh r4(r6:m),r8 ; Register form
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ld.ub -16(r6:m),r8 ; Short Immediate form
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ld.uh -16(r6:m),r8 ; Short Immediate form
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ld.ub 0xE0000000(r6:m),r8 ; Long Immediate form
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ld.uh 0xE0000000(r6:m),r8 ; Long Immediate form
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st.b r4(r6:m),r8 ; Register form
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st.h r4(r6:m),r8 ; Register form
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st r4(r6:m),r8 ; Register form
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st.d r4(r6:m),r8 ; Register form
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st.b -256(r6:m),r8 ; Short Immediate form
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st.h -256(r6:m),r8 ; Short Immediate form
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st -256(r6:m),r8 ; Short Immediate form
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st.d -256(r6:m),r8 ; Short Immediate form
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st.b 0xE0000000(r6:m),r8 ; Long Immediate form
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st.h 0xE0000000(r6:m),r8 ; Long Immediate form
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st 0xE0000000(r6:m),r8 ; Long Immediate form
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st.d 0xE0000000(r6:m),r8 ; Long Immediate form
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@ -0,0 +1,28 @@
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#objdump: -d
|
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#name: TIc80 register operands with :s modifier
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.*: +file format .*tic80.*
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Disassembly of section .text:
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00000000 <.text>:
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0: 04 0c b4 41.*
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4: 04 2c b4 41.*
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8: 04 4c b4 41.*
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c: 04 6c b4 41.*
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10: 04 0c b5 41.*
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14: 04 2c b5 41.*
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18: 04 0c b6 41.*
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1c: 04 2c b6 41.*
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20: 04 4c b6 41.*
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24: 04 6c b6 41.*
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28: 04 08 b4 41.*
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2c: 04 28 b4 41.*
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30: 04 48 b4 41.*
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34: 04 68 b4 41.*
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38: 04 08 b5 41.*
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3c: 04 28 b5 41.*
|
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40: 04 08 b6 41.*
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44: 04 28 b6 41.*
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48: 04 48 b6 41.*
|
||||
4c: 04 68 b6 41.*
|
||||
|
|
@ -0,0 +1,27 @@
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MVP MP Macro Assembler Version 1.13 Wed Feb 26 14:32:19 1997
|
||||
Copyright (c) 1993-1995 Texas Instruments Incorporated
|
||||
|
||||
regops3.s PAGE 1
|
||||
|
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1 00000000 41B40C04 dld.b r4:s(r6),r8 ; Register form
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2 00000004 41B42C04 dld.h r4:s(r6),r8 ; Register form
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||||
3 00000008 41B44C04 dld r4:s(r6),r8 ; Register form
|
||||
4 0000000C 41B46C04 dld.d r4:s(r6),r8 ; Register form
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||||
5 00000010 41B50C04 dld.ub r4:s(r6),r8 ; Register form
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||||
6 00000014 41B52C04 dld.uh r4:s(r6),r8 ; Register form
|
||||
7 00000018 41B60C04 dst.b r4:s(r6),r8 ; Register form
|
||||
8 0000001C 41B62C04 dst.h r4:s(r6),r8 ; Register form
|
||||
9 00000020 41B64C04 dst r4:s(r6),r8 ; Register form
|
||||
10 00000024 41B66C04 dst.d r4:s(r6),r8 ; Register form
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||||
11 00000028 41B40804 ld.b r4:s(r6),r8 ; Register form
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12 0000002C 41B42804 ld.h r4:s(r6),r8 ; Register form
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||||
13 00000030 41B44804 ld r4:s(r6),r8 ; Register form
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||||
14 00000034 41B46804 ld.d r4:s(r6),r8 ; Register form
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15 00000038 41B50804 ld.ub r4:s(r6),r8 ; Register form
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16 0000003C 41B52804 ld.uh r4:s(r6),r8 ; Register form
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17 00000040 41B60804 st.b r4:s(r6),r8 ; Register form
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18 00000044 41B62804 st.h r4:s(r6),r8 ; Register form
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19 00000048 41B64804 st r4:s(r6),r8 ; Register form
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20 0000004C 41B66804 st.d r4:s(r6),r8 ; Register form
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No Errors, No Warnings
|
||||
|
|
@ -0,0 +1,20 @@
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dld.b r4:s(r6),r8 ; Register form
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||||
dld.h r4:s(r6),r8 ; Register form
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||||
dld r4:s(r6),r8 ; Register form
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dld.d r4:s(r6),r8 ; Register form
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||||
dld.ub r4:s(r6),r8 ; Register form
|
||||
dld.uh r4:s(r6),r8 ; Register form
|
||||
dst.b r4:s(r6),r8 ; Register form
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||||
dst.h r4:s(r6),r8 ; Register form
|
||||
dst r4:s(r6),r8 ; Register form
|
||||
dst.d r4:s(r6),r8 ; Register form
|
||||
ld.b r4:s(r6),r8 ; Register form
|
||||
ld.h r4:s(r6),r8 ; Register form
|
||||
ld r4:s(r6),r8 ; Register form
|
||||
ld.d r4:s(r6),r8 ; Register form
|
||||
ld.ub r4:s(r6),r8 ; Register form
|
||||
ld.uh r4:s(r6),r8 ; Register form
|
||||
st.b r4:s(r6),r8 ; Register form
|
||||
st.h r4:s(r6),r8 ; Register form
|
||||
st r4:s(r6),r8 ; Register form
|
||||
st.d r4:s(r6),r8 ; Register form
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#objdump: -d
|
||||
#name: TIc80 register operands with both :m and :s modifier
|
||||
|
||||
.*: +file format .*tic80.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
00000000 <.text>:
|
||||
0: 04 8c b4 41.*
|
||||
4: 04 ac b4 41.*
|
||||
8: 04 cc b4 41.*
|
||||
c: 04 ec b4 41.*
|
||||
10: 04 8c b5 41.*
|
||||
14: 04 ac b5 41.*
|
||||
18: 04 8c b6 41.*
|
||||
1c: 04 ac b6 41.*
|
||||
20: 04 cc b6 41.*
|
||||
24: 04 ec b6 41.*
|
||||
28: 04 88 b4 41.*
|
||||
2c: 04 a8 b4 41.*
|
||||
30: 04 c8 b4 41.*
|
||||
34: 04 e8 b4 41.*
|
||||
38: 04 88 b5 41.*
|
||||
3c: 04 a8 b5 41.*
|
||||
40: 04 88 b6 41.*
|
||||
44: 04 a8 b6 41.*
|
||||
48: 04 c8 b6 41.*
|
||||
4c: 04 e8 b6 41.*
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
MVP MP Macro Assembler Version 1.13 Wed Feb 26 14:32:25 1997
|
||||
Copyright (c) 1993-1995 Texas Instruments Incorporated
|
||||
|
||||
regops4.s PAGE 1
|
||||
|
||||
1 00000000 41B48C04 dld.b r4:s(r6:m),r8 ; Register form
|
||||
2 00000004 41B4AC04 dld.h r4:s(r6:m),r8 ; Register form
|
||||
3 00000008 41B4CC04 dld r4:s(r6:m),r8 ; Register form
|
||||
4 0000000C 41B4EC04 dld.d r4:s(r6:m),r8 ; Register form
|
||||
5 00000010 41B58C04 dld.ub r4:s(r6:m),r8 ; Register form
|
||||
6 00000014 41B5AC04 dld.uh r4:s(r6:m),r8 ; Register form
|
||||
7 00000018 41B68C04 dst.b r4:s(r6:m),r8 ; Register form
|
||||
8 0000001C 41B6AC04 dst.h r4:s(r6:m),r8 ; Register form
|
||||
9 00000020 41B6CC04 dst r4:s(r6:m),r8 ; Register form
|
||||
10 00000024 41B6EC04 dst.d r4:s(r6:m),r8 ; Register form
|
||||
11 00000028 41B48804 ld.b r4:s(r6:m),r8 ; Register form
|
||||
12 0000002C 41B4A804 ld.h r4:s(r6:m),r8 ; Register form
|
||||
13 00000030 41B4C804 ld r4:s(r6:m),r8 ; Register form
|
||||
14 00000034 41B4E804 ld.d r4:s(r6:m),r8 ; Register form
|
||||
15 00000038 41B58804 ld.ub r4:s(r6:m),r8 ; Register form
|
||||
16 0000003C 41B5A804 ld.uh r4:s(r6:m),r8 ; Register form
|
||||
17 00000040 41B68804 st.b r4:s(r6:m),r8 ; Register form
|
||||
18 00000044 41B6A804 st.h r4:s(r6:m),r8 ; Register form
|
||||
19 00000048 41B6C804 st r4:s(r6:m),r8 ; Register form
|
||||
20 0000004C 41B6E804 st.d r4:s(r6:m),r8 ; Register form
|
||||
|
||||
No Errors, No Warnings
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
dld.b r4:s(r6:m),r8 ; Register form
|
||||
dld.h r4:s(r6:m),r8 ; Register form
|
||||
dld r4:s(r6:m),r8 ; Register form
|
||||
dld.d r4:s(r6:m),r8 ; Register form
|
||||
dld.ub r4:s(r6:m),r8 ; Register form
|
||||
dld.uh r4:s(r6:m),r8 ; Register form
|
||||
dst.b r4:s(r6:m),r8 ; Register form
|
||||
dst.h r4:s(r6:m),r8 ; Register form
|
||||
dst r4:s(r6:m),r8 ; Register form
|
||||
dst.d r4:s(r6:m),r8 ; Register form
|
||||
ld.b r4:s(r6:m),r8 ; Register form
|
||||
ld.h r4:s(r6:m),r8 ; Register form
|
||||
ld r4:s(r6:m),r8 ; Register form
|
||||
ld.d r4:s(r6:m),r8 ; Register form
|
||||
ld.ub r4:s(r6:m),r8 ; Register form
|
||||
ld.uh r4:s(r6:m),r8 ; Register form
|
||||
st.b r4:s(r6:m),r8 ; Register form
|
||||
st.h r4:s(r6:m),r8 ; Register form
|
||||
st r4:s(r6:m),r8 ; Register form
|
||||
st.d r4:s(r6:m),r8 ; Register form
|
||||
|
|
@ -4,6 +4,9 @@
|
|||
if [istarget tic80*-*-*] then {
|
||||
|
||||
run_dump_test "regops"
|
||||
run_dump_test "regops2"
|
||||
run_dump_test "regops3"
|
||||
run_dump_test "regops4"
|
||||
run_dump_test "cregops"
|
||||
run_dump_test "endmask"
|
||||
run_dump_test "bitnum"
|
||||
|
|
|
|||
Loading…
Reference in New Issue