2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU instruction format. 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-zEC12.d: Adjust length operands for cdzt, cxzt, czdt, and czxt. * gas/s390/zarch-zEC12.d: Likewise.
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@ -1,3 +1,9 @@
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2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* gas/s390/zarch-zEC12.d: Adjust length operands for cdzt, cxzt,
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czdt, and czxt.
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* gas/s390/zarch-zEC12.d: Likewise.
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2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
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* gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ
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@ -47,10 +47,10 @@ Disassembly of section .text:
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.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
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.*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
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.*: ec 67 0c 0d 0e 59 [ ]*risbgn %r6,%r7,12,13,14
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.*: ed 90 8f a0 6d aa [ ]*cdzt %f6,4000\(10,%r8\),13
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.*: ed 90 8f a0 4d ab [ ]*cxzt %f4,4000\(10,%r8\),13
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.*: ed 90 8f a0 6d a8 [ ]*czdt %f6,4000\(10,%r8\),13
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.*: ed 90 8f a0 4d a9 [ ]*czxt %f4,4000\(10,%r8\),13
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.*: ed 0f 8f a0 6d aa [ ]*cdzt %f6,4000\(16,%r8\),13
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.*: ed 21 8f a0 4d ab [ ]*cxzt %f4,4000\(34,%r8\),13
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.*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13
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.*: ed 21 8f a0 4d a9 [ ]*czxt %f4,4000\(34,%r8\),13
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.*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12
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.*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9,0
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.*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1
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@ -44,10 +44,10 @@ foo:
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clgtnh %r6,-5555(%r7)
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risbgn %r6,%r7,12,13,14
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cdzt %f6,4000(10,%r8),13
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cxzt %f4,4000(10,%r8),13
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czdt %f6,4000(10,%r8),13
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czxt %f4,4000(10,%r8),13
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cdzt %f6,4000(16,%r8),13
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cxzt %f4,4000(34,%r8),13
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czdt %f6,4000(16,%r8),13
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czxt %f4,4000(34,%r8),13
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ppa %r5,%r6,12
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crdte %r5,%r6,%r9
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@ -1,3 +1,8 @@
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2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
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instruction format.
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2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
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* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
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@ -388,8 +388,8 @@ const struct s390_operand s390_operands[] =
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#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
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#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
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#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */
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#define INSTR_RSL_LRDFU 6, { F_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cdzt */
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#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L4_8,B_16,U4_36,0 } /* e.g. cxzt */
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#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */
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#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */
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#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
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#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
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#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */
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