* Make-common.in (SCHEME,SCHEMEFLAGS): Delete.
(CGENDIR,CGEN): New variables.
(CGEN_VERBOSE): Renamed to CGENFLAGS.
(cgen-arch,cgen-cpu,cgen-decode): Update.
(CGEN_CPU_WRITE): New variable.
(CGEN_CPU_SEMSW): -W -> -X.
(CGEN_FLAGS_TO_PASS): Delete SCHEME. Add CGEN,CGENFLAGS.
* cgen.sh: Delete args scheme,schemeflags. New arg cgen.
* cgen-sim.h (RECORD_IADDR): Delete.
* cgen-types.h (HOSTINT,HOSTUINT,HOSTPTR): New types.
* genmloop.sh (engine_resume_{full,fast}): Delete icount.
This commit is contained in:
Doug Evans
parent
7c269afbb6
commit
6de2add29f
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@ -1,3 +1,23 @@
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Wed Jul 1 16:44:12 1998 Doug Evans <devans@seba.cygnus.com>
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* Make-common.in (SCHEME,SCHEMEFLAGS): Delete.
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(CGENDIR,CGEN): New variables.
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(CGEN_VERBOSE): Renamed to CGENFLAGS.
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(cgen-arch,cgen-cpu,cgen-decode): Update.
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(CGEN_CPU_WRITE): New variable.
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(CGEN_CPU_SEMSW): -W -> -X.
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(CGEN_FLAGS_TO_PASS): Delete SCHEME. Add CGEN,CGENFLAGS.
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* cgen.sh: Delete args scheme,schemeflags. New arg cgen.
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* cgen-sim.h (RECORD_IADDR): Delete.
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* cgen-types.h (HOSTINT,HOSTUINT,HOSTPTR): New types.
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* genmloop.sh (engine_resume_{full,fast}): Delete icount.
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Wed Jun 17 12:25:08 1998 Mark Alexander <marka@cygnus.com>
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* gennltvals.def (mn10200): Add entry.
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* nltvals.def: Regenerate with MN10200 additions.
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Wed Jun 17 13:18:28 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-inline.h (EXTERN_*): Replace with EXTERN_*_P. Correct
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@ -39,10 +39,11 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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/* Execution support. */
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/* Forward decls. Defined in the machine generated arch.h and cpu.h files. */
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/* Forward decls. Defined in the machine generated files. */
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typedef struct argbuf ARGBUF;
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typedef struct scache SCACHE;
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typedef struct parexec PAREXEC;
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typedef struct idesc IDESC;
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#ifdef SCACHE_P
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@ -64,7 +65,7 @@ typedef ARGBUF *SEM_ARG;
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#endif /* ! SCACHE_P */
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/* Semantic functions come in two versions on two axis:
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/* Semantic functions come in two versions on two axes:
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fast and full (featured), and using or not using scache.
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A full featured simulator is always provided. --enable-sim-fast includes
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support for fast execution by duplicating the semantic code but leaving
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@ -89,32 +90,6 @@ typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
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#endif
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#endif
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/* DECODE struct, there is one per instruction. */
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typedef struct {
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/* Using cgen_insn_type requires <cpu>-opc.h. */
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int /*enum cgen_insn_type*/ insn_type;
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const struct cgen_insn *opcode;
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EXTRACT_FN *extract;
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#ifdef HAVE_PARALLEL_EXEC
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#ifdef __GNUC__
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void *read;
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#else
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int read;
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#endif
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#endif
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SEMANTIC_FN *semantic;
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SEMANTIC_FN *semantic_fast;
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#if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
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/* Set at runtime. */
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void *sem_full_lab;
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#endif
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#if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
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/* Set at runtime. */
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void *semantic_lab; /* FIXME: Rename to sem_fast_lab. */
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#endif
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} DECODE;
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/* Scache data for each cpu. */
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typedef struct cpu_scache {
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@ -199,18 +174,10 @@ do { \
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#define CIA_ADDR(cia) (cia)
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/* extract.c support */
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/* scache_unset is a cache entry that is never used.
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It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for
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newval.cache == NULL. */
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extern struct scache scache_unset;
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#define RECORD_IADDR(fld, val) \
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do { (fld) = (val); } while (0)
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/* semantics.c support */
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#define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf)
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#define SEM_INSN(sem_arg) shouldnt_be_used
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#define SEM_NEXT_PC(sc) ((sc) -> next)
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#define SEM_NEXT_PC(sc, len) ((sc) -> next)
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#define SEM_BRANCH_VIA_CACHE(sc, newval) (newval)
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#define SEM_BRANCH_VIA_ADDR(sc, newval) (newval)
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/* Return address a branch insn will branch to.
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@ -221,14 +188,11 @@ do { (fld) = (val); } while (0)
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#define CIA_ADDR(cia) (cia)
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/* extract.c support */
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#define RECORD_IADDR(fld, val) \
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do { (fld) = (val); } while (0)
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/* semantics.c support */
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#define SEM_ARGBUF(sem_arg) (sem_arg)
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#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
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#define SEM_NEXT_PC(abuf) (abuf -> addr + abuf -> length)
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/* FIXME:wip */
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#define SEM_NEXT_PC(abuf, len) (abuf -> addr + abuf -> length)
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#define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval)
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#define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval)
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#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
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@ -288,10 +252,28 @@ typedef struct cgen_state {
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The member's name must be `cgen_cpu'. */
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typedef struct {
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/* Simulator's execution cache. */
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#if WITH_SCACHE
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/* Simulator's execution cache.
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Allocate space for this even if not used as some simulators may have
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one machine variant that uses the scache and another that doesn't and
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we don't want members in this struct to move about. */
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CPU_SCACHE scache;
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#endif /* WITH_SCACHE */
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/* Instruction descriptor table. */
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IDESC *idesc;
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#define CPU_IDESC(cpu) ((cpu)->cgen_cpu.idesc)
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/* Whether the read,semantic entries have been initialized or not.
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These are computed goto labels. */
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int idesc_read_init_p;
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#define CPU_IDESC_READ_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_read_init_p)
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int idesc_sem_init_p;
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#define CPU_IDESC_SEM_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_sem_init_p)
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/* Function to fetch the opcode table entry in the IDESC. */
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const CGEN_INSN * (*opcode) (SIM_CPU *, int);
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#define CPU_OPCODE(cpu) ((cpu)->cgen_cpu.opcode)
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/* Return name of instruction numbered INUM. */
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#define INSN_NAME(cpu, inum) CGEN_INSN_NAME ((* CPU_OPCODE (cpu)) ((cpu), (inum)))
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/* Allow slop in size calcs for case where multiple cpu types are supported
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and space for the specified cpu is malloc'd at run time. */
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@ -301,10 +283,13 @@ typedef struct {
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/* Various utilities. */
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/* Called after sim_post_argv_init to do any cgen initialization. */
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void cgen_init (SIM_DESC);
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extern void cgen_init (SIM_DESC);
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void
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sim_disassemble_insn (SIM_CPU *, const struct cgen_insn *,
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/* Return the maximum number of extra bytes required for a sim_cpu struct. */
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extern int cgen_cpu_max_extra_bytes (void);
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extern void
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sim_disassemble_insn (SIM_CPU *, const CGEN_INSN *,
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const struct argbuf *, PCADDR, char *);
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#endif /* CGEN_SIM_H */
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@ -92,15 +92,15 @@ cat <<EOF
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#include "cpu-sim.h"
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#include "sim-assert.h"
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/* Tell sim_main_loop to use the cache if it's active.
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/* Tell sim_main_loop to use the scache if it's active.
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Collecting profile data and tracing slow us down so we don't do them in
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"fast mode".
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There are 2 possibilities on 2 axes:
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- use or don't use the cache
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- use or don't use the scache
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- run normally (full featured) or run fast
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Supporting all four possibilities in one executable is a bit much but
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supporting full/fast seems reasonable.
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If the cache is configured in it is always used.
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If the scache is configured in it is always used.
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??? Need to see whether it speeds up profiling significantly or not.
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Speeding up tracing doesn't seem worth it.
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??? Sometimes supporting more than one set of semantic functions will make
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@ -263,7 +263,6 @@ engine_resume_full (SIM_DESC sd)
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/* current_{state,cpu} exist for the generated code to use. */
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SIM_DESC current_state = sd;
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sim_cpu *current_cpu = STATE_CPU (sd, 0);
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${parallel+ int icount = 0;}
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EOF
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@ -276,13 +275,12 @@ cat << EOF
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#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
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{
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static read_init_p = 0;
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if (! read_init_p)
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if (! CPU_IDESC_READ_INIT_P (current_cpu))
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{
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/* ??? Later maybe paste read.c in when building mainloop.c. */
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#define DEFINE_LABELS
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#include "readx.c"
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read_init_p = 1;
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CPU_IDESC_READ_INIT_P (current_cpu) = 1;
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}
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}
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#endif
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@ -362,7 +360,6 @@ engine_resume_full (SIM_DESC sd)
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sim_cpu *current_cpu = STATE_CPU (sd, 0);
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SCACHE cache[MAX_LIW_INSNS];
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SCACHE *sc = &cache[0];
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${parallel+ int icount = 0;}
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EOF
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@ -375,13 +372,12 @@ cat << EOF
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#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
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{
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static read_init_p = 0;
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if (! read_init_p)
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if (! CPU_IDESC_READ_INIT_P (current_cpu))
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{
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/* ??? Later maybe paste read.c in when building mainloop.c. */
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#define DEFINE_LABELS
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#include "readx.c"
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read_init_p = 1;
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CPU_IDESC_READ_INIT_P (current_cpu) = 1;
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}
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}
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#endif
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@ -432,7 +428,6 @@ engine_resume_fast (SIM_DESC sd)
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#define FAST_P 1
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SIM_DESC current_state = sd;
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sim_cpu *current_cpu = STATE_CPU (sd, 0);
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${parallel+ int icount = 0;}
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EOF
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@ -445,13 +440,12 @@ cat << EOF
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#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
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{
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static read_init_p = 0;
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if (! read_init_p)
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if (! CPU_IDESC_READ_INIT_P (current_cpu))
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{
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/* ??? Later maybe paste read.c in when building mainloop.c. */
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#define DEFINE_LABELS
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#include "readx.c"
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read_init_p = 1;
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CPU_IDESC_READ_INIT_P (current_cpu) = 1;
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}
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}
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#endif
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@ -463,13 +457,12 @@ cat <<EOF
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#if defined (WITH_SEM_SWITCH_FAST) && defined (__GNUC__)
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{
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static decode_init_p = 0;
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if (! decode_init_p)
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if (! CPU_IDESC_SEM_INIT_P (current_cpu))
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{
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/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
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#define DEFINE_LABELS
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#include "sem-switch.c"
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decode_init_p = 1;
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CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
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}
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}
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#endif
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@ -531,7 +524,6 @@ engine_resume_fast (SIM_DESC sd)
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sim_cpu *current_cpu = STATE_CPU (sd, 0);
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SCACHE cache[MAX_LIW_INSNS];
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SCACHE *sc = &cache[0];
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${parallel+ int icount = 0;}
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EOF
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@ -544,13 +536,12 @@ cat << EOF
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#if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
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{
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static read_init_p = 0;
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if (! read_init_p)
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if (! CPU_IDESC_READ_INIT_P (current_cpu))
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{
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/* ??? Later maybe paste read.c in when building mainloop.c. */
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#define DEFINE_LABELS
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#include "readx.c"
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read_init_p = 1;
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CPU_IDESC_READ_INIT_P (current_cpu) = 1;
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}
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}
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#endif
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