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Add support for m32r-linux target, including a RELA ABI and PIC.

This commit is contained in:
Nick Clifton 2003-12-19 11:44:01 +00:00
parent c4bf77942d
commit 6edf0760c5
48 changed files with 4978 additions and 107 deletions
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39
bfd/ChangeLog
View File

@ -1,3 +1,42 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
Adfd m32r-linux and PIC support. Add new ABI that uses RELA.
* config.bfd (m32r*-*-linux*, m32r*le-*-linux*, m32r*le-*-*): Added.
* configure.in (bfd_elf32_m32rlin_vec, bfd_elf32_m32rlelin_vec,
bfd_elf32_m32rle_vec): Added
* configure: Regenerated.
* elf32-m32r.c (m32r_info_to_howto, m32r_elf_adjust_dynamic_symbol,
m32r_elf_size_dynamic_sections, m32r_elf_create_dynamic_sections,
m32r_elf_finish_dynamic_sections, m32r_elf_finish_dynamic_symbol,
allocate_dynrelocs, readonly_dynrelocs, m32r_elf_reloc_type_class,
m32r_elf_fake_sections): Added.
(m32r_elf_howto_table): Added
R_M32R_16_RELA, R_M32R_32_RELA, R_M32R_24_RELA,
R_M32R_10_PCREL_RELA, R_M32R_18_PCREL_RELA,
R_M32R_26_PCREL_RELA, R_M32R_HI16_ULO_RELA,
R_M32R_HI16_SLO_RELA, R_M32R_LO16_RELA,
R_M32R_SDA16_RELA, R_M32R_RELA_GNU_VTINHERIT,
R_M32R_RELA_GNU_VTENTRY, R_M32R_GOT24,
R_M32R_26_PLTREL, R_M32R_COPY, R_M32R_GLOB_DAT,
R_M32R_JMP_SLOT, R_M32R_RELATIVE, R_M32R_GOTOFF,
R_M32R_GOTPC24, R_M32R_GOT16_HI_ULO,
R_M32R_GOT16_HI_SLO, R_M32R_GOT16_LO,
R_M32R_GOTPC_HI_ULO, R_M32R_GOTPC_HI_SLO,
R_M32R_GOTPC_LO.
(m32r_elf_relocate_section, m32r_elf_check_relocs): Changed for
New ABI.
* reloc.c: Add BFD_RELOC_M32R_GOT24, BFD_RELOC_M32R_26_PLTREL,
BFD_RELOC_M32R_COPY, BFD_RELOC_M32R_GLOB_DAT,
BFD_RELOC_M32R_JMP_SLOT, BFD_RELOC_M32R_RELATIVE,
BFD_RELOC_M32R_GOTOFF, BFD_RELOC_M32R_GOTPC24,
BFD_RELOC_M32R_GOT16_HI_ULO, BFD_RELOC_M32R_GOT16_HI_SLO,
BFD_RELOC_M32R_GOT16_LO, BFD_RELOC_M32R_GOTPC_HI_ULO,
BFD_RELOC_M32R_GOTPC_HI_SLO, BFD_RELOC_M32R_GOTPC_LO.
* targets.c (bfd_elf32_m32rlin_vec, bfd_elf32_m32rlelin_vec,
bfd_elf32_m32rle_vec): Added.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
2003-12-19 Danny Smith <dannysmith@users.sourceforge.net>
* coffcode.h (styp_to_sec_flags): Don't treat .reloc section

16
bfd/bfd-in2.h
View File

@ -2807,6 +2807,22 @@ used when the lower 16 bits are treated as signed. */
add3, load, and store instructions. */
BFD_RELOC_M32R_SDA16,
/* For PIC. */
BFD_RELOC_M32R_GOT24,
BFD_RELOC_M32R_26_PLTREL,
BFD_RELOC_M32R_COPY,
BFD_RELOC_M32R_GLOB_DAT,
BFD_RELOC_M32R_JMP_SLOT,
BFD_RELOC_M32R_RELATIVE,
BFD_RELOC_M32R_GOTOFF,
BFD_RELOC_M32R_GOTPC24,
BFD_RELOC_M32R_GOT16_HI_ULO,
BFD_RELOC_M32R_GOT16_HI_SLO,
BFD_RELOC_M32R_GOT16_LO,
BFD_RELOC_M32R_GOTPC_HI_ULO,
BFD_RELOC_M32R_GOTPC_HI_SLO,
BFD_RELOC_M32R_GOTPC_LO,
/* This is a 9-bit reloc */
BFD_RELOC_V850_9_PCREL,

15
bfd/config.bfd
View File

@ -597,6 +597,21 @@ case "${targ}" in
targ_defvec=bfd_elf32_iq2000_vec
;;
m32r*le-*-linux*)
targ_defvec=bfd_elf32_m32rlelin_vec
targ_selvecs="bfd_elf32_m32rlin_vec bfd_elf32_m32rlelin_vec"
;;
m32r*-*-linux*)
targ_defvec=bfd_elf32_m32rlin_vec
targ_selvecs="bfd_elf32_m32rlin_vec bfd_elf32_m32rlelin_vec"
;;
m32r*le-*-*)
targ_defvec=bfd_elf32_m32rle_vec
targ_selvecs="bfd_elf32_m32r_vec bfd_elf32_m32rle_vec"
;;
m32r-*-*)
targ_defvec=bfd_elf32_m32r_vec
;;

31
bfd/configure vendored
View File

@ -6320,6 +6320,9 @@ do
bfd_elf32_littlearm_vec) tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rlin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rlelin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m68hc11_vec) tb="$tb elf32-m68hc11.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
bfd_elf32_m68hc12_vec) tb="$tb elf32-m68hc12.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
bfd_elf32_m68k_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;;
@ -6579,10 +6582,10 @@ case ${host64}-${target64}-${want64} in
if test -n "$GCC" ; then
bad_64bit_gcc=no;
echo $ac_n "checking for gcc version with buggy 64-bit support""... $ac_c" 1>&6
echo "configure:6583: checking for gcc version with buggy 64-bit support" >&5
echo "configure:6586: checking for gcc version with buggy 64-bit support" >&5
# Add more tests for gcc versions with non-working 64-bit support here.
cat > conftest.$ac_ext <<EOF
#line 6586 "configure"
#line 6589 "configure"
#include "confdefs.h"
:__GNUC__:__GNUC_MINOR__:__i386__:
EOF
@ -6628,17 +6631,17 @@ for ac_hdr in unistd.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:6632: checking for $ac_hdr" >&5
echo "configure:6635: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 6637 "configure"
#line 6640 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:6642: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:6645: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -6667,12 +6670,12 @@ done
for ac_func in getpagesize
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:6671: checking for $ac_func" >&5
echo "configure:6674: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 6676 "configure"
#line 6679 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -6695,7 +6698,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:6699: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:6702: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -6720,7 +6723,7 @@ fi
done
echo $ac_n "checking for working mmap""... $ac_c" 1>&6
echo "configure:6724: checking for working mmap" >&5
echo "configure:6727: checking for working mmap" >&5
if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -6728,7 +6731,7 @@ else
ac_cv_func_mmap_fixed_mapped=no
else
cat > conftest.$ac_ext <<EOF
#line 6732 "configure"
#line 6735 "configure"
#include "confdefs.h"
/* Thanks to Mike Haertel and Jim Avera for this test.
@ -6868,7 +6871,7 @@ main()
}
EOF
if { (eval echo configure:6872: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
if { (eval echo configure:6875: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_func_mmap_fixed_mapped=yes
else
@ -6893,12 +6896,12 @@ fi
for ac_func in madvise mprotect
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:6897: checking for $ac_func" >&5
echo "configure:6900: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 6902 "configure"
#line 6905 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -6921,7 +6924,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:6925: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:6928: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else

3
bfd/configure.in
View File

@ -631,6 +631,9 @@ do
bfd_elf32_littlearm_vec) tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;;
bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rlin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m32rlelin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;;
bfd_elf32_m68hc11_vec) tb="$tb elf32-m68hc11.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
bfd_elf32_m68hc12_vec) tb="$tb elf32-m68hc12.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
bfd_elf32_m68k_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;;

2754
bfd/elf32-m32r.c
View File

File diff suppressed because it is too large Load Diff

31
bfd/reloc.c
View File

@ -2911,6 +2911,37 @@ ENUM
ENUMDOC
This is a 16-bit reloc containing the small data area offset for use in
add3, load, and store instructions.
ENUM
BFD_RELOC_M32R_GOT24
ENUMX
BFD_RELOC_M32R_26_PLTREL
ENUMX
BFD_RELOC_M32R_COPY
ENUMX
BFD_RELOC_M32R_GLOB_DAT
ENUMX
BFD_RELOC_M32R_JMP_SLOT
ENUMX
BFD_RELOC_M32R_RELATIVE
ENUMX
BFD_RELOC_M32R_GOTOFF
ENUMX
BFD_RELOC_M32R_GOTPC24
ENUMX
BFD_RELOC_M32R_GOT16_HI_ULO
ENUMX
BFD_RELOC_M32R_GOT16_HI_SLO
ENUMX
BFD_RELOC_M32R_GOT16_LO
ENUMX
BFD_RELOC_M32R_GOTPC_HI_ULO
ENUMX
BFD_RELOC_M32R_GOTPC_HI_SLO
ENUMX
BFD_RELOC_M32R_GOTPC_LO
ENUMDOC
For PIC.
ENUM
BFD_RELOC_V850_9_PCREL

6
bfd/targets.c
View File

@ -542,6 +542,9 @@ extern const bfd_target bfd_elf32_littlearm_oabi_vec;
extern const bfd_target bfd_elf32_littlearm_vec;
extern const bfd_target bfd_elf32_littlemips_vec;
extern const bfd_target bfd_elf32_m32r_vec;
extern const bfd_target bfd_elf32_m32rle_vec;
extern const bfd_target bfd_elf32_m32rlin_vec;
extern const bfd_target bfd_elf32_m32rlelin_vec;
extern const bfd_target bfd_elf32_m68hc11_vec;
extern const bfd_target bfd_elf32_m68hc12_vec;
extern const bfd_target bfd_elf32_m68k_vec;
@ -831,6 +834,9 @@ static const bfd_target * const _bfd_target_vector[] = {
&bfd_elf32_littlearm_vec,
&bfd_elf32_littlemips_vec,
&bfd_elf32_m32r_vec,
&bfd_elf32_m32rle_vec,
&bfd_elf32_m32rlin_vec,
&bfd_elf32_m32rlelin_vec,
&bfd_elf32_m68hc11_vec,
&bfd_elf32_m68hc12_vec,
&bfd_elf32_m68k_vec,

4
binutils/ChangeLog
View File

@ -1,3 +1,7 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* readelf.c (guess_is_rela): Changed m32r's default type to RELA.
2003-12-11 Nick Clifton <nickc@redhat.com>
* objcopy.c (strip_usage): Add --only-keep-debug.

2
binutils/readelf.c
View File

@ -618,7 +618,6 @@ guess_is_rela (unsigned long e_machine)
case EM_DLX:
case EM_OPENRISC:
case EM_OR32:
case EM_M32R:
case EM_CYGNUS_M32R:
case EM_D10V:
case EM_CYGNUS_D10V:
@ -668,6 +667,7 @@ guess_is_rela (unsigned long e_machine)
case EM_IQ2000:
case EM_XTENSA:
case EM_XTENSA_OLD:
case EM_M32R:
return TRUE;
case EM_MMA:

15
gas/ChangeLog
View File

@ -1,3 +1,18 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
Add m32r-linux and PIC support. Add new ABI that uses RELA.
* configure.in: Add m32r-linux targets.
* configure: Regenerate.
* config/tc-m32r.c (md_parse_option): Add -KPIC option.
(tc_gen_reloc): Added.
(debug_sym, md_estimate_size_before_relax, md_convert_frag,
md_pcrel_from_section, m32r_fix_adjustable): Changed for PIC.
* config/tc-m32r.h (tc_gen_reloc, EXTERN_FORCE_RELOC): Undefined.
(TC_HANDLES_FX_DONE, TC_FIX_ADJUSTABLE, TC_RELOC_RTSYM_LOC_FIXUP):
Defined.
* doc/c-m32r.texi: Document -KPIC option.
* NEWS: Mention the support m32r Linux and PIC.
2003-12-18 Nick Clifton <nickc@redhat.com>
* input-file.c (input_file_open): Remove call to stat().

2
gas/NEWS
View File

@ -1,5 +1,7 @@
-*- text -*-
* Added PIC m32r Linux (ELF) and support to M32R assembler.
* Added support for ARM V6.
* Added support for sh4a and variants.

154
gas/config/tc-m32r.c
View File

@ -70,6 +70,9 @@ static m32r_insn prev_insn;
alignment request. */
static int seen_relaxable_p = 0;
/* Non-zero if we are generating PIC code. */
int pic_code;
/* Non-zero if -relax specified, in which case sufficient relocs are output
for the linker to do relaxing.
We do simple forms of relaxing internally, but they are always done.
@ -194,7 +197,7 @@ allow_m32rx (int on)
gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
}
#define M32R_SHORTOPTS "O"
#define M32R_SHORTOPTS "O::K:"
const char *md_shortopts = M32R_SHORTOPTS;
@ -362,6 +365,13 @@ md_parse_option (c, arg)
warn_unmatched_high = 0;
break;
case 'K':
if (strcmp (arg, "PIC") != 0)
as_warn (_("Unrecognized option following -K"));
else
pic_code = 1;
break;
#if 0
/* Not supported yet. */
case OPTION_RELAX:
@ -436,6 +446,9 @@ md_show_usage (stream)
fprintf (stream, _("\
-Wnuh synonym for -no-warn-unmatched-high\n"));
fprintf (stream, _("\
-KPIC generate PIC\n"));
#if 0
fprintf (stream, _("\
-relax create linker relaxable code\n"));
@ -558,7 +571,9 @@ debug_sym (ignore)
}
symbol_table_insert (symbolP);
if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
|| S_IS_EXTERNAL (symbolP)
|| S_IS_WEAK (symbolP)))
/* xgettext:c-format */
as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
@ -1710,7 +1725,9 @@ md_estimate_size_before_relax (fragP, segment)
However, we can't finish the fragment here and emit the reloc as insn
alignment requirements may move the insn about. */
if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
|| S_IS_EXTERNAL (fragP->fr_symbol)
|| S_IS_WEAK (fragP->fr_symbol))
{
#if 0
int old_fr_fix = fragP->fr_fix;
@ -1816,12 +1833,18 @@ md_convert_frag (abfd, sec, fragP)
abort ();
}
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|| S_IS_EXTERNAL (fragP->fr_symbol)
|| S_IS_WEAK (fragP->fr_symbol))
{
/* Symbol must be resolved by linker. */
if (fragP->fr_offset & 3)
as_warn (_("Addend to unresolved symbol not on word boundary."));
addend = fragP->fr_offset >> 2;
#ifdef USE_M32R_OLD_RELOC
addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
#else
addend = 0;
#endif
}
else
{
@ -1833,7 +1856,9 @@ md_convert_frag (abfd, sec, fragP)
/* Create a relocation for symbols that must be resolved by the linker.
Otherwise output the completed insn. */
if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
if (S_GET_SEGMENT (fragP->fr_symbol) != sec
|| S_IS_EXTERNAL (fragP->fr_symbol)
|| S_IS_WEAK (fragP->fr_symbol))
{
assert (fragP->fr_subtype != 1);
assert (fragP->fr_cgen.insn != 0);
@ -1874,7 +1899,9 @@ md_pcrel_from_section (fixP, sec)
{
if (fixP->fx_addsy != (symbolS *) NULL
&& (! S_IS_DEFINED (fixP->fx_addsy)
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
|| S_GET_SEGMENT (fixP->fx_addsy) != sec
|| S_IS_EXTERNAL (fixP->fx_addsy)
|| S_IS_WEAK (fixP->fx_addsy)))
{
/* The symbol is undefined (or is defined but not in this section).
Let the linker figure it out. */
@ -2189,6 +2216,23 @@ m32r_fix_adjustable (fixP)
else
reloc_type = fixP->fx_r_type;
if (fixP->fx_addsy == NULL)
return 1;
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERN (fixP->fx_addsy))
return 0;
if (S_IS_WEAK (fixP->fx_addsy))
return 0;
if (pic_code
&& (reloc_type == BFD_RELOC_M32R_24
|| reloc_type == BFD_RELOC_M32R_26_PCREL
|| reloc_type == BFD_RELOC_M32R_HI16_SLO
|| reloc_type == BFD_RELOC_M32R_HI16_ULO
|| reloc_type == BFD_RELOC_M32R_LO16))
return 0;
/* We need the symbol name for the VTABLE entries. */
if (reloc_type == BFD_RELOC_VTABLE_INHERIT
|| reloc_type == BFD_RELOC_VTABLE_ENTRY)
@ -2204,3 +2248,99 @@ m32r_elf_final_processing ()
m32r_flags |= E_M32R_HAS_PARALLEL;
elf_elfheader (stdoutput)->e_flags |= m32r_flags;
}
#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
/* Translate internal representation of relocation info to BFD target
format. */
arelent *
tc_gen_reloc (section, fixP)
asection * section;
fixS * fixP;
{
arelent * reloc;
bfd_reloc_code_real_type code;
reloc = (arelent *) xmalloc (sizeof (arelent));
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
code = fixP->fx_r_type;
if (pic_code)
{
#ifdef DEBUG_PIC
printf("%s",bfd_get_reloc_code_name(code));
#endif
switch (code)
{
case BFD_RELOC_M32R_26_PCREL:
code = BFD_RELOC_M32R_26_PLTREL;
break;
case BFD_RELOC_M32R_24:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
code = BFD_RELOC_M32R_GOTPC24;
else
code = BFD_RELOC_M32R_GOT24;
break;
case BFD_RELOC_M32R_HI16_ULO:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
code = BFD_RELOC_M32R_GOTPC_HI_ULO;
else
code = BFD_RELOC_M32R_GOT16_HI_ULO;
break;
case BFD_RELOC_M32R_HI16_SLO:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
code = BFD_RELOC_M32R_GOTPC_HI_SLO;
else
code = BFD_RELOC_M32R_GOT16_HI_SLO;
break;
case BFD_RELOC_M32R_LO16:
if (fixP->fx_addsy != NULL
&& strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
code = BFD_RELOC_M32R_GOTPC_LO;
else
code = BFD_RELOC_M32R_GOT16_LO;
break;
default:
break;
}
#ifdef DEBUG_PIC
printf(" => %s",bfd_get_reloc_code_name(code));
#endif
}
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
#ifdef DEBUG_PIC
printf(" => %s\n",reloc->howto->name);
#endif
if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
_("internal error: can't export reloc type %d (`%s')"),
fixP->fx_r_type, bfd_get_reloc_code_name (code));
return NULL;
}
/* Use fx_offset for these cases */
if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT)
reloc->addend = fixP->fx_offset;
else if (!pic_code
&& fixP->fx_pcrel
&& fixP->fx_addsy != NULL
&& (S_GET_SEGMENT(fixP->fx_addsy) != section)
&& S_IS_DEFINED (fixP->fx_addsy)
&& ! S_IS_EXTERNAL(fixP->fx_addsy)
&& ! S_IS_WEAK(fixP->fx_addsy))
/* already used fx_offset in the opcode field itseld. */
reloc->addend = 0;
else
reloc->addend = fixP->fx_addnumber;
return reloc;
}

23
gas/config/tc-m32r.h
View File

@ -87,14 +87,31 @@ bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
HI16 relocs and queue them up for later sorting. */
#define md_cgen_record_fixup_exp m32r_cgen_record_fixup_exp
#define tc_gen_reloc gas_cgen_tc_gen_reloc
/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
#define TC_HANDLES_FX_DONE
extern int pic_code;
extern bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
/* This arranges for gas/write.c to not apply a relocation if
obj_fix_adjustable() says it is not adjustable. */
#define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP)
#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
((FIX)->fx_addsy == NULL \
|| (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
&& ! S_IS_WEAK ((FIX)->fx_addsy) \
&& S_IS_DEFINED ((FIX)->fx_addsy) \
&& ! S_IS_COMMON ((FIX)->fx_addsy)))
#define tc_frob_file_before_fix() m32r_frob_file ()
extern void m32r_frob_file PARAMS ((void));
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
visible symbols can be overridden.
#define EXTERN_FORCE_RELOC 0 */
/* When relaxing, we need to emit various relocs we otherwise wouldn't. */
#define TC_FORCE_RELOCATION(fix) m32r_force_relocation (fix)

5
gas/configure vendored
View File

@ -4000,6 +4000,8 @@ for this_target in $target $canon_targets ; do
sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
v850*) cpu_type=v850 ;;
xtensa*) cpu_type=xtensa arch=xtensa ;;
m32r) cpu_type=m32r target_cpu=m32r endian=big ;;
m32rle) cpu_type=m32r target_cpu=m32r endian=little ;;
*) cpu_type=${cpu} ;;
esac
@ -4180,7 +4182,8 @@ echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a wo
iq2000-*-elf) fmt=elf bfd_gas=yes ;;
m32r-*-*) fmt=elf ;;
m32r-*-elf*) fmt=elf ;;
m32r-*-linux*) fmt=elf em=linux;;
m68hc11-*-* | m6811-*-*) fmt=elf ;;
m68hc12-*-* | m6812-*-*) fmt=elf ;;

5
gas/configure.in
View File

@ -164,6 +164,8 @@ changequote([,])dnl
sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
v850*) cpu_type=v850 ;;
xtensa*) cpu_type=xtensa arch=xtensa ;;
m32r) cpu_type=m32r target_cpu=m32r endian=big ;;
m32rle) cpu_type=m32r target_cpu=m32r endian=little ;;
*) cpu_type=${cpu} ;;
esac
@ -337,7 +339,8 @@ changequote([,])dnl
iq2000-*-elf) fmt=elf bfd_gas=yes ;;
m32r-*-*) fmt=elf ;;
m32r-*-elf*) fmt=elf ;;
m32r-*-linux*) fmt=elf em=linux;;
m68hc11-*-* | m6811-*-*) fmt=elf ;;
m68hc12-*-* | m6812-*-*) fmt=elf ;;

6
gas/doc/c-m32r.texi
View File

@ -75,6 +75,12 @@ data.
@cindex @code{-EB} option, M32R
This is a synonum for @emph{-big}.
@item -KPIC
@cindex @code{-KPIC} option, M32R
@cindex PIC code generation for M32R
This option specifies that the output of the assembler should be
marked as position-independent code (PIC).
@item -parallel
@cindex @code{-parallel} option, M32RX
This option tells the assembler to attempts to combine two sequential

13
gas/testsuite/ChangeLog
View File

@ -1,3 +1,16 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* gas/m32r/m32rx.s: Changed pattern bncl to bncl.s.
* gas/m32r/allinsn.d: Update for New RELA-ABI.
* gas/m32r/high-1.d: Likewise.
* gas/m32r/relax-1.d: Likewise.
* gas/m32r/uppercase.d: Likewise.
* gas/m32r/m32rx.d: Likewise.
* gas/vtable/vtable.exp: Likewise.
* gas/m32r/pic.exp: New file for PIC.
* gas/m32r/pic.s: Likewise.
* gas/m32r/pic.d: Likewise.
2003-12-18 Richard Sandiford <rsandifo@redhat.com>
* gas/mips/mips16-jalx.d: Use -mabi=o64.

2
gas/testsuite/gas/m32r/allinsn.d
View File

@ -209,7 +209,7 @@ Disassembly of section .text:
0+010c <ld24>:
10c: ed 00 00 00 ld24 fp,[#]*0 <add>
10c: R_M32R_24 .data
10c: R_M32R_24_RELA .data
0+0110 <ldi8>:
110: 6d 00 f0 00 ldi fp,[#]*0 \|\| nop

6
gas/testsuite/gas/m32r/high-1.d
View File

@ -7,10 +7,10 @@
Disassembly of section .text:
0* <foo>:
*0: d4 c0 00 01 seth r4,[#]*0x1
[ ]*0: R_M32R_HI16_ULO .text
*0: d4 c0 00 00 seth r4,[#]*0x0
[ ]*0: R_M32R_HI16_ULO_RELA .text\+0x10000
*4: 84 e4 00 00 or3 r4,r4,[#]*0x0
[ ]*4: R_M32R_LO16 .text
[ ]*4: R_M32R_LO16_RELA .text\+0x10000
*8: d4 c0 12 34 seth r4,[#]*0x1234
*c: 84 e4 87 65 or3 r4,r4,[#]*0x8765
*10: d4 c0 12 35 seth r4,[#]*0x1235

36
gas/testsuite/gas/m32r/m32rx.d
View File

@ -85,28 +85,40 @@ Disassembly of section .text:
64: 54 81 f0 00 rach a1,a0,#0x2 \|\| nop
0+0068 <bc__add>:
68: 7c e6 8d ad bc 0 <bcl> \|\| add fp,fp
6c: 7c e5 0d ad bc 0 <bcl> -> add fp,fp
68: 7c 00 8d ad bc 68 <bc__add> \|\| add fp,fp
68: R_M32R_10_PCREL_RELA bcl
6c: 7c 00 0d ad bc 6c <bc__add\+0x4> -> add fp,fp
6c: R_M32R_10_PCREL_RELA bcl
0+0070 <bcl__addi>:
70: 78 e4 cd 4d bcl 0 <bcl> \|\| addi fp,#77
74: 78 e3 cd 4d bcl 0 <bcl> \|\| addi fp,#77
70: 78 00 cd 4d bcl 70 <bcl__addi> \|\| addi fp,#77
70: R_M32R_10_PCREL_RELA bcl
74: 78 00 cd 4d bcl 74 <bcl__addi\+0x4> \|\| addi fp,#77
74: R_M32R_10_PCREL_RELA bcl
0+0078 <bl__addv>:
78: 7e e2 8d 8d bl 0 <bcl> \|\| addv fp,fp
7c: 7e e1 8d 8d bl 0 <bcl> \|\| addv fp,fp
78: 7e 00 8d 8d bl 78 <bl__addv> \|\| addv fp,fp
78: R_M32R_10_PCREL_RELA bcl
7c: 7e 00 8d 8d bl 7c <bl__addv\+0x4> \|\| addv fp,fp
7c: R_M32R_10_PCREL_RELA bcl
0+0080 <bnc__addx>:
80: 7d e0 8d 9d bnc 0 <bcl> \|\| addx fp,fp
84: 7d df 0d 9d bnc 0 <bcl> -> addx fp,fp
80: 7d 00 8d 9d bnc 80 <bnc__addx> \|\| addx fp,fp
80: R_M32R_10_PCREL_RELA bcl
84: 7d 00 0d 9d bnc 84 <bnc__addx\+0x4> -> addx fp,fp
84: R_M32R_10_PCREL_RELA bcl
0+0088 <bncl__and>:
88: 79 de 8d cd bncl 0 <bcl> \|\| and fp,fp
8c: 0d cd 79 dd and fp,fp -> bncl 0 <bcl>
88: 79 00 8d cd bncl 88 <bncl__and> \|\| and fp,fp
88: R_M32R_10_PCREL_RELA bcl
8c: 79 00 8d cd bncl 8c <bncl__and\+0x4> \|\| and fp,fp
8c: R_M32R_10_PCREL_RELA bcl
0+0090 <bra__cmp>:
90: 7f dc 8d 4d bra 0 <bcl> \|\| cmp fp,fp
94: 7f db 8d 4d bra 0 <bcl> \|\| cmp fp,fp
90: 7f 00 8d 4d bra 90 <bra__cmp> \|\| cmp fp,fp
90: R_M32R_10_PCREL_RELA bcl
94: 7f 00 8d 4d bra 94 <bra__cmp\+0x4> \|\| cmp fp,fp
94: R_M32R_10_PCREL_RELA bcl
0+0098 <jl__cmpeq>:
98: 1e cd 8d 6d jl fp \|\| cmpeq fp,fp

2
gas/testsuite/gas/m32r/m32rx.s
View File

@ -172,7 +172,7 @@ bnc__addx:
bncl__and:
bncl bcl || and fp, fp
and fp, fp
bncl bcl
bncl.s bcl
.text
.global bra__cmp

47
gas/testsuite/gas/m32r/pic.d Normal file
View File

@ -0,0 +1,47 @@
#as: -K PIC
#objdump: -dr
#name: pic
.*: +file format .*
Disassembly of section .text:
0+0000 <pic_gotpc>:
0: 7e 01 f0 00 bl 4 <pic_gotpc\+0x4> \|\| nop
4: ec 00 00 00 ld24 r12,0 <pic_gotpc>
4: R_M32R_GOTPC24 _GLOBAL_OFFSET_TABLE_
8: 0c ae f0 00 add r12,lr \|\| nop
0+000c <pic_gotpc_slo>:
c: 7e 01 f0 00 bl 10 <pic_gotpc_slo\+0x4> \|\| nop
10: dc c0 00 00 seth r12,[#]0x0
10: R_M32R_GOTPC_HI_SLO _GLOBAL_OFFSET_TABLE_
14: 8c ac 00 00 add3 r12,r12,[#]0
14: R_M32R_GOTPC_LO _GLOBAL_OFFSET_TABLE_\+0x4
18: 0c ae f0 00 add r12,lr \|\| nop
0+001c <pic_gotpc_ulo>:
1c: 7e 01 f0 00 bl 20 <pic_gotpc_ulo\+0x4> \|\| nop
20: dc c0 00 00 seth r12,[#]0x0
20: R_M32R_GOTPC_HI_ULO _GLOBAL_OFFSET_TABLE_
24: 8c ec 00 00 or3 r12,r12,[#]0x0
24: R_M32R_GOTPC_LO _GLOBAL_OFFSET_TABLE_\+0x4
28: 0c ae f0 00 add r12,lr \|\| nop
0+002c <pic_got>:
2c: e0 00 00 00 ld24 r0,0 <pic_gotpc>
2c: R_M32R_GOT24 sym
0+0030 <pic_got16>:
30: dc c0 00 00 seth r12,[#]0x0
30: R_M32R_GOT16_HI_SLO sym2
34: 8c ac 00 00 add3 r12,r12,[#]0
34: R_M32R_GOT16_LO sym2\+0x4
38: dc c0 00 00 seth r12,[#]0x0
38: R_M32R_GOT16_HI_ULO sym2
3c: 8c ec 00 00 or3 r12,r12,[#]0x0
3c: R_M32R_GOT16_LO sym2\+0x4
0+0040 <pic_plt>:
40: fe 00 00 00 bl 40 <pic_plt>
40: R_M32R_26_PLTREL func

5
gas/testsuite/gas/m32r/pic.exp Normal file
View File

@ -0,0 +1,5 @@
# M32R PIC testcases
if [istarget m32r*-*-*] {
run_dump_test "pic"
}

43
gas/testsuite/gas/m32r/pic.s Normal file
View File

@ -0,0 +1,43 @@
.section .text
# R_M32R_GOTPC24
pic_gotpc:
bl.s .+4
ld24 r12,#_GLOBAL_OFFSET_TABLE_
add r12,lr
# R_M32R_GOTPC_HI_ULO
# R_M32R_GOTPC_HI_SLO
# R_M32R_GOTPC_LO
pic_gotpc_slo:
bl.s .+4
seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
pic_gotpc_ulo:
bl.s .+4
seth r12,#high(_GLOBAL_OFFSET_TABLE_)
or3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
add r12,lr
# R_M32R_GOT24
pic_got:
.global sym
ld24 r0,#sym
# R_M32R_GOT16_HI_ULO
# R_M32R_GOT16_HI_SLO
# R_M32R_GOT16_LO
pic_got16:
.global sym2
seth r12,#shigh(sym2)
add3 r12,r12,#low(sym2+4)
seth r12,#high(sym2)
or3 r12,r12,#low(sym2+4)
# R_M32R_26_PLTREL
pic_plt:
.global func
bl func
.end

2
gas/testsuite/gas/m32r/relax-1.d
View File

@ -15,4 +15,4 @@ Disassembly of section .branch:
0* <branch>:
*0: ff 00 00 01 bra 4 <Work>
[ ]*0: R_M32R_26_PCREL .text
[ ]*0: R_M32R_26_PCREL_RELA .text

10
gas/testsuite/gas/m32r/uppercase.d
View File

@ -11,16 +11,16 @@ Disassembly of section .text:
0+0004 <high>:
4: d0 c0 00 00 seth r0,#0x0
[ ]*4: R_M32R_HI16_ULO [.]text
[ ]*4: R_M32R_HI16_ULO_RELA [.]text\+0x4
0+0008 <shigh>:
8: d0 c0 00 00 seth r0,#0x0
[ ]*8: R_M32R_HI16_SLO [.]text
[ ]*8: R_M32R_HI16_SLO_RELA [.]text\+0x8
0+000c <low>:
c: 80 e0 00 0c or3 r0,r0,#0xc
[ ]*c: R_M32R_LO16 [.]text
c: 80 e0 00 00 or3 r0,r0,#0x0
[ ]*c: R_M32R_LO16_RELA [.]text\+0xc
0+0010 <sda>:
10: 80 a0 00 00 add3 r0,r0,#0
[ ]*10: R_M32R_SDA16 sdavar
[ ]*10: R_M32R_SDA16_RELA sdavar

1
gas/testsuite/gas/vtable/vtable.exp
View File

@ -41,7 +41,6 @@ if { ( [istarget "*-*-elf*"] || [istarget "*-*-linux*"])
|| [istarget "d10v-*"]
|| [istarget "dlx-*"]
|| [istarget "i*86-*"]
|| [istarget "m32r-*"]
|| ([istarget "mips*-*"]
&& ! [istarget "mips64*-*-linux*"]
&& ! [istarget "mips*-*-irix6*"])

17
include/elf/ChangeLog
View File

@ -1,3 +1,20 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* elf/m32r.h : Added m32r-linux and PIC support. Add new ABI that
uses RELA.
(R_M32R_16_RELA, R_M32R_32_RELA, R_M32R_24_RELA,
R_M32R_10_PCREL_RELA, R_M32R_18_PCREL_RELA,
R_M32R_26_PCREL_RELA, R_M32R_HI16_ULO_RELA,
R_M32R_HI16_SLO_RELA, R_M32R_LO16_RELA,
R_M32R_SDA16_RELA, R_M32R_RELA_GNU_VTINHERIT,
R_M32R_RELA_GNU_VTENTRY, R_M32R_GOT24,
R_M32R_26_PLTREL, R_M32R_COPY, R_M32R_GLOB_DAT,
R_M32R_JMP_SLOT, R_M32R_RELATIVE, R_M32R_GOTOFF,
R_M32R_GOTPC24, R_M32R_GOT16_HI_ULO,
R_M32R_GOT16_HI_SLO, R_M32R_GOT16_LO,
R_M32R_GOTPC_HI_ULO, R_M32R_GOTPC_HI_SLO,
R_M32R_GOTPC_LO): New relocs.
2003-12-06 Alan Modra <amodra@bigpond.net.au>
From Jan Beulich <JBeulich@novell.com>

54
include/elf/m32r.h
View File

@ -25,18 +25,48 @@
/* Relocations. */
START_RELOC_NUMBERS (elf_m32r_reloc_type)
RELOC_NUMBER (R_M32R_NONE, 0)
RELOC_NUMBER (R_M32R_16, 1)
RELOC_NUMBER (R_M32R_32, 2)
RELOC_NUMBER (R_M32R_24, 3)
RELOC_NUMBER (R_M32R_10_PCREL, 4)
RELOC_NUMBER (R_M32R_18_PCREL, 5)
RELOC_NUMBER (R_M32R_26_PCREL, 6)
RELOC_NUMBER (R_M32R_HI16_ULO, 7)
RELOC_NUMBER (R_M32R_HI16_SLO, 8)
RELOC_NUMBER (R_M32R_LO16, 9)
RELOC_NUMBER (R_M32R_SDA16, 10)
RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)
RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12)
/* REL relocations */
RELOC_NUMBER (R_M32R_16, 1) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_32, 2) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_24, 3) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_10_PCREL, 4) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_18_PCREL, 5) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_26_PCREL, 6) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_HI16_ULO, 7) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_HI16_SLO, 8) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_LO16, 9) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_SDA16, 10) /* For backwards compatibility. */
RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)/* For backwards compatibility. */
RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12) /* For backwards compatibility. */
/* RELA relocations */
RELOC_NUMBER (R_M32R_16_RELA, 33)
RELOC_NUMBER (R_M32R_32_RELA, 34)
RELOC_NUMBER (R_M32R_24_RELA, 35)
RELOC_NUMBER (R_M32R_10_PCREL_RELA, 36)
RELOC_NUMBER (R_M32R_18_PCREL_RELA, 37)
RELOC_NUMBER (R_M32R_26_PCREL_RELA, 38)
RELOC_NUMBER (R_M32R_HI16_ULO_RELA, 39)
RELOC_NUMBER (R_M32R_HI16_SLO_RELA, 40)
RELOC_NUMBER (R_M32R_LO16_RELA, 41)
RELOC_NUMBER (R_M32R_SDA16_RELA, 42)
RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43)
RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44)
RELOC_NUMBER (R_M32R_GOT24, 48)
RELOC_NUMBER (R_M32R_26_PLTREL, 49)
RELOC_NUMBER (R_M32R_COPY, 50)
RELOC_NUMBER (R_M32R_GLOB_DAT, 51)
RELOC_NUMBER (R_M32R_JMP_SLOT, 52)
RELOC_NUMBER (R_M32R_RELATIVE, 53)
RELOC_NUMBER (R_M32R_GOTOFF, 54)
RELOC_NUMBER (R_M32R_GOTPC24, 55)
RELOC_NUMBER (R_M32R_GOT16_HI_ULO, 56)
RELOC_NUMBER (R_M32R_GOT16_HI_SLO, 57)
RELOC_NUMBER (R_M32R_GOT16_LO, 58)
RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59)
RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60)
RELOC_NUMBER (R_M32R_GOTPC_LO, 61)
END_RELOC_NUMBERS (R_M32R_max)
/* Processor specific section indices. These sections do not actually

12
ld/ChangeLog
View File

@ -1,3 +1,15 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
Add m32r-linux and PIC support. Add new ABI that uses RELA.
* Makefile.am: Added em32rlelf.c, em32relf_linux.c,
em32rlelf_linux.c.
* Makefile.in: Regenerate.
* configure.tgt (m32r*-*-linux*, m32r*le-*-linux*, m32r*le-*-*):Added.
* emulparams/m32relf_linux.sh: Added.
* emulparams/m32rlelf.sh: Ditto.
* emulparams/m32rlelf_linux.sh: Ditto.
* NEWS: Mention support m32r Linux.
2003-12-18 Eric Youngdale <eric@mkssoftware.com>
Nick Clifton <nickc@redhat.com>

12
ld/Makefile.am
View File

@ -230,6 +230,9 @@ ALL_EMULATIONS = \
ei386pe_posix.o \
elnk960.o \
em32relf.o \
em32rlelf.o \
em32relf_linux.o \
em32rlelf_linux.o \
em68hc11elf.o \
em68hc11elfb.o \
em68hc12elf.o \
@ -603,6 +606,15 @@ eelf32mcore.c: $(srcdir)/emulparams/elf32mcore.sh \
em32relf.c: $(srcdir)/emulparams/m32relf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32relf "$(tdir_m32r)"
em32rlelf.c: $(srcdir)/emulparams/m32rlelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32rlelf "$(tdir_m32rlelf)"
em32relf_linux.c: $(srcdir)/emulparams/m32relf_linux.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32relf_linux "$(tdir_m32relf_linux)"
em32rlelf_linux.c: $(srcdir)/emulparams/m32rlelf_linux.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32rlelf_linux "$(tdir_m32rlelf_linux)"
eelf32_sparc.c: $(srcdir)/emulparams/elf32_sparc.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32_sparc "$(tdir_elf32_sparc)"

18
ld/Makefile.in
View File

@ -1,4 +1,4 @@
# Makefile.in generated automatically by automake 1.4-p6 from Makefile.am
# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am
# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc.
# This Makefile.in is free software; the Free Software Foundation
@ -344,6 +344,9 @@ ALL_EMULATIONS = \
ei386pe_posix.o \
elnk960.o \
em32relf.o \
em32rlelf.o \
em32relf_linux.o \
em32rlelf_linux.o \
em68hc11elf.o \
em68hc11elfb.o \
em68hc12elf.o \
@ -598,7 +601,7 @@ deffilep.c ldgram.c ldlex.c
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = $(ld_new_SOURCES) $(EXTRA_ld_new_SOURCES)
OBJECTS = $(ld_new_OBJECTS)
@ -1080,7 +1083,7 @@ distclean-generic:
-test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES)
maintainer-clean-generic:
-test -z "ldlex.cdeffilep.hdeffilep.cldgram.hldgram.c$(MAINTAINERCLEANFILES)" || rm -f ldlex.c deffilep.h deffilep.c ldgram.h ldgram.c $(MAINTAINERCLEANFILES)
-test -z "ldlexldeffilephdeffilepcldgramhldgramc$(MAINTAINERCLEANFILES)" || rm -f ldlexl deffileph deffilepc ldgramh ldgramc $(MAINTAINERCLEANFILES)
mostlyclean-am: mostlyclean-hdr mostlyclean-noinstPROGRAMS \
mostlyclean-compile mostlyclean-libtool \
mostlyclean-aminfo mostlyclean-tags mostlyclean-generic \
@ -1329,6 +1332,15 @@ eelf32mcore.c: $(srcdir)/emulparams/elf32mcore.sh \
em32relf.c: $(srcdir)/emulparams/m32relf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32relf "$(tdir_m32r)"
em32rlelf.c: $(srcdir)/emulparams/m32rlelf.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32rlelf "$(tdir_m32rlelf)"
em32relf_linux.c: $(srcdir)/emulparams/m32relf_linux.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32relf_linux "$(tdir_m32relf_linux)"
em32rlelf_linux.c: $(srcdir)/emulparams/m32rlelf_linux.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} m32rlelf_linux "$(tdir_m32rlelf_linux)"
eelf32_sparc.c: $(srcdir)/emulparams/elf32_sparc.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32_sparc "$(tdir_elf32_sparc)"

2
ld/NEWS
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@ -1,5 +1,7 @@
-*- text -*-
* m32r Linux (ELF) support added by Renesas.
* Improved linker's handling of unresolved symbols. The switch
--unresolved-symbols=<method> has been added to tell the linker when it
should report them and the switch --warn-unresolved-symbols has been added to

5
ld/configure.tgt
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@ -115,7 +115,10 @@ ia64-*-freebsd* | ia64-*-kfreebsd*-gnu)
ia64-*-netbsd*) targ_emul=elf64_ia64 ;;
ia64-*-linux*) targ_emul=elf64_ia64 ;;
ia64-*-aix*) targ_emul=elf64_aix ;;
m32r-*-*) targ_emul=m32relf ;;
m32r*le-*-elf*) targ_emul=m32rlelf ;;
m32r*-*-elf*) targ_emul=m32relf ;;
m32r*le-*-linux-gnu*) targ_emul=m32rlelf_linux ;;
m32r*-*-linux-gnu*) targ_emul=m32relf_linux ;;
m68hc11-*-*|m6811-*-*) targ_emul=m68hc11elf
targ_extra_emuls="m68hc11elfb m68hc12elf m68hc12elfb" ;;
m68hc12-*-*|m6812-*-*) targ_emul=m68hc12elf

13
ld/emulparams/m32relf_linux.sh Normal file
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@ -0,0 +1,13 @@
MACHINE=
SCRIPT_NAME=elf
TEMPLATE_NAME=elf32
OUTPUT_FORMAT="elf32-m32r-linux"
TEXT_START_ADDR=0x1000
ARCH=m32r
MACHINE=
MAXPAGESIZE=0x1000
# Hmmm, there's got to be a better way. This sets the stack to the
# top of simulator memory (32MB).
OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = 0x2000000);'
GENERATE_SHLIB_SCRIPT=yes

2
ld/emulparams/m32rlelf.sh Normal file
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@ -0,0 +1,2 @@
. ${srcdir}/emulparams/m32relf.sh
OUTPUT_FORMAT="elf32-m32rle"

2
ld/emulparams/m32rlelf_linux.sh Normal file
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@ -0,0 +1,2 @@
. ${srcdir}/emulparams/m32relf_linux.sh
OUTPUT_FORMAT="elf32-m32rle-linux"

4
sim/common/ChangeLog
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@ -1,3 +1,7 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* sim-core.c (sim_core_trans_addr): Added for m32r-linux-run.
2003-11-22 Kazu Hirata <kazu@cs.umass.edu>
* sim-options.c (standard_options): Fix the names of H8

19
sim/common/sim-core.c
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@ -801,6 +801,25 @@ sim_core_xor_write_buffer (SIM_DESC sd,
}
#endif
#if EXTERN_SIM_CORE_P
void *
sim_core_trans_addr (SIM_DESC sd,
sim_cpu *cpu,
unsigned map,
address_word addr)
{
sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
sim_core_mapping *mapping =
sim_core_find_mapping (core, map,
addr, /*nr-bytes*/1,
write_transfer,
0 /*dont-abort*/, NULL, NULL_CIA);
if (mapping == NULL)
return NULL;
return sim_core_translate(mapping, addr);
}
#endif
/* define the read/write 1/2/4/8/16/word functions */

12
sim/m32r/ChangeLog
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@ -1,3 +1,15 @@
2003-12-19 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* configure.in: Changed for dummy simulator of m32r-linux.
* configure: Regenerate.
* Makefile.in: Added traps-linux.o for dummy simulator of m32r-linux.
* traps-linux.c: Added for dummy simulator of m32r-linux.
* syscall.h: Ditto.
* sim-if.c (sim_create_inferior): Changed to setup SP for dummy
simulator for m32r-linux.
* sim-main.h (M32R_DEFAULT_MEM_SIZE): Changed for dummy simulator of
m32r-linux.
2003-12-11 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in: Add support for new machine m32r2.

7
sim/m32r/Makefile.in
View File

@ -23,6 +23,7 @@
M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
TRAPS_OBJ = @traps_obj@
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
@ -40,7 +41,8 @@ SIM_OBJS = \
$(M32R_OBJS) \
$(M32RX_OBJS) \
$(M32R2_OBJS) \
traps.o devices.o \
$(TRAPS_OBJ) \
devices.o \
$(CONFIG_DEVICES)
# Extra headers included by sim-main.h.
@ -48,7 +50,7 @@ SIM_EXTRA_DEPS = \
$(CGEN_INCLUDE_DEPS) \
arch.h cpuall.h m32r-sim.h $(srcdir)/../../opcodes/m32r-desc.h
SIM_EXTRA_CFLAGS =
SIM_EXTRA_CFLAGS = @sim_extra_cflags@
SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = m32r-clean
@ -65,6 +67,7 @@ sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
arch.o: arch.c $(SIM_MAIN_DEPS)
traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
traps-linux.o: traps.c syscall.h targ-vals.h $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)
# M32R objs

16
sim/m32r/configure vendored
View File

@ -3848,6 +3848,20 @@ fi
case "${target_alias}" in
m32r*-linux*)
traps_obj=traps-linux.o
sim_extra_cflags="-DM32R_LINUX"
;;
*)
traps_obj=traps.o
sim_extra_cflags="-DM32R_ELF"
;;
esac
trap '' 1 2 15
@ -4061,6 +4075,8 @@ s%@EXEEXT@%$EXEEXT%g
s%@CGEN_MAINT@%$CGEN_MAINT%g
s%@cgendir@%$cgendir%g
s%@cgen@%$cgen%g
s%@traps_obj@%$traps_obj%g
s%@sim_extra_cflags@%$sim_extra_cflags%g
CEOF
EOF

14
sim/m32r/configure.in
View File

@ -14,4 +14,18 @@ SIM_AC_OPTION_ENVIRONMENT
SIM_AC_OPTION_INLINE()
SIM_AC_OPTION_CGEN_MAINT
case "${target_alias}" in
m32r*-linux*)
traps_obj=traps-linux.o
sim_extra_cflags="-DM32R_LINUX"
;;
*)
traps_obj=traps.o
sim_extra_cflags="-DM32R_ELF"
;;
esac
AC_SUBST(traps_obj)
AC_SUBST(sim_extra_cflags)
SIM_AC_OUTPUT

7
sim/m32r/sim-if.c
View File

@ -214,6 +214,13 @@ sim_create_inferior (sd, abfd, argv, envp)
addr = 0;
sim_pc_set (current_cpu, addr);
#ifdef M32R_LINUX
m32rbf_h_cr_set (current_cpu,
m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
m32rbf_h_cr_set (current_cpu,
m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
#endif
#if 0
STATE_ARGV (sd) = sim_copy_argv (argv);
STATE_ENVP (sd) = sim_copy_argv (envp);

4
sim/m32r/sim-main.h
View File

@ -85,6 +85,10 @@ m32r_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
(TRANSFER), (ERROR))
/* Default memory size. */
#ifdef M32R_LINUX
#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
#else
#define M32R_DEFAULT_MEM_SIZE 0x800000 /* 8M */
#endif
#endif /* SIM_MAIN_H */

195
sim/m32r/syscall.h Normal file
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@ -0,0 +1,195 @@
/*
* This file contains the system call numbers.
*/
#define __NR_exit 1
#define __NR_fork 2
#define __NR_read 3
#define __NR_write 4
#define __NR_open 5
#define __NR_close 6
#define __NR_waitpid 7
#define __NR_creat 8
#define __NR_link 9
#define __NR_unlink 10
#define __NR_execve 11
#define __NR_chdir 12
#define __NR_time 13
#define __NR_mknod 14
#define __NR_chmod 15
#define __NR_lchown 16
#define __NR_break 17
#define __NR_oldstat 18
#define __NR_lseek 19
#define __NR_getpid 20
#define __NR_mount 21
#define __NR_umount 22
#define __NR_setuid 23
#define __NR_getuid 24
#define __NR_stime 25
#define __NR_ptrace 26
#define __NR_alarm 27
#define __NR_oldfstat 28
#define __NR_pause 29
#define __NR_utime 30
#define __NR_stty 31
#define __NR_gtty 32
#define __NR_access 33
#define __NR_nice 34
#define __NR_ftime 35
#define __NR_sync 36
#define __NR_kill 37
#define __NR_rename 38
#define __NR_mkdir 39
#define __NR_rmdir 40
#define __NR_dup 41
#define __NR_pipe 42
#define __NR_times 43
#define __NR_prof 44
#define __NR_brk 45
#define __NR_setgid 46
#define __NR_getgid 47
#define __NR_signal 48
#define __NR_geteuid 49
#define __NR_getegid 50
#define __NR_acct 51
#define __NR_umount2 52
#define __NR_lock 53
#define __NR_ioctl 54
#define __NR_fcntl 55
#define __NR_mpx 56
#define __NR_setpgid 57
#define __NR_ulimit 58
#define __NR_oldolduname 59
#define __NR_umask 60
#define __NR_chroot 61
#define __NR_ustat 62
#define __NR_dup2 63
#define __NR_getppid 64
#define __NR_getpgrp 65
#define __NR_setsid 66
#define __NR_sigaction 67
#define __NR_sgetmask 68
#define __NR_ssetmask 69
#define __NR_setreuid 70
#define __NR_setregid 71
#define __NR_sigsuspend 72
#define __NR_sigpending 73
#define __NR_sethostname 74
#define __NR_setrlimit 75
#define __NR_getrlimit 76
#define __NR_getrusage 77
#define __NR_gettimeofday 78
#define __NR_settimeofday 79
#define __NR_getgroups 80
#define __NR_setgroups 81
#define __NR_select 82
#define __NR_symlink 83
#define __NR_oldlstat 84
#define __NR_readlink 85
#define __NR_uselib 86
#define __NR_swapon 87
#define __NR_reboot 88
#define __NR_readdir 89
#define __NR_mmap 90
#define __NR_munmap 91
#define __NR_truncate 92
#define __NR_ftruncate 93
#define __NR_fchmod 94
#define __NR_fchown 95
#define __NR_getpriority 96
#define __NR_setpriority 97
#define __NR_profil 98
#define __NR_statfs 99
#define __NR_fstatfs 100
#define __NR_ioperm 101
#define __NR_socketcall 102
#define __NR_syslog 103
#define __NR_setitimer 104
#define __NR_getitimer 105
#define __NR_stat 106
#define __NR_lstat 107
#define __NR_fstat 108
#define __NR_olduname 109
#define __NR_iopl 110
#define __NR_vhangup 111
#define __NR_idle 112
#define __NR_vm86old 113
#define __NR_wait4 114
#define __NR_swapoff 115
#define __NR_sysinfo 116
#define __NR_ipc 117
#define __NR_fsync 118
#define __NR_sigreturn 119
#define __NR_clone 120
#define __NR_setdomainname 121
#define __NR_uname 122
#define __NR_modify_ldt 123
#define __NR_adjtimex 124
#define __NR_mprotect 125
#define __NR_sigprocmask 126
#define __NR_create_module 127
#define __NR_init_module 128
#define __NR_delete_module 129
#define __NR_get_kernel_syms 130
#define __NR_quotactl 131
#define __NR_getpgid 132
#define __NR_fchdir 133
#define __NR_bdflush 134
#define __NR_sysfs 135
#define __NR_personality 136
#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
#define __NR_setfsuid 138
#define __NR_setfsgid 139
#define __NR__llseek 140
#define __NR_getdents 141
#define __NR__newselect 142
#define __NR_flock 143
#define __NR_msync 144
#define __NR_readv 145
#define __NR_writev 146
#define __NR_getsid 147
#define __NR_fdatasync 148
#define __NR__sysctl 149
#define __NR_mlock 150
#define __NR_munlock 151
#define __NR_mlockall 152
#define __NR_munlockall 153
#define __NR_sched_setparam 154
#define __NR_sched_getparam 155
#define __NR_sched_setscheduler 156
#define __NR_sched_getscheduler 157
#define __NR_sched_yield 158
#define __NR_sched_get_priority_max 159
#define __NR_sched_get_priority_min 160
#define __NR_sched_rr_get_interval 161
#define __NR_nanosleep 162
#define __NR_mremap 163
#define __NR_setresuid 164
#define __NR_getresuid 165
#define __NR_vm86 166
#define __NR_query_module 167
#define __NR_poll 168
#define __NR_nfsservctl 169
#define __NR_setresgid 170
#define __NR_getresgid 171
#define __NR_prctl 172
#define __NR_rt_sigreturn 173
#define __NR_rt_sigaction 174
#define __NR_rt_sigprocmask 175
#define __NR_rt_sigpending 176
#define __NR_rt_sigtimedwait 177
#define __NR_rt_sigqueueinfo 178
#define __NR_rt_sigsuspend 179
#define __NR_pread 180
#define __NR_pwrite 181
#define __NR_chown 182
#define __NR_getcwd 183
#define __NR_capget 184
#define __NR_capset 185
#define __NR_sigaltstack 186
#define __NR_sendfile 187
#define __NR_getpmsg 188 /* some people actually want streams */
#define __NR_putpmsg 189 /* some people actually want streams */
#define __NR_vfork 190

1392
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