* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
This commit is contained in:
Mark Alexander
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@ -1,5 +1,14 @@
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Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
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* interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
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Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* gencode.c (print_igen_insn_models): Assume certain architectures
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include all mips* instructions.
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(print_igen_insn_format): Use data_size==-1 as marker for MIPS16
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instruction.
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* Makefile.in (tmp.igen): Add target. Generate igen input from
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gencode file.
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@ -121,6 +121,7 @@ struct sim_state simulator;
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#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
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#define Trap (13)
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#define FPE (15)
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#define DebugBreakPoint (16)
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#define Watch (23)
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/* The following exception code is actually private to the simulator
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@ -231,6 +232,9 @@ static int register_widths[LAST_EMBED_REGNUM + 1];
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#define FCR31IDX (70)
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#define FCR31 (registers[FCR31IDX]) /* really a 32bit register */
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#define FCSR (FCR31)
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#define Debug (registers[86])
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#define DEPC (registers[87])
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#define EPC (registers[88])
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#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
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/* The following are pseudonyms for standard registers */
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@ -244,6 +248,13 @@ static int register_widths[LAST_EMBED_REGNUM + 1];
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#define RA (registers[31])
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/* Bits in the Debug register */
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#define Debug_DBD 0x80000000 /* Debug Branch Delay */
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#define Debug_DM 0x40000000 /* Debug Mode */
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#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
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/* start-sanitize-r5900 */
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/*
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The R5900 has 128 bit registers, but the hi 64 bits are only touched by
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@ -368,8 +379,6 @@ GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
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static ut_reg SA; /* the shift amount register */
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/* end-sanitize-r5900 */
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static ut_reg EPC = 0; /* Exception PC */
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#if defined(HASFPU)
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/* Keep the current format state for each register: */
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static FP_formats fpr_state[32];
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@ -580,6 +589,7 @@ static unsigned int instruction_fetch_overflow = 0;
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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static unsigned int state = 0;
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static unsigned int dsstate;
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#define DELAYSLOT() {\
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if (state & simDELAYSLOT)\
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@ -597,6 +607,11 @@ static unsigned int state = 0;
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state |= simSKIPNEXT;\
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}
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#define CANCELDELAYSLOT() {\
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dsstate = 0;\
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state &= ~(simDELAYSLOT | simJALDELAYSLOT);\
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}
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#define INDELAYSLOT() ((state & simDELAYSLOT) != 0)
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#define INJALDELAYSLOT() ((state & simJALDELAYSLOT) != 0)
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@ -2736,17 +2751,63 @@ SignalException (int exception,...)
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{
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int vector;
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SIM_DESC sd = &simulator;
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#ifdef DEBUG
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callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%s\n",exception,pr_addr(IPC));
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#endif /* DEBUG */
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/* Ensure that any active atomic read/modify/write operation will fail: */
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LLBIT = 0;
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switch (exception) {
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/* TODO: For testing purposes I have been ignoring TRAPs. In
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reality we should either simulate them, or allow the user to
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ignore them at run-time. */
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ignore them at run-time.
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Same for SYSCALL */
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case Trap :
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sim_warning("Ignoring instruction TRAP (PC 0x%s)",pr_addr(IPC));
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break;
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case SystemCall :
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{
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va_list ap;
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unsigned int instruction;
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unsigned int code;
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va_start(ap,exception);
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instruction = va_arg(ap,unsigned int);
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va_end(ap);
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code = (instruction >> 6) & 0xFFFFF;
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sim_warning("Ignoring instruction `syscall %d' (PC 0x%s)",
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code, pr_addr(IPC));
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}
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break;
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case DebugBreakPoint :
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if (! (Debug & Debug_DM))
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{
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if (INDELAYSLOT())
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{
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CANCELDELAYSLOT();
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Debug |= Debug_DBD; /* signaled from within in delay slot */
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DEPC = IPC - 4; /* reference the branch instruction */
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}
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else
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{
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Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
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DEPC = IPC;
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}
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Debug |= Debug_DM; /* in debugging mode */
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Debug |= Debug_DBp; /* raising a DBp exception */
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PC = 0xBFC00200;
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sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA);
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}
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break;
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case ReservedInstruction :
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{
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va_list ap;
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@ -3964,7 +4025,7 @@ COP_LW(coproc_num,coproc_reg,memword)
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return;
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}
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static void
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static void UNUSED
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COP_LD(coproc_num,coproc_reg,memword)
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int coproc_num, coproc_reg;
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uword64 memword;
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@ -4026,7 +4087,7 @@ COP_SW(coproc_num,coproc_reg)
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return(value);
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}
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static uword64
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static uword64 UNUSED
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COP_SD(coproc_num,coproc_reg)
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int coproc_num, coproc_reg;
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{
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@ -4117,8 +4178,28 @@ decode_coproc(instruction)
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break;
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/* 14 = EPC R4000 VR4100 VR4300 */
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/* 15 = PRId R4000 VR4100 VR4300 */
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#ifdef SUBTARGET_R3900
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/* 16 = Debug */
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case 16:
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if (code == 0x00)
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GPR[rt] = Debug;
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else
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Debug = GPR[rt];
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break;
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#else
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/* 16 = Config R4000 VR4100 VR4300 */
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#endif
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#ifdef SUBTARGET_R3900
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/* 17 = Debug */
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case 17:
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if (code == 0x00)
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GPR[rt] = DEPC;
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else
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DEPC = GPR[rt];
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break;
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#else
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/* 17 = LLAddr R4000 VR4100 VR4300 */
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#endif
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/* 18 = WatchLo R4000 VR4100 VR4300 */
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/* 19 = WatchHi R4000 VR4100 VR4300 */
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/* 20 = XContext R4000 VR4100 VR4300 */
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@ -4152,6 +4233,17 @@ decode_coproc(instruction)
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SR &= ~status_EXL;
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}
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}
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else if (code == 0x10 && (instruction & 0x3f) == 0x10)
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{
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/* RFE */
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}
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else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
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{
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/* DERET */
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Debug &= ~Debug_DM;
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DELAYSLOT();
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DSPC = DEPC;
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}
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else
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sim_warning("Unrecognised COP0 instruction 0x%08X at IPC = 0x%s : No handler present",instruction,pr_addr(IPC));
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/* TODO: When executing an ERET or RFE instruction we should
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@ -4206,7 +4298,6 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
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uword64 paddr;
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int cca;
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unsigned int instruction; /* uword64? what's this used for? FIXME! */
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int dsstate = (state & simDELAYSLOT);
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#ifdef DEBUG
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{
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@ -4224,6 +4315,7 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
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}
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#endif /* DEBUG */
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dsstate = (state & simDELAYSLOT);
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#ifdef DEBUG
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if (dsstate)
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callback->printf_filtered(callback,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
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@ -4386,7 +4478,7 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
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printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
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#endif /* DEBUG */
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PC = DSPC;
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state &= ~(simDELAYSLOT | simJALDELAYSLOT);
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CANCELDELAYSLOT();
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}
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if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
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