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Updates the ARM disassembler's output of floating point constants to include the actual floating point value.

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opcodes	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	float bitfield format.
	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	quarter float bitfield format.

tests	* gas/arm/vfpv3-const-conv.d: Update expected result due to change
	of comment for vmov reg,immediate with VFP coprocessor.
This commit is contained in:
Alessandro Marzocchi 2015-07-16 16:38:48 +01:00 committed by Nick Clifton
parent 53c3012ccc
commit 6f1c214259
3 changed files with 42 additions and 4 deletions
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4
gas/testsuite/gas/arm/vfpv3-const-conv.d
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@ -5,10 +5,10 @@
.*: +file format .*arm.*
Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4
0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4.*
0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165.*
0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64.*
0[0-9a-f]+ <[^>]+> eef01b04 (vmov\.f64|fconstd) d17, #4
0[0-9a-f]+ <[^>]+> eef01b04 (vmov\.f64|fconstd) d17, #4.*
0[0-9a-f]+ <[^>]+> eefa2b05 (vmov\.f64|fconstd) d18, #165.*
0[0-9a-f]+ <[^>]+> eef43b00 (vmov\.f64|fconstd) d19, #64.*
0[0-9a-f]+ <[^>]+> eefa8a63 (vcvt\.f32\.s16 s17, s17, #9|fshtos s17, #9)

7
opcodes/ChangeLog
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@ -1,3 +1,10 @@
2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
* arm-dis.c (print_insn_coprocessor): Added support for quarter
float bitfield format.
(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
quarter float bitfield format.
2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.

35
opcodes/arm-dis.c
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@ -115,6 +115,7 @@ struct opcode16
%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%<bitfield>E print a quarter-float immediate value
%y<code> print a single precision VFP reg.
Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
@ -578,9 +579,9 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
@ -3467,6 +3468,36 @@ print_insn_coprocessor (bfd_vma pc,
func (stream, "%ld", value);
value_in_comment = value;
break;
case 'E':
{
/* Converts immediate 8 bit back to float value. */
unsigned floatVal = (value & 0x80) << 24
| (value & 0x3F) << 19
| ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
/* Quarter float have a maximum value of 31.0.
Get floating point value multiplied by 1e7.
The maximum value stays in limit of a 32-bit int. */
unsigned decVal =
(78125 << (((floatVal >> 23) & 0xFF) - 124)) *
(16 + (value & 0xF));
if (!(decVal % 1000000))
func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000,
decVal % 10000000 / 1000000);
else if (!(decVal % 10000))
func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000,
decVal % 10000000 / 10000);
else
func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
floatVal, value & 0x80 ? '-' : ' ',
decVal / 10000000, decVal % 10000000);
break;
}
case 'k':
{
int from = (given & (1 << 7)) ? 32 : 16;