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sim: m68hc11: standardize sim_cpu naming 

We use "sim_cpu *cpu" in the sim code base, not "struct _sim_cpu" or
the name "proc", so clean up this sim to follow along.
This commit is contained in:
Mike Frysinger 2016-08-13 08:44:24 -07:00
parent 527aaa4a31
commit 6f64fd48c5
10 changed files with 361 additions and 342 deletions
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19
sim/m68hc11/ChangeLog
View File

@ -1,3 +1,22 @@
2016-08-13 Mike Frysinger <vapier@gentoo.org>
* dv-m68hc11.c (m68hc11cpu_port_event): Adjust cpu prototype style.
* dv-m68hc11spi.c (m68hc11spi_port_event): Likewise.
* dv-m68hc11tim.c (m68hc11tim_print_timer): Likewise.
* emulos.c (emul_bench): Likewise.
(emul_write): Likewise. Also rename state to cpu.
(emul_os): Rename proc to cpu.
* gencode.c: Rename proc to cpu.
* interrupts.c (interrupts_initialize): Likewise.
* interrupts.h (interrupts): Adjust cpu type.
(interrupts_initialize): Likewise.
* m68hc11_sim.c (cpu_get_reg): Adjust cpu prototype style.
(cpu_get_src_reg, cpu_set_dst_reg, cpu_set_reg,
cpu_get_indexed_operand_addr, cpu_get_indexed_operand8,
cpu_get_indexed_operand16, cpu_dbcc, cpu_exg): Likewise.
(cpu_ccr_update_tst8): Rename proc to cpu.
* sim-main.h: Rename PROC and proc to cpu.
2016-08-13 Mike Frysinger <vapier@gentoo.org>
* dv-m68hc11eepr.c (attach_m68hc11eepr_regs): Drop cast with

2
sim/m68hc11/dv-m68hc11.c
View File

@ -496,7 +496,7 @@ m68hc11cpu_port_event (struct hw *me,
{
struct m68hc11cpu *controller = hw_data (me);
SIM_DESC sd;
sim_cpu* cpu;
sim_cpu *cpu;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);

2
sim/m68hc11/dv-m68hc11spi.c
View File

@ -156,7 +156,7 @@ m68hc11spi_port_event (struct hw *me,
{
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu* cpu;
sim_cpu *cpu;
unsigned8 val;
controller = hw_data (me);

2
sim/m68hc11/dv-m68hc11tim.c
View File

@ -521,7 +521,7 @@ m68hc11tim_print_timer (struct hw *me, const char *name,
else
{
signed64 t;
sim_cpu* cpu;
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);

22
sim/m68hc11/emulos.c
View File

@ -34,7 +34,7 @@ static struct timeval bench_start;
static struct timeval bench_stop;
static void
emul_bench (struct _sim_cpu* cpu)
emul_bench (sim_cpu *cpu)
{
int op;
@ -91,18 +91,18 @@ emul_bench (struct _sim_cpu* cpu)
#endif
static void
emul_write(struct _sim_cpu* state)
emul_write (sim_cpu *cpu)
{
int addr = cpu_get_x (state) & 0x0FFFF;
int size = cpu_get_d (state) & 0x0FFFF;
int addr = cpu_get_x (cpu) & 0x0FFFF;
int size = cpu_get_d (cpu) & 0x0FFFF;
if (addr + size > 0x0FFFF) {
size = 0x0FFFF - addr;
}
state->cpu_running = 0;
cpu->cpu_running = 0;
while (size)
{
uint8 val = memory_read8 (state, addr);
uint8 val = memory_read8 (cpu, addr);
write(0, &val, 1);
addr ++;
@ -124,9 +124,9 @@ emul_exit (sim_cpu *cpu)
}
void
emul_os (int code, sim_cpu *proc)
emul_os (int code, sim_cpu *cpu)
{
proc->cpu_current_cycle = 8;
cpu->cpu_current_cycle = 8;
switch (code)
{
case 0x0:
@ -134,7 +134,7 @@ emul_os (int code, sim_cpu *proc)
/* 0xCD 0x01 */
case 0x01:
emul_write (proc);
emul_write (cpu);
break;
/* 0xCD 0x02 */
@ -143,13 +143,13 @@ emul_os (int code, sim_cpu *proc)
/* 0xCD 0x03 */
case 0x03:
emul_exit (proc);
emul_exit (cpu);
break;
/* 0xCD 0x04 */
case 0x04:
#ifndef WIN32
emul_bench (proc);
emul_bench (cpu);
#endif
break;

352
sim/m68hc11/gencode.c
View File

@ -90,134 +90,134 @@ struct m6811_opcode_pattern
struct m6811_opcode_pattern m6811_opcode_patterns[] = {
/* Move 8 and 16 bits. We need two implementations: one that sets the
flags and one that preserve them. */
{ "movtst8", "dst8 = src8", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "movtst16", "dst16 = src16", "cpu_ccr_update_tst16 (proc, dst16)" },
{ "movtst8", "dst8 = src8", "cpu_ccr_update_tst8 (cpu, dst8)" },
{ "movtst16", "dst16 = src16", "cpu_ccr_update_tst16 (cpu, dst16)" },
{ "mov8", "dst8 = src8" },
{ "mov16", "dst16 = src16" },
{ "lea16", "dst16 = addr" },
/* Conditional branches. 'addr' is the address of the branch. */
{ "bra", "cpu_set_pc (proc, addr)" },
{ "bra", "cpu_set_pc (cpu, addr)" },
{ "bhi",
"if ((cpu_get_ccr (proc) & (M6811_C_BIT|M6811_Z_BIT)) == 0)\n@ \
cpu_set_pc (proc, addr)" },
"if ((cpu_get_ccr (cpu) & (M6811_C_BIT|M6811_Z_BIT)) == 0)\n@ \
cpu_set_pc (cpu, addr)" },
{ "bls",
"if ((cpu_get_ccr (proc) & (M6811_C_BIT|M6811_Z_BIT)))\n@ \
cpu_set_pc (proc, addr)" },
{ "bcc", "if (!cpu_get_ccr_C (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bcs", "if (cpu_get_ccr_C (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bne", "if (!cpu_get_ccr_Z (proc))\n@ cpu_set_pc (proc, addr)" },
{ "beq", "if (cpu_get_ccr_Z (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bvc", "if (!cpu_get_ccr_V (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bvs", "if (cpu_get_ccr_V (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bpl", "if (!cpu_get_ccr_N (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bmi", "if (cpu_get_ccr_N (proc))\n@ cpu_set_pc (proc, addr)" },
{ "bge", "if ((cpu_get_ccr_N (proc) ^ cpu_get_ccr_V (proc)) == 0)\n@ cpu_set_pc (proc, addr)" },
{ "blt", "if ((cpu_get_ccr_N (proc) ^ cpu_get_ccr_V (proc)))\n@ cpu_set_pc (proc, addr)" },
"if ((cpu_get_ccr (cpu) & (M6811_C_BIT|M6811_Z_BIT)))\n@ \
cpu_set_pc (cpu, addr)" },
{ "bcc", "if (!cpu_get_ccr_C (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bcs", "if (cpu_get_ccr_C (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bne", "if (!cpu_get_ccr_Z (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "beq", "if (cpu_get_ccr_Z (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bvc", "if (!cpu_get_ccr_V (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bvs", "if (cpu_get_ccr_V (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bpl", "if (!cpu_get_ccr_N (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bmi", "if (cpu_get_ccr_N (cpu))\n@ cpu_set_pc (cpu, addr)" },
{ "bge", "if ((cpu_get_ccr_N (cpu) ^ cpu_get_ccr_V (cpu)) == 0)\n@ cpu_set_pc (cpu, addr)" },
{ "blt", "if ((cpu_get_ccr_N (cpu) ^ cpu_get_ccr_V (cpu)))\n@ cpu_set_pc (cpu, addr)" },
{ "bgt",
"if ((cpu_get_ccr_Z (proc) | (cpu_get_ccr_N (proc) ^ cpu_get_ccr_V (proc))) == 0)\n@ \
cpu_set_pc (proc, addr)" },
"if ((cpu_get_ccr_Z (cpu) | (cpu_get_ccr_N (cpu) ^ cpu_get_ccr_V (cpu))) == 0)\n@ \
cpu_set_pc (cpu, addr)" },
{ "ble",
"if ((cpu_get_ccr_Z (proc) | (cpu_get_ccr_N (proc) ^ cpu_get_ccr_V (proc))))\n@ \
cpu_set_pc (proc, addr)" },
"if ((cpu_get_ccr_Z (cpu) | (cpu_get_ccr_N (cpu) ^ cpu_get_ccr_V (cpu))))\n@ \
cpu_set_pc (cpu, addr)" },
/* brclr and brset perform a test and a conditional jump at the same
time. Flags are not changed. */
{ "brclr8",
"if ((src8 & dst8) == 0)\n@ cpu_set_pc (proc, addr)" },
"if ((src8 & dst8) == 0)\n@ cpu_set_pc (cpu, addr)" },
{ "brset8",
"if (((~src8) & dst8) == 0)\n@ cpu_set_pc (proc, addr)" },
"if (((~src8) & dst8) == 0)\n@ cpu_set_pc (cpu, addr)" },
{ "rts11", "addr = cpu_m68hc11_pop_uint16 (proc); cpu_set_pc (proc, addr); cpu_return(proc)" },
{ "rts12", "addr = cpu_m68hc12_pop_uint16 (proc); cpu_set_pc (proc, addr); cpu_return(proc)" },
{ "rts11", "addr = cpu_m68hc11_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
{ "rts12", "addr = cpu_m68hc12_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
{ "mul16", "dst16 = ((uint16) src8 & 0x0FF) * ((uint16) dst8 & 0x0FF)",
"cpu_set_ccr_C (proc, src8 & 0x80)" },
"cpu_set_ccr_C (cpu, src8 & 0x80)" },
{ "neg8", "dst8 = - src8",
"cpu_set_ccr_C (proc, src8 == 0); cpu_ccr_update_tst8 (proc, dst8)" },
"cpu_set_ccr_C (cpu, src8 == 0); cpu_ccr_update_tst8 (cpu, dst8)" },
{ "com8", "dst8 = ~src8",
"cpu_set_ccr_C (proc, 1); cpu_ccr_update_tst8 (proc, dst8);" },
"cpu_set_ccr_C (cpu, 1); cpu_ccr_update_tst8 (cpu, dst8);" },
{ "clr8", "dst8 = 0",
"cpu_set_ccr (proc, (cpu_get_ccr (proc) & (M6811_S_BIT|M6811_X_BIT|M6811_H_BIT| \
"cpu_set_ccr (cpu, (cpu_get_ccr (cpu) & (M6811_S_BIT|M6811_X_BIT|M6811_H_BIT| \
M6811_I_BIT)) | M6811_Z_BIT)"},
{ "clr16","dst16 = 0",
"cpu_set_ccr (proc, (cpu_get_ccr (proc) & (M6811_S_BIT|M6811_X_BIT|M6811_H_BIT| \
"cpu_set_ccr (cpu, (cpu_get_ccr (cpu) & (M6811_S_BIT|M6811_X_BIT|M6811_H_BIT| \
M6811_I_BIR)) | M6811_Z_BIT)"},
/* 8-bits shift and rotation. */
{ "lsr8", "dst8 = src8 >> 1",
"cpu_set_ccr_C (proc, src8 & 1); cpu_ccr_update_shift8 (proc, dst8)" },
"cpu_set_ccr_C (cpu, src8 & 1); cpu_ccr_update_shift8 (cpu, dst8)" },
{ "lsl8", "dst8 = src8 << 1",
"cpu_set_ccr_C (proc, (src8 & 0x80) >> 7); cpu_ccr_update_shift8 (proc, dst8)" },
"cpu_set_ccr_C (cpu, (src8 & 0x80) >> 7); cpu_ccr_update_shift8 (cpu, dst8)" },
{ "asr8", "dst8 = (src8 >> 1) | (src8 & 0x80)",
"cpu_set_ccr_C (proc, src8 & 1); cpu_ccr_update_shift8 (proc, dst8)" },
{ "ror8", "dst8 = (src8 >> 1) | (cpu_get_ccr_C (proc) << 7)",
"cpu_set_ccr_C (proc, src8 & 1); cpu_ccr_update_shift8 (proc, dst8)" },
{ "rol8", "dst8 = (src8 << 1) | (cpu_get_ccr_C (proc))",
"cpu_set_ccr_C (proc, (src8 & 0x80) >> 7); cpu_ccr_update_shift8 (proc, dst8)" },
"cpu_set_ccr_C (cpu, src8 & 1); cpu_ccr_update_shift8 (cpu, dst8)" },
{ "ror8", "dst8 = (src8 >> 1) | (cpu_get_ccr_C (cpu) << 7)",
"cpu_set_ccr_C (cpu, src8 & 1); cpu_ccr_update_shift8 (cpu, dst8)" },
{ "rol8", "dst8 = (src8 << 1) | (cpu_get_ccr_C (cpu))",
"cpu_set_ccr_C (cpu, (src8 & 0x80) >> 7); cpu_ccr_update_shift8 (cpu, dst8)" },
/* 16-bits shift instructions. */
{ "lsl16", "dst16 = src16 << 1",
"cpu_set_ccr_C (proc, (src16&0x8000) >> 15); cpu_ccr_update_shift16 (proc, dst16)"},
"cpu_set_ccr_C (cpu, (src16&0x8000) >> 15); cpu_ccr_update_shift16 (cpu, dst16)"},
{ "lsr16", "dst16 = src16 >> 1",
"cpu_set_ccr_C (proc, src16 & 1); cpu_ccr_update_shift16 (proc, dst16)"},
"cpu_set_ccr_C (cpu, src16 & 1); cpu_ccr_update_shift16 (cpu, dst16)"},
{ "dec8", "dst8 = src8 - 1", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "inc8", "dst8 = src8 + 1", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "tst8", 0, "cpu_set_ccr_C (proc, 0); cpu_ccr_update_tst8 (proc, src8)" },
{ "dec8", "dst8 = src8 - 1", "cpu_ccr_update_tst8 (cpu, dst8)" },
{ "inc8", "dst8 = src8 + 1", "cpu_ccr_update_tst8 (cpu, dst8)" },
{ "tst8", 0, "cpu_set_ccr_C (cpu, 0); cpu_ccr_update_tst8 (cpu, src8)" },
{ "sub8", "cpu_ccr_update_sub8 (proc, dst8 - src8, dst8, src8);\
{ "sub8", "cpu_ccr_update_sub8 (cpu, dst8 - src8, dst8, src8);\
dst8 = dst8 - src8", 0 },
{ "add8", "cpu_ccr_update_add8 (proc, dst8 + src8, dst8, src8);\
{ "add8", "cpu_ccr_update_add8 (cpu, dst8 + src8, dst8, src8);\
dst8 = dst8 + src8", 0 },
{ "sbc8", "if (cpu_get_ccr_C (proc))\n@ \
{ "sbc8", "if (cpu_get_ccr_C (cpu))\n@ \
{\n\
cpu_ccr_update_sub8 (proc, dst8 - src8 - 1, dst8, src8);\n\
cpu_ccr_update_sub8 (cpu, dst8 - src8 - 1, dst8, src8);\n\
dst8 = dst8 - src8 - 1;\n\
}\n\
else\n\
{\n\
cpu_ccr_update_sub8 (proc, dst8 - src8, dst8, src8);\n\
cpu_ccr_update_sub8 (cpu, dst8 - src8, dst8, src8);\n\
dst8 = dst8 - src8;\n\
}", 0 },
{ "adc8", "if (cpu_get_ccr_C (proc))\n@ \
{ "adc8", "if (cpu_get_ccr_C (cpu))\n@ \
{\n\
cpu_ccr_update_add8 (proc, dst8 + src8 + 1, dst8, src8);\n\
cpu_ccr_update_add8 (cpu, dst8 + src8 + 1, dst8, src8);\n\
dst8 = dst8 + src8 + 1;\n\
}\n\
else\n\
{\n\
cpu_ccr_update_add8 (proc, dst8 + src8, dst8, src8);\n\
cpu_ccr_update_add8 (cpu, dst8 + src8, dst8, src8);\n\
dst8 = dst8 + src8;\n\
}",
0 },
/* 8-bits logical operations. */
{ "and8", "dst8 = dst8 & src8", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "eor8", "dst8 = dst8 ^ src8", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "or8", "dst8 = dst8 | src8", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "bclr8","dst8 = (~dst8) & src8", "cpu_ccr_update_tst8 (proc, dst8)" },
{ "and8", "dst8 = dst8 & src8", "cpu_ccr_update_tst8 (cpu, dst8)" },
{ "eor8", "dst8 = dst8 ^ src8", "cpu_ccr_update_tst8 (cpu, dst8)" },
{ "or8", "dst8 = dst8 | src8", "cpu_ccr_update_tst8 (cpu, dst8)" },
{ "bclr8","dst8 = (~dst8) & src8", "cpu_ccr_update_tst8 (cpu, dst8)" },
/* 16-bits add and subtract instructions. */
{ "sub16", "cpu_ccr_update_sub16 (proc, dst16 - src16, dst16, src16);\
{ "sub16", "cpu_ccr_update_sub16 (cpu, dst16 - src16, dst16, src16);\
dst16 = dst16 - src16", 0 },
{ "add16", "cpu_ccr_update_add16 (proc, dst16 + src16, dst16, src16);\
{ "add16", "cpu_ccr_update_add16 (cpu, dst16 + src16, dst16, src16);\
dst16 = dst16 + src16", 0 },
{ "inc16", "dst16 = src16 + 1", "cpu_set_ccr_Z (proc, dst16 == 0)" },
{ "dec16", "dst16 = src16 - 1", "cpu_set_ccr_Z (proc, dst16 == 0)" },
{ "inc16", "dst16 = src16 + 1", "cpu_set_ccr_Z (cpu, dst16 == 0)" },
{ "dec16", "dst16 = src16 - 1", "cpu_set_ccr_Z (cpu, dst16 == 0)" },
/* Special increment/decrement for the stack pointer:
flags are not changed. */
{ "ins16", "dst16 = src16 + 1" },
{ "des16", "dst16 = src16 - 1" },
{ "jsr_11_16", "cpu_m68hc11_push_uint16 (proc, cpu_get_pc (proc)); cpu_call (proc, addr)"},
{ "jsr_12_16", "cpu_m68hc12_push_uint16 (proc, cpu_get_pc (proc)); cpu_call (proc, addr)"},
{ "jsr_11_16", "cpu_m68hc11_push_uint16 (cpu, cpu_get_pc (cpu)); cpu_call (cpu, addr)"},
{ "jsr_12_16", "cpu_m68hc12_push_uint16 (cpu, cpu_get_pc (cpu)); cpu_call (cpu, addr)"},
/* xgdx and xgdx patterns. Flags are not changed. */
{ "xgdxy16", "dst16 = cpu_get_d (proc); cpu_set_d (proc, src16)"},
{ "stop", "cpu_special (proc, M6811_STOP)"},
{ "xgdxy16", "dst16 = cpu_get_d (cpu); cpu_set_d (cpu, src16)"},
{ "stop", "cpu_special (cpu, M6811_STOP)"},
/* tsx, tsy, txs, tys don't affect the flags. Sp value is corrected
by +/- 1. */
@ -228,7 +228,7 @@ dst16 = dst16 + src16", 0 },
{ "abxy16","dst16 = dst16 + (uint16) src8"},
/* After 'daa', the Z flag is undefined. Mark it as changed. */
{ "daa8", "cpu_special (proc, M6811_DAA)" },
{ "daa8", "cpu_special (cpu, M6811_DAA)" },
{ "nop", 0 },
@ -238,87 +238,87 @@ dst16 = dst16 + src16", 0 },
{ "idiv16", "if (src16 == 0)\n{\n\
dst16 = 0xffff;\
}\nelse\n{\n\
cpu_set_d (proc, dst16 % src16);\
cpu_set_d (cpu, dst16 % src16);\
dst16 = dst16 / src16;\
}",
"cpu_set_ccr_Z (proc, dst16 == 0); cpu_set_ccr_V (proc, 0);\
cpu_set_ccr_C (proc, src16 == 0)" },
"cpu_set_ccr_Z (cpu, dst16 == 0); cpu_set_ccr_V (cpu, 0);\
cpu_set_ccr_C (cpu, src16 == 0)" },
/* Fractional divide:
(parallel (set IX (div (mul D 65536) IX)
(set D (mod (mul D 65536) IX)))) */
{ "fdiv16", "if (src16 <= dst16 )\n{\n\
dst16 = 0xffff;\n\
cpu_set_ccr_Z (proc, 0);\n\
cpu_set_ccr_V (proc, 1);\n\
cpu_set_ccr_C (proc, dst16 == 0);\n\
cpu_set_ccr_Z (cpu, 0);\n\
cpu_set_ccr_V (cpu, 1);\n\
cpu_set_ccr_C (cpu, dst16 == 0);\n\
}\nelse\n{\n\
unsigned long l = (unsigned long) (dst16) << 16;\n\
cpu_set_d (proc, (uint16) (l % (unsigned long) (src16)));\n\
cpu_set_d (cpu, (uint16) (l % (unsigned long) (src16)));\n\
dst16 = (uint16) (l / (unsigned long) (src16));\n\
cpu_set_ccr_V (proc, 0);\n\
cpu_set_ccr_C (proc, 0);\n\
cpu_set_ccr_Z (proc, dst16 == 0);\n\
cpu_set_ccr_V (cpu, 0);\n\
cpu_set_ccr_C (cpu, 0);\n\
cpu_set_ccr_Z (cpu, dst16 == 0);\n\
}", 0 },
/* Operations to get/set the CCR. */
{ "clv", 0, "cpu_set_ccr_V (proc, 0)" },
{ "sev", 0, "cpu_set_ccr_V (proc, 1)" },
{ "clc", 0, "cpu_set_ccr_C (proc, 0)" },
{ "sec", 0, "cpu_set_ccr_C (proc, 1)" },
{ "cli", 0, "cpu_set_ccr_I (proc, 0)" },
{ "sei", 0, "cpu_set_ccr_I (proc, 1)" },
{ "clv", 0, "cpu_set_ccr_V (cpu, 0)" },
{ "sev", 0, "cpu_set_ccr_V (cpu, 1)" },
{ "clc", 0, "cpu_set_ccr_C (cpu, 0)" },
{ "sec", 0, "cpu_set_ccr_C (cpu, 1)" },
{ "cli", 0, "cpu_set_ccr_I (cpu, 0)" },
{ "sei", 0, "cpu_set_ccr_I (cpu, 1)" },
/* Some special instructions are implemented by 'cpu_special'. */
{ "rti11", "cpu_special (proc, M6811_RTI)" },
{ "rti12", "cpu_special (proc, M6812_RTI)" },
{ "wai", "cpu_special (proc, M6811_WAI)" },
{ "test", "cpu_special (proc, M6811_TEST)" },
{ "swi", "cpu_special (proc, M6811_SWI)" },
{ "syscall","cpu_special (proc, M6811_EMUL_SYSCALL)" },
{ "rti11", "cpu_special (cpu, M6811_RTI)" },
{ "rti12", "cpu_special (cpu, M6812_RTI)" },
{ "wai", "cpu_special (cpu, M6811_WAI)" },
{ "test", "cpu_special (cpu, M6811_TEST)" },
{ "swi", "cpu_special (cpu, M6811_SWI)" },
{ "syscall","cpu_special (cpu, M6811_EMUL_SYSCALL)" },
{ "page2", "cpu_page2_interp (proc)", 0 },
{ "page3", "cpu_page3_interp (proc)", 0 },
{ "page4", "cpu_page4_interp (proc)", 0 },
{ "page2", "cpu_page2_interp (cpu)", 0 },
{ "page3", "cpu_page3_interp (cpu)", 0 },
{ "page4", "cpu_page4_interp (cpu)", 0 },
/* 68HC12 special instructions. */
{ "bgnd", "cpu_special (proc, M6812_BGND)" },
{ "call8", "cpu_special (proc, M6812_CALL)" },
{ "call_ind", "cpu_special (proc, M6812_CALL_INDIRECT)" },
{ "dbcc8", "cpu_dbcc (proc)" },
{ "ediv", "cpu_special (proc, M6812_EDIV)" },
{ "emul", "{ uint32 src1 = (uint32) cpu_get_d (proc);\
uint32 src2 = (uint32) cpu_get_y (proc);\
{ "bgnd", "cpu_special (cpu, M6812_BGND)" },
{ "call8", "cpu_special (cpu, M6812_CALL)" },
{ "call_ind", "cpu_special (cpu, M6812_CALL_INDIRECT)" },
{ "dbcc8", "cpu_dbcc (cpu)" },
{ "ediv", "cpu_special (cpu, M6812_EDIV)" },
{ "emul", "{ uint32 src1 = (uint32) cpu_get_d (cpu);\
uint32 src2 = (uint32) cpu_get_y (cpu);\
src1 *= src2;\
cpu_set_d (proc, src1);\
cpu_set_y (proc, src1 >> 16);\
cpu_set_ccr_Z (proc, src1 == 0);\
cpu_set_ccr_C (proc, src1 & 0x08000);\
cpu_set_ccr_N (proc, src1 & 0x80000000);}" },
{ "emuls", "cpu_special (proc, M6812_EMULS)" },
{ "mem", "cpu_special (proc, M6812_MEM)" },
{ "rtc", "cpu_special (proc, M6812_RTC)" },
{ "emacs", "cpu_special (proc, M6812_EMACS)" },
{ "idivs", "cpu_special (proc, M6812_IDIVS)" },
{ "edivs", "cpu_special (proc, M6812_EDIVS)" },
{ "exg8", "cpu_exg (proc, src8)" },
{ "move8", "cpu_move8 (proc, op)" },
{ "move16","cpu_move16 (proc, op)" },
cpu_set_d (cpu, src1);\
cpu_set_y (cpu, src1 >> 16);\
cpu_set_ccr_Z (cpu, src1 == 0);\
cpu_set_ccr_C (cpu, src1 & 0x08000);\
cpu_set_ccr_N (cpu, src1 & 0x80000000);}" },
{ "emuls", "cpu_special (cpu, M6812_EMULS)" },
{ "mem", "cpu_special (cpu, M6812_MEM)" },
{ "rtc", "cpu_special (cpu, M6812_RTC)" },
{ "emacs", "cpu_special (cpu, M6812_EMACS)" },
{ "idivs", "cpu_special (cpu, M6812_IDIVS)" },
{ "edivs", "cpu_special (cpu, M6812_EDIVS)" },
{ "exg8", "cpu_exg (cpu, src8)" },
{ "move8", "cpu_move8 (cpu, op)" },
{ "move16","cpu_move16 (cpu, op)" },
{ "max8", "cpu_ccr_update_sub8 (proc, dst8 - src8, dst8, src8);\
{ "max8", "cpu_ccr_update_sub8 (cpu, dst8 - src8, dst8, src8);\
if (dst8 < src8) dst8 = src8" },
{ "min8", "cpu_ccr_update_sub8 (proc, dst8 - src8, dst8, src8);\
{ "min8", "cpu_ccr_update_sub8 (cpu, dst8 - src8, dst8, src8);\
if (dst8 > src8) dst8 = src8" },
{ "max16", "cpu_ccr_update_sub16 (proc, dst16 - src16, dst16, src16);\
{ "max16", "cpu_ccr_update_sub16 (cpu, dst16 - src16, dst16, src16);\
if (dst16 < src16) dst16 = src16" },
{ "min16", "cpu_ccr_update_sub16 (proc, dst16 - src16, dst16, src16);\
{ "min16", "cpu_ccr_update_sub16 (cpu, dst16 - src16, dst16, src16);\
if (dst16 > src16) dst16 = src16" },
{ "rev", "cpu_special (proc, M6812_REV);" },
{ "revw", "cpu_special (proc, M6812_REVW);" },
{ "wav", "cpu_special (proc, M6812_WAV);" },
{ "tbl8", "cpu_special (proc, M6812_ETBL);" },
{ "tbl16", "cpu_special (proc, M6812_ETBL);" }
{ "rev", "cpu_special (cpu, M6812_REV);" },
{ "revw", "cpu_special (cpu, M6812_REVW);" },
{ "wav", "cpu_special (cpu, M6812_WAV);" },
{ "tbl8", "cpu_special (cpu, M6812_ETBL);" },
{ "tbl16", "cpu_special (cpu, M6812_ETBL);" }
};
/* Definition of an opcode of the 68HC11. */
@ -1282,12 +1282,12 @@ print (FILE *fp, int col, const char *msg, ...)
- End of input operands.
Example:
(x),a->a addr = x + (uint16) (fetch8 (proc));
(x),a->a addr = x + (uint16) (fetch8 (cpu));
src8 = a
*,#,r addr = (uint16) (fetch8 (proc)) <- Temporary 'addr'
src8 = read_mem8 (proc, addr)
dst8 = fetch8 (proc)
addr = fetch_relbranch (proc) <- Final 'addr'
*,#,r addr = (uint16) (fetch8 (cpu)) <- Temporary 'addr'
src8 = read_mem8 (cpu, addr)
dst8 = fetch8 (cpu)
addr = fetch_relbranch (cpu) <- Final 'addr'
Returns 1 if the 'addr' operand is set, 0 otherwise. */
int
@ -1315,35 +1315,35 @@ gen_fetch_operands (FILE *fp, int col,
if (cur_var >= 2)
fatal_error (opcode, "Too many locals");
print (fp, col, "%s8 = cpu_get_a (proc);", vars[cur_var]);
print (fp, col, "%s8 = cpu_get_a (cpu);", vars[cur_var]);
break;
case 'b':
if (cur_var >= 2)
fatal_error (opcode, "Too many locals");
print (fp, col, "%s8 = cpu_get_b (proc);", vars[cur_var]);
print (fp, col, "%s8 = cpu_get_b (cpu);", vars[cur_var]);
break;
case 'd':
if (cur_var >= 2)
fatal_error (opcode, "Too many locals");
print (fp, col, "%s16 = cpu_get_d (proc);", vars[cur_var]);
print (fp, col, "%s16 = cpu_get_d (cpu);", vars[cur_var]);
break;
case 'x':
if (cur_var >= 2)
fatal_error (opcode, "Too many locals");
print (fp, col, "%s16 = cpu_get_x (proc);", vars[cur_var]);
print (fp, col, "%s16 = cpu_get_x (cpu);", vars[cur_var]);
break;
case 'y':
if (cur_var >= 2)
fatal_error (opcode, "Too many locals");
print (fp, col, "%s16 = cpu_get_y (proc);", vars[cur_var]);
print (fp, col, "%s16 = cpu_get_y (cpu);", vars[cur_var]);
break;
case '*':
@ -1355,8 +1355,8 @@ gen_fetch_operands (FILE *fp, int col,
addr_set = 1;
current_insn_size += 1;
print (fp, col, "addr = (uint16) cpu_fetch8 (proc);");
print (fp, col, "%s%s = memory_read%s (proc, addr);",
print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
break;
@ -1368,25 +1368,25 @@ gen_fetch_operands (FILE *fp, int col,
if (strncmp (operands, "(x)", 3) == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_x (proc) + (uint16) cpu_fetch8 (proc);");
print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
operands += 3;
}
else if (strncmp (operands, "(y)", 3) == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_y (proc) + (uint16) cpu_fetch8 (proc);");
print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
operands += 3;
}
else if (strncmp (operands, "()", 2) == 0)
{
current_insn_size += 2;
print (fp, col, "addr = cpu_fetch16 (proc);");
print (fp, col, "addr = cpu_fetch16 (cpu);");
operands += 2;
}
else if (strncmp (operands, "[]", 2) == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_indexed_operand_addr (proc, 0);");
print (fp, col, "addr = cpu_get_indexed_operand_addr (cpu, 0);");
operands += 2;
}
else
@ -1406,8 +1406,8 @@ gen_fetch_operands (FILE *fp, int col,
{
addr_set = 1;
current_insn_size += 1;
print (fp, col, "addr = cpu_get_x (proc) + (uint16) cpu_fetch8 (proc);");
print (fp, col, "%s%s = memory_read%s (proc, addr);",
print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
}
@ -1415,8 +1415,8 @@ gen_fetch_operands (FILE *fp, int col,
{
addr_set = 1;
current_insn_size += 1;
print (fp, col, "addr = cpu_get_y (proc) + (uint16) cpu_fetch8 (proc);");
print (fp, col, "%s%s = memory_read%s (proc, addr);",
print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
}
@ -1424,22 +1424,22 @@ gen_fetch_operands (FILE *fp, int col,
{
addr_set = 1;
current_insn_size += 2;
print (fp, col, "addr = cpu_fetch16 (proc);");
print (fp, col, "%s%s = memory_read%s (proc, addr);",
print (fp, col, "addr = cpu_fetch16 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands++;
}
else if (strncmp (operands, "@)", 2) == 0)
{
current_insn_size += 2;
print (fp, col, "addr = cpu_fetch16 (proc);");
print (fp, col, "%s%s = memory_read%s (proc, addr);",
print (fp, col, "addr = cpu_fetch16 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
}
else if (strncmp (operands, "sp)", 3) == 0)
{
print (fp, col, "%s%s = cpu_%s_pop_uint%s (proc);",
print (fp, col, "%s%s = cpu_%s_pop_uint%s (cpu);",
vars[cur_var], operand_size,
cpu_type == cpu6811 ? "m68hc11" : "m68hc12",
operand_size);
@ -1462,8 +1462,8 @@ gen_fetch_operands (FILE *fp, int col,
{
addr_set = 1;
current_insn_size += 1;
print (fp, col, "addr = cpu_get_indexed_operand_addr (proc,0);");
print (fp, col, "%s%s = memory_read%s (proc, addr);",
print (fp, col, "addr = cpu_get_indexed_operand_addr (cpu,0);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 1;
}
@ -1472,7 +1472,7 @@ gen_fetch_operands (FILE *fp, int col,
else if (strncmp (operands, "]", 1) == 0)
{
current_insn_size += 1;
print (fp, col, "%s%s = cpu_get_indexed_operand%s (proc,0);",
print (fp, col, "%s%s = cpu_get_indexed_operand%s (cpu,0);",
vars[cur_var], operand_size, operand_size);
operands += 1;
}
@ -1493,7 +1493,7 @@ gen_fetch_operands (FILE *fp, int col,
if (strncmp (operands, "}", 1) == 0)
{
current_insn_size += 1;
print (fp, col, "%s%s = cpu_get_indexed_operand%s (proc, 1);",
print (fp, col, "%s%s = cpu_get_indexed_operand%s (cpu, 1);",
vars[cur_var], operand_size, operand_size);
operands += 1;
}
@ -1509,7 +1509,7 @@ gen_fetch_operands (FILE *fp, int col,
if (strncmp (operands, "p", 1) == 0)
{
print (fp, col, "%s16 = cpu_get_sp (proc);", vars[cur_var]);
print (fp, col, "%s16 = cpu_get_sp (cpu);", vars[cur_var]);
operands++;
}
else
@ -1521,7 +1521,7 @@ gen_fetch_operands (FILE *fp, int col,
case 'c':
if (strncmp (operands, "cr", 2) == 0)
{
print (fp, col, "%s8 = cpu_get_ccr (proc);", vars[cur_var]);
print (fp, col, "%s8 = cpu_get_ccr (cpu);", vars[cur_var]);
operands += 2;
}
else
@ -1536,7 +1536,7 @@ gen_fetch_operands (FILE *fp, int col,
addr_set = 1;
current_insn_size += 1;
print (fp, col, "addr = cpu_fetch_relbranch (proc);");
print (fp, col, "addr = cpu_fetch_relbranch (cpu);");
break;
case 'R':
@ -1545,7 +1545,7 @@ gen_fetch_operands (FILE *fp, int col,
addr_set = 1;
current_insn_size += 2;
print (fp, col, "addr = cpu_fetch_relbranch16 (proc);");
print (fp, col, "addr = cpu_fetch_relbranch16 (cpu);");
break;
case '#':
@ -1557,7 +1557,7 @@ gen_fetch_operands (FILE *fp, int col,
{
current_insn_size += 2;
}
print (fp, col, "%s%s = cpu_fetch%s (proc);", vars[cur_var],
print (fp, col, "%s%s = cpu_fetch%s (cpu);", vars[cur_var],
operand_size, operand_size);
break;
@ -1639,37 +1639,37 @@ gen_save_result (FILE *fp, int col,
{
case 'a':
result_size = "8";
print (fp, col, "cpu_set_a (proc, dst8);");
print (fp, col, "cpu_set_a (cpu, dst8);");
break;
case 'b':
result_size = "8";
print (fp, col, "cpu_set_b (proc, dst8);");
print (fp, col, "cpu_set_b (cpu, dst8);");
break;
case 'd':
result_size = "16";
print (fp, col, "cpu_set_d (proc, dst16);");
print (fp, col, "cpu_set_d (cpu, dst16);");
break;
case 'x':
result_size = "16";
print (fp, col, "cpu_set_x (proc, dst16);");
print (fp, col, "cpu_set_x (cpu, dst16);");
break;
case 'y':
result_size = "16";
print (fp, col, "cpu_set_y (proc, dst16);");
print (fp, col, "cpu_set_y (cpu, dst16);");
break;
case '*':
if (addr_set == 0)
{
current_insn_size += 1;
print (fp, col, "addr = (uint16) cpu_fetch8 (proc);");
print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
}
result_size = operand_size;
print (fp, col, "memory_write%s (proc, addr, dst%s);",
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
operand_size, operand_size);
break;
@ -1679,9 +1679,9 @@ gen_save_result (FILE *fp, int col,
if (addr_set == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_x (proc) + cpu_fetch8 (proc);");
print (fp, col, "addr = cpu_get_x (cpu) + cpu_fetch8 (cpu);");
}
print (fp, col, "memory_write%s (proc, addr, dst%s);",
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
operand_size, operand_size);
operands += 2;
result_size = operand_size;
@ -1691,9 +1691,9 @@ gen_save_result (FILE *fp, int col,
if (addr_set == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_y (proc) + cpu_fetch8 (proc);");
print (fp, col, "addr = cpu_get_y (cpu) + cpu_fetch8 (cpu);");
}
print (fp, col, "memory_write%s (proc, addr, dst%s);",
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
operand_size, operand_size);
operands += 2;
result_size = operand_size;
@ -1703,16 +1703,16 @@ gen_save_result (FILE *fp, int col,
if (addr_set == 0)
{
current_insn_size += 2;
print (fp, col, "addr = cpu_fetch16 (proc);");
print (fp, col, "addr = cpu_fetch16 (cpu);");
}
print (fp, col, "memory_write%s (proc, addr, dst%s);",
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
operand_size, operand_size);
operands++;
result_size = operand_size;
}
else if (strncmp (operands, "sp)", 3) == 0)
{
print (fp, col, "cpu_%s_push_uint%s (proc, dst%s);",
print (fp, col, "cpu_%s_push_uint%s (cpu, dst%s);",
cpu_type == cpu6811 ? "m68hc11" : "m68hc12",
operand_size, operand_size);
operands += 3;
@ -1730,9 +1730,9 @@ gen_save_result (FILE *fp, int col,
if (addr_set == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_indexed_operand_addr (proc,0);");
print (fp, col, "addr = cpu_get_indexed_operand_addr (cpu,0);");
}
print (fp, col, "memory_write%s (proc, addr, dst%s);",
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
operand_size, operand_size);
operands++;
result_size = operand_size;
@ -1747,8 +1747,8 @@ gen_save_result (FILE *fp, int col,
if (strncmp (operands, "}", 1) == 0)
{
current_insn_size += 1;
print (fp, col, "addr = cpu_get_indexed_operand_addr (proc, 1);");
print (fp, col, "memory_write%s (proc, addr, dst%s);",
print (fp, col, "addr = cpu_get_indexed_operand_addr (cpu, 1);");
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
operand_size, operand_size);
operands++;
result_size = operand_size;
@ -1762,7 +1762,7 @@ gen_save_result (FILE *fp, int col,
case 's':
if (strncmp (operands, "p", 1) == 0)
{
print (fp, col, "cpu_set_sp (proc, dst16);");
print (fp, col, "cpu_set_sp (cpu, dst16);");
operands++;
result_size = "16";
}
@ -1775,7 +1775,7 @@ gen_save_result (FILE *fp, int col,
case 'c':
if (strncmp (operands, "cr", 2) == 0)
{
print (fp, col, "cpu_set_ccr (proc, dst8);");
print (fp, col, "cpu_set_ccr (cpu, dst8);");
operands += 2;
result_size = "8";
}
@ -1896,8 +1896,8 @@ gen_interpreter_for_table (FILE *fp, int col,
|| table == m6812_page1_opcodes? 1 : 2;
/* Get the opcode and dispatch directly. */
print (fp, col, "op = cpu_fetch8 (proc);");
print (fp, col, "cpu_add_cycles (proc, %s[op]);", cycles_table_name);
print (fp, col, "op = cpu_fetch8 (cpu);");
print (fp, col, "cpu_add_cycles (cpu, %s[op]);", cycles_table_name);
print (fp, col, "switch (op)\n");
col += indent_level;
@ -1921,7 +1921,7 @@ gen_interpreter_for_table (FILE *fp, int col,
}
print (fp, col, "default:\n");
print (fp, col + indent_level, "cpu_special (proc, M6811_ILLEGAL);");
print (fp, col + indent_level, "cpu_special (cpu, M6811_ILLEGAL);");
print (fp, col + indent_level, "break;");
print (fp, col, "}\n");
}
@ -1988,7 +1988,7 @@ void
gen_function_entry (FILE *fp, const char *name, int locals)
{
/* Generate interpretor entry point. */
print (fp, 0, "%s (sim_cpu *proc)\n", name);
print (fp, 0, "%s (sim_cpu *cpu)\n", name);
print (fp, indent_level, "{\n");
/* Interpretor local variables. */

6
sim/m68hc11/interrupts.c
View File

@ -123,11 +123,11 @@ static const OPTION interrupt_options[] =
/* Initialize the interrupts module. */
void
interrupts_initialize (SIM_DESC sd, struct _sim_cpu *proc)
interrupts_initialize (SIM_DESC sd, sim_cpu *cpu)
{
struct interrupts *interrupts = &proc->cpu_interrupts;
struct interrupts *interrupts = &cpu->cpu_interrupts;
interrupts->cpu = proc;
interrupts->cpu = cpu;
sim_add_option_table (sd, 0, interrupt_options);
}

4
sim/m68hc11/interrupts.h
View File

@ -122,7 +122,7 @@ struct interrupt
are masked; second it checks for pending interrupts and raise one if
interrupts are enabled. */
struct interrupts {
struct _sim_cpu *cpu;
sim_cpu *cpu;
/* Mask of current pending interrupts. */
unsigned long pending_mask;
@ -159,7 +159,7 @@ struct interrupts {
struct interrupt_history interrupts_history[MAX_INT_HISTORY];
};
extern void interrupts_initialize (SIM_DESC sd, struct _sim_cpu* cpu);
extern void interrupts_initialize (SIM_DESC sd, sim_cpu *cpu);
extern void interrupts_reset (struct interrupts* interrupts);
extern void interrupts_update_pending (struct interrupts* interrupts);
extern int interrupts_get_current (struct interrupts* interrupts);

26
sim/m68hc11/m68hc11_sim.c
View File

@ -114,7 +114,7 @@ cpu_set_sp (sim_cpu *cpu, uint16 val)
}
uint16
cpu_get_reg (sim_cpu* cpu, uint8 reg)
cpu_get_reg (sim_cpu *cpu, uint8 reg)
{
switch (reg)
{
@ -136,7 +136,7 @@ cpu_get_reg (sim_cpu* cpu, uint8 reg)
}
uint16
cpu_get_src_reg (sim_cpu* cpu, uint8 reg)
cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
{
switch (reg)
{
@ -170,7 +170,7 @@ cpu_get_src_reg (sim_cpu* cpu, uint8 reg)
}
void
cpu_set_dst_reg (sim_cpu* cpu, uint8 reg, uint16 val)
cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
{
switch (reg)
{
@ -212,7 +212,7 @@ cpu_set_dst_reg (sim_cpu* cpu, uint8 reg, uint16 val)
}
void
cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val)
cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
{
switch (reg)
{
@ -240,7 +240,7 @@ cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val)
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
uint16
cpu_get_indexed_operand_addr (sim_cpu* cpu, int restricted)
cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
{
uint8 reg;
uint16 sval;
@ -345,7 +345,7 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restricted)
}
uint8
cpu_get_indexed_operand8 (sim_cpu* cpu, int restricted)
cpu_get_indexed_operand8 (sim_cpu *cpu, int restricted)
{
uint16 addr;
@ -354,7 +354,7 @@ cpu_get_indexed_operand8 (sim_cpu* cpu, int restricted)
}
uint16
cpu_get_indexed_operand16 (sim_cpu* cpu, int restricted)
cpu_get_indexed_operand16 (sim_cpu *cpu, int restricted)
{
uint16 addr;
@ -602,11 +602,11 @@ print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
}
void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val)
cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
{
cpu_set_ccr_V (proc, 0);
cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
cpu_set_ccr_V (cpu, 0);
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
}
@ -656,7 +656,7 @@ cpu_push_all (sim_cpu *cpu)
/* Simulation of the dbcc/ibcc/tbcc 68HC12 conditional branch operations. */
void
cpu_dbcc (sim_cpu* cpu)
cpu_dbcc (sim_cpu *cpu)
{
uint8 code;
uint16 addr;
@ -697,7 +697,7 @@ cpu_dbcc (sim_cpu* cpu)
}
void
cpu_exg (sim_cpu* cpu, uint8 code)
cpu_exg (sim_cpu *cpu, uint8 code)
{
uint8 r1, r2;
uint16 src1;

268
sim/m68hc11/sim-main.h
View File

@ -219,78 +219,78 @@ struct _sim_cpu {
/* Returns the cpu absolute cycle time (A virtual counter incremented
at each 68HC11 E clock). */
#define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
#define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(PROC) ((PROC)->cpu_running)
#define cpu_current_cycle(cpu) ((cpu)->cpu_absolute_cycle)
#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (signed64) (T))
#define cpu_is_running(cpu) ((cpu)->cpu_running)
/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
#define cpu_get_io_base(PROC) \
(((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
#define cpu_get_reg_base(PROC) \
(((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
#define cpu_get_io_base(cpu) \
(((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
#define cpu_get_reg_base(cpu) \
(((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
/* Returns the different CPU registers. */
#define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
#define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
#define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
#define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
#define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
#define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
#define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
#define cpu_get_ccr(cpu) ((cpu)->cpu_regs.ccr)
#define cpu_get_pc(cpu) ((cpu)->cpu_regs.pc)
#define cpu_get_d(cpu) ((cpu)->cpu_regs.d)
#define cpu_get_x(cpu) ((cpu)->cpu_regs.ix)
#define cpu_get_y(cpu) ((cpu)->cpu_regs.iy)
#define cpu_get_sp(cpu) ((cpu)->cpu_regs.sp)
#define cpu_get_a(cpu) (((cpu)->cpu_regs.d >> 8) & 0x0FF)
#define cpu_get_b(cpu) ((cpu)->cpu_regs.d & 0x0FF)
#define cpu_get_page(cpu) ((cpu)->cpu_regs.page)
/* 68HC12 specific and Motorola internal registers. */
#define cpu_get_tmp3(PROC) (0)
#define cpu_get_tmp2(PROC) (0)
#define cpu_get_tmp3(cpu) (0)
#define cpu_get_tmp2(cpu) (0)
#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
#define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
#define cpu_set_d(cpu, val) ((cpu)->cpu_regs.d = (val))
#define cpu_set_x(cpu, val) ((cpu)->cpu_regs.ix = (val))
#define cpu_set_y(cpu, val) ((cpu)->cpu_regs.iy = (val))
#define cpu_set_page(cpu, val) ((cpu)->cpu_regs.page = (val))
/* 68HC12 specific and Motorola internal registers. */
#define cpu_set_tmp3(PROC,VAL) (0)
#define cpu_set_tmp2(PROC,VAL) (void) (0)
#define cpu_set_tmp3(cpu, val) (0)
#define cpu_set_tmp2(cpu, val) (void) (0)
#if 0
/* This is a function in m68hc11_sim.c to keep track of the frame. */
#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
#define cpu_set_sp(cpu, val) ((cpu)->cpu_regs.sp = (val))
#endif
#define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
#define cpu_set_pc(cpu, val) ((cpu)->cpu_regs.pc = (val))
#define cpu_set_a(PROC,VAL) \
cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
#define cpu_set_b(PROC,VAL) \
cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
#define cpu_set_a(cpu, val) \
cpu_set_d(cpu, ((val) << 8) | cpu_get_b (cpu))
#define cpu_set_b(cpu, val) \
cpu_set_d(cpu, ((cpu_get_a (cpu)) << 8) | ((val) & 0x0FF))
#define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
#define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
#define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
#define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
#define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
#define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
#define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
#define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
#define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
#define cpu_set_ccr(cpu, val) ((cpu)->cpu_regs.ccr = (val))
#define cpu_get_ccr_H(cpu) ((cpu_get_ccr (cpu) & M6811_H_BIT) ? 1 : 0)
#define cpu_get_ccr_X(cpu) ((cpu_get_ccr (cpu) & M6811_X_BIT) ? 1 : 0)
#define cpu_get_ccr_S(cpu) ((cpu_get_ccr (cpu) & M6811_S_BIT) ? 1 : 0)
#define cpu_get_ccr_N(cpu) ((cpu_get_ccr (cpu) & M6811_N_BIT) ? 1 : 0)
#define cpu_get_ccr_V(cpu) ((cpu_get_ccr (cpu) & M6811_V_BIT) ? 1 : 0)
#define cpu_get_ccr_C(cpu) ((cpu_get_ccr (cpu) & M6811_C_BIT) ? 1 : 0)
#define cpu_get_ccr_Z(cpu) ((cpu_get_ccr (cpu) & M6811_Z_BIT) ? 1 : 0)
#define cpu_get_ccr_I(cpu) ((cpu_get_ccr (cpu) & M6811_I_BIT) ? 1 : 0)
#define cpu_set_ccr_flag(S,B,V) \
cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
#define cpu_set_ccr_flag(S, B, V) \
cpu_set_ccr (S, (cpu_get_ccr (S) & ~(B)) | ((V) ? (B) : 0))
#define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
#define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
#define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
#define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
#define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
#define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
#define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
#define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
#define cpu_set_ccr_H(cpu, val) cpu_set_ccr_flag (cpu, M6811_H_BIT, val)
#define cpu_set_ccr_X(cpu, val) cpu_set_ccr_flag (cpu, M6811_X_BIT, val)
#define cpu_set_ccr_S(cpu, val) cpu_set_ccr_flag (cpu, M6811_S_BIT, val)
#define cpu_set_ccr_N(cpu, val) cpu_set_ccr_flag (cpu, M6811_N_BIT, val)
#define cpu_set_ccr_V(cpu, val) cpu_set_ccr_flag (cpu, M6811_V_BIT, val)
#define cpu_set_ccr_C(cpu, val) cpu_set_ccr_flag (cpu, M6811_C_BIT, val)
#define cpu_set_ccr_Z(cpu, val) cpu_set_ccr_flag (cpu, M6811_Z_BIT, val)
#define cpu_set_ccr_I(cpu, val) cpu_set_ccr_flag (cpu, M6811_I_BIT, val)
#undef inline
#define inline static __inline__
extern void cpu_memory_exception (struct _sim_cpu *proc,
extern void cpu_memory_exception (sim_cpu *cpu,
SIM_SIGNAL excep,
uint16 addr,
const char *message);
@ -356,189 +356,189 @@ memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
}
}
extern void
cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
inline void
cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
{
cpu_set_ccr_V (proc, 0);
cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
cpu_set_ccr_V (cpu, 0);
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
}
inline void
cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
{
cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
}
inline void
cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
{
cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
cpu_set_ccr_V (cpu, cpu_get_ccr_N (cpu) ^ cpu_get_ccr_C (cpu));
}
inline void
cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
{
cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_Z (proc, r == 0);
cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_Z (cpu, r == 0);
cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
}
inline void
cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
{
cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_Z (proc, r == 0);
cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_Z (cpu, r == 0);
cpu_set_ccr_N (cpu, r & 0x80 ? 1 : 0);
}
inline void
cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
{
cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (proc, r == 0);
cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (cpu, r == 0);
cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
}
inline void
cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
{
cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (proc, r == 0);
cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (cpu, r == 0);
cpu_set_ccr_N (cpu, r & 0x8000 ? 1 : 0);
}
/* Push and pop instructions for 68HC11 (next-available stack mode). */
inline void
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
memory_write8 (proc, addr, val);
proc->cpu_regs.sp = addr - 1;
memory_write8 (cpu, addr, val);
cpu->cpu_regs.sp = addr - 1;
}
inline void
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
{
uint16 addr = proc->cpu_regs.sp - 1;
uint16 addr = cpu->cpu_regs.sp - 1;
memory_write16 (proc, addr, val);
proc->cpu_regs.sp = addr - 1;
memory_write16 (cpu, addr, val);
cpu->cpu_regs.sp = addr - 1;
}
inline uint8
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
uint8 val;
val = memory_read8 (proc, addr + 1);
proc->cpu_regs.sp = addr + 1;
val = memory_read8 (cpu, addr + 1);
cpu->cpu_regs.sp = addr + 1;
return val;
}
inline uint16
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
uint16 val;
val = memory_read16 (proc, addr + 1);
proc->cpu_regs.sp = addr + 2;
val = memory_read16 (cpu, addr + 1);
cpu->cpu_regs.sp = addr + 2;
return val;
}
/* Push and pop instructions for 68HC12 (last-used stack mode). */
inline void
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
addr --;
memory_write8 (proc, addr, val);
proc->cpu_regs.sp = addr;
memory_write8 (cpu, addr, val);
cpu->cpu_regs.sp = addr;
}
inline void
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
addr -= 2;
memory_write16 (proc, addr, val);
proc->cpu_regs.sp = addr;
memory_write16 (cpu, addr, val);
cpu->cpu_regs.sp = addr;
}
inline uint8
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
uint8 val;
val = memory_read8 (proc, addr);
proc->cpu_regs.sp = addr + 1;
val = memory_read8 (cpu, addr);
cpu->cpu_regs.sp = addr + 1;
return val;
}
inline uint16
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
{
uint16 addr = proc->cpu_regs.sp;
uint16 addr = cpu->cpu_regs.sp;
uint16 val;
val = memory_read16 (proc, addr);
proc->cpu_regs.sp = addr + 2;
val = memory_read16 (cpu, addr);
cpu->cpu_regs.sp = addr + 2;
return val;
}
/* Fetch a 8/16 bit value and update the PC. */
inline uint8
cpu_fetch8 (sim_cpu *proc)
cpu_fetch8 (sim_cpu *cpu)
{
uint16 addr = proc->cpu_regs.pc;
uint16 addr = cpu->cpu_regs.pc;
uint8 val;
val = memory_read8 (proc, addr);
proc->cpu_regs.pc = addr + 1;
val = memory_read8 (cpu, addr);
cpu->cpu_regs.pc = addr + 1;
return val;
}
inline uint16
cpu_fetch16 (sim_cpu *proc)
cpu_fetch16 (sim_cpu *cpu)
{
uint16 addr = proc->cpu_regs.pc;
uint16 addr = cpu->cpu_regs.pc;
uint16 val;
val = memory_read16 (proc, addr);
proc->cpu_regs.pc = addr + 2;
val = memory_read16 (cpu, addr);
cpu->cpu_regs.pc = addr + 2;
return val;
}
extern void cpu_call (sim_cpu* proc, uint16 addr);
extern void cpu_exg (sim_cpu* proc, uint8 code);
extern void cpu_dbcc (sim_cpu* proc);
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *proc, uint8 op);
extern void cpu_move16 (sim_cpu *proc, uint8 op);
extern void cpu_call (sim_cpu *cpu, uint16 addr);
extern void cpu_exg (sim_cpu *cpu, uint8 code);
extern void cpu_dbcc (sim_cpu *cpu);
extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
extern void cpu_move8 (sim_cpu *cpu, uint8 op);
extern void cpu_move16 (sim_cpu *cpu, uint8 op);
extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
extern void cpu_push_all (sim_cpu *proc);
extern void cpu_single_step (sim_cpu *proc);
extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
extern void cpu_push_all (sim_cpu *cpu);
extern void cpu_single_step (sim_cpu *cpu);
extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
extern void cpu_info (SIM_DESC sd, sim_cpu *cpu);
extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);