x86: Properly encode vmovd with 64-bit memeory

For historical reason, we allow movd/vmovd with 64-bit register and
memeory operands.  But for vmovd, we failed to handle 64-bit memeory
operand.  This has been gone unnoticed since AT&T syntax always treats
memory operand as 32-bit memory.  This patch properly encodes vmovd
with 64-bit memeory operands.  It also removes AVX512 vmovd with 64-bit
operands since GCC has

    case TYPE_SSEMOV:
      switch (get_attr_mode (insn))
        {
        case MODE_DI:
          /* Handle broken assemblers that require movd instead of movq.  */
          if (!HAVE_AS_IX86_INTERUNIT_MOVQ
              && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
            return "%vmovd\t{%1, %0|%0, %1}";
          return "%vmovq\t{%1, %0|%0, %1}";

and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't
generate AVX512 vmovd with 64-bit operand.

gas/

	PR gas/22681
	* testsuite/gas/i386/i386.exp: Run x86-64-movd and
	x86-64-movd-intel.
	* testsuite/gas/i386/x86-64-movd-intel.d: New file.
	* testsuite/gas/i386/x86-64-movd.d: Likewise.
	* testsuite/gas/i386/x86-64-movd.s: Likewise.

opcodes/

	PR gas/22681
	* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
	Remove AVX512 vmovd with 64-bit operands.
	* i386-tbl.h: Regenerated.

gas/ChangeLog

@@ -1,3 +1,12 @@
+2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/22681
+	* testsuite/gas/i386/i386.exp: Run x86-64-movd and
+	x86-64-movd-intel.
+	* testsuite/gas/i386/x86-64-movd-intel.d: New file.
+	* testsuite/gas/i386/x86-64-movd.d: Likewise.
+	* testsuite/gas/i386/x86-64-movd.s: Likewise.
+
 2018-01-08  Nick Clifton  <nickc@redhat.com>
 
 	PR 22553

gas/testsuite/gas/i386/i386.exp

@@ -900,6 +900,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-notrack"
     run_dump_test "x86-64-notrack-intel"
     run_list_test "x86-64-notrackbad" "-al"
+    run_dump_test "x86-64-movd"
+    run_dump_test "x86-64-movd-intel"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]

gas/testsuite/gas/i386/x86-64-movd-intel.d

@@ -0,0 +1,47 @@
+#source: x86-64-movd.s
+#as: -J
+#objdump: -dw -Mintel
+#name: x86-64 movd (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	66 48 0f 6e c8       	movq   xmm1,rax
+ +[a-f0-9]+:	66 0f 7e 88 80 00 00 00 	movd   DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	66 48 0f 7e c8       	movq   rax,xmm1
+ +[a-f0-9]+:	c5 f9 6e 88 80 00 00 00 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  xmm1,rax
+ +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  rax,xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	66 0f 6e c8          	movd   xmm1,eax
+ +[a-f0-9]+:	66 0f 7e 88 80 00 00 00 	movd   DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	66 0f 7e 88 80 00 00 00 	movd   DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	66 0f 7e c8          	movd   eax,xmm1
+ +[a-f0-9]+:	66 48 0f 6e 88 80 00 00 00 	movq   xmm1,QWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	66 48 0f 6e c8       	movq   xmm1,rax
+ +[a-f0-9]+:	66 48 0f 7e 88 80 00 00 00 	movq   QWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	66 48 0f 7e c8       	movq   rax,xmm1
+ +[a-f0-9]+:	c5 f9 6e 88 80 00 00 00 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	c5 f9 6e 88 80 00 00 00 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	c5 f9 6e c8          	vmovd  xmm1,eax
+ +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	c5 f9 7e c8          	vmovd  eax,xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	62 f1 7d 08 6e c8    	vmovd  xmm1,eax
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e c8    	vmovd  eax,xmm1
+ +[a-f0-9]+:	c4 e1 f9 6e 88 80 00 00 00 	vmovq  xmm1,QWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  xmm1,rax
+ +[a-f0-9]+:	c4 e1 f9 7e 88 80 00 00 00 	vmovq  QWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  rax,xmm1
+#pass

gas/testsuite/gas/i386/x86-64-movd.d

@@ -0,0 +1,46 @@
+#as: -J
+#objdump: -dw
+#name: x86-64 movd
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	66 48 0f 6e c8       	movq   %rax,%xmm1
+ +[a-f0-9]+:	66 0f 7e 88 80 00 00 00 	movd   %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	66 48 0f 7e c8       	movq   %xmm1,%rax
+ +[a-f0-9]+:	c5 f9 6e 88 80 00 00 00 	vmovd  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  %rax,%xmm1
+ +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  %xmm1,%rax
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	66 0f 6e c8          	movd   %eax,%xmm1
+ +[a-f0-9]+:	66 0f 7e 88 80 00 00 00 	movd   %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	66 0f 7e 88 80 00 00 00 	movd   %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	66 0f 7e c8          	movd   %xmm1,%eax
+ +[a-f0-9]+:	66 48 0f 6e 88 80 00 00 00 	movq   0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	66 48 0f 6e c8       	movq   %rax,%xmm1
+ +[a-f0-9]+:	66 48 0f 7e 88 80 00 00 00 	movq   %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	66 48 0f 7e c8       	movq   %xmm1,%rax
+ +[a-f0-9]+:	c5 f9 6e 88 80 00 00 00 	vmovd  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	c5 f9 6e 88 80 00 00 00 	vmovd  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	c5 f9 6e c8          	vmovd  %eax,%xmm1
+ +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	c5 f9 7e c8          	vmovd  %xmm1,%eax
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e c8    	vmovd  %eax,%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 7e c8    	vmovd  %xmm1,%eax
+ +[a-f0-9]+:	c4 e1 f9 6e 88 80 00 00 00 	vmovq  0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  %rax,%xmm1
+ +[a-f0-9]+:	c4 e1 f9 7e 88 80 00 00 00 	vmovq  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  %xmm1,%rax
+#pass

gas/testsuite/gas/i386/x86-64-movd.s

@@ -0,0 +1,41 @@
+# Check movd/vmovd with memory and register.
+
+	.text
+_start:
+	movd 128(%rax), %xmm1
+	movd %rax, %xmm1
+	movd %xmm1, 128(%rax)
+	movd %xmm1, %rax
+	vmovd 128(%rax), %xmm1
+	vmovd %rax, %xmm1
+	vmovd %xmm1, 128(%rax)
+	vmovd %xmm1, %rax
+	{evex} vmovd 128(%rax), %xmm1
+	{evex} vmovd %xmm1, 128(%rax)
+	.intel_syntax noprefix
+	movd xmm1, [rax + 128]
+	movd xmm1, dword ptr [rax + 128]
+	movd xmm1, eax
+	movd dword ptr [rax + 128], xmm1
+	movd [rax + 128], xmm1
+	movd eax, xmm1
+	movd xmm1, qword ptr [rax + 128]
+	movd xmm1, rax
+	movd qword ptr [rax + 128], xmm1
+	movd rax, xmm1
+	vmovd xmm1, dword ptr [rax + 128]
+	vmovd xmm1, [rax + 128]
+	vmovd xmm1, eax
+	vmovd dword ptr [rax + 128], xmm1
+	vmovd [rax + 128], xmm1
+	vmovd eax, xmm1
+	{evex} vmovd xmm1, dword ptr [rax + 128]
+	{evex} vmovd xmm1, [rax + 128]
+	{evex} vmovd xmm1, eax
+	{evex} vmovd dword ptr [rax + 128], xmm1
+	{evex} vmovd [rax + 128], xmm1
+	{evex} vmovd eax, xmm1
+	vmovd xmm1, qword ptr [rax + 128]
+	vmovd xmm1, rax
+	vmovd qword ptr [rax + 128], xmm1
+	vmovd rax, xmm1

opcodes/ChangeLog

@@ -1,3 +1,10 @@
+2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/22681
+	* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
+	Remove AVX512 vmovd with 64-bit operands.
+	* i386-tbl.h: Regenerated.
+
 2018-01-05  Jim Wilson  <jimw@sifive.com>
 
 	* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a

opcodes/i386-opc.tbl

@@ -2057,9 +2057,9 @@ vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_
 // support assembler for AMD64, we accept 64bit operand on vmovd so
 // that we can use one template for both SSE and AVX instructions.
 vmovd, 2, 0x666e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|BaseIndex, RegXMM }
+vmovd, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Qword|BaseIndex, RegXMM }
 vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|Reg32|BaseIndex }
-vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Qword|Reg64|BaseIndex }
+vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex=3|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { RegXMM, Reg64|Qword|BaseIndex }
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
 vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
 vmovdqa, 2, 0x666f, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
@@ -3873,9 +3873,7 @@ vmovups, 2, 0x10, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1
 vmovups, 2, 0x11, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegZMM|RegMem }
 
 vmovd, 2, 0x666E, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, RegXMM }
-vmovd, 2, 0x666E, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64|Qword|Unspecified|BaseIndex, RegXMM }
 vmovd, 2, 0x667E, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-vmovd, 2, 0x667E, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Reg64|Qword|Unspecified|BaseIndex }
 
 vmovddup, 2, 0xF212, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|VecESize=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM }
 

opcodes/i386-tbl.h

@@ -40861,8 +40861,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         1, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
@@ -40895,8 +40895,8 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         1, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -40922,23 +40922,6 @@ const insn_template i386_optab[] =
       { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
 	  0, 0, 0 } } } },
-  { "vmovd", 2, 0x666E, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        1, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 2, 0, 0, 0,
-      0, 0, 0, 0, 0 },
-    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
-	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0,
-	  0, 0, 0 } },
-      { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
-	  0, 0, 0 } } } },
   { "vmovd", 2, 0x667E, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -40956,23 +40939,6 @@ const insn_template i386_optab[] =
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
 	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0,
 	  0, 0, 0 } } } },
-  { "vmovd", 2, 0x667E, None, 1,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        1, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
-      0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 2, 0, 0, 0,
-      0, 0, 0, 0, 0 },
-    { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
-	  0, 0, 0 } },
-      { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
-	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0,
-	  0, 0, 0 } } } },
   { "vmovddup", 2, 0xf212, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,