x86: fold various AVX512VL templates into their AVX512F counterparts
This commit is contained in:
parent
c30be56ebf
commit
7091c61201
|
@ -1,3 +1,11 @@
|
||||||
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
||||||
|
|
||||||
|
* config/tc-i386.c (is_evex_encoding): Also check disp8memshift.
|
||||||
|
(optimize_encoding): Also cover templates without cpuavx512vl
|
||||||
|
allowing for zmmword and having a ymmword actual.
|
||||||
|
(check_VecOperands): Handle DISP8_SHIFT_VL.
|
||||||
|
* testsuite/gas/i386/noavx512-2.l: Adjust expectations.
|
||||||
|
|
||||||
2018-07-18 Maciej W. Rozycki <macro@mips.com>
|
2018-07-18 Maciej W. Rozycki <macro@mips.com>
|
||||||
|
|
||||||
* testsuite/gas/mips/loongson-2e.d: Correct whitespace issues.
|
* testsuite/gas/mips/loongson-2e.d: Correct whitespace issues.
|
||||||
|
|
|
@ -3466,7 +3466,7 @@ build_vex_prefix (const insn_template *t)
|
||||||
static INLINE bfd_boolean
|
static INLINE bfd_boolean
|
||||||
is_evex_encoding (const insn_template *t)
|
is_evex_encoding (const insn_template *t)
|
||||||
{
|
{
|
||||||
return t->opcode_modifier.evex
|
return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
|
||||||
|| t->opcode_modifier.broadcast || t->opcode_modifier.masking
|
|| t->opcode_modifier.broadcast || t->opcode_modifier.masking
|
||||||
|| t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
|
|| t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
|
||||||
}
|
}
|
||||||
|
@ -3889,6 +3889,8 @@ optimize_encoding (void)
|
||||||
&& is_evex_encoding (&i.tm)
|
&& is_evex_encoding (&i.tm)
|
||||||
&& (i.vec_encoding != vex_encoding_evex
|
&& (i.vec_encoding != vex_encoding_evex
|
||||||
|| i.tm.cpu_flags.bitfield.cpuavx512vl
|
|| i.tm.cpu_flags.bitfield.cpuavx512vl
|
||||||
|
|| (i.tm.operand_types[2].bitfield.zmmword
|
||||||
|
&& i.types[2].bitfield.ymmword)
|
||||||
|| cpu_arch_isa_flags.bitfield.cpuavx512vl)))
|
|| cpu_arch_isa_flags.bitfield.cpuavx512vl)))
|
||||||
&& ((i.tm.base_opcode == 0x55
|
&& ((i.tm.base_opcode == 0x55
|
||||||
|| i.tm.base_opcode == 0x6655
|
|| i.tm.base_opcode == 0x6655
|
||||||
|
@ -5210,8 +5212,47 @@ check_VecOperands (const insn_template *t)
|
||||||
{
|
{
|
||||||
if (i.broadcast)
|
if (i.broadcast)
|
||||||
i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
|
i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
|
||||||
else
|
else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
|
||||||
i.memshift = t->opcode_modifier.disp8memshift;
|
i.memshift = t->opcode_modifier.disp8memshift;
|
||||||
|
else
|
||||||
|
{
|
||||||
|
const i386_operand_type *type = NULL;
|
||||||
|
|
||||||
|
i.memshift = 0;
|
||||||
|
for (op = 0; op < i.operands; op++)
|
||||||
|
if (operand_type_check (i.types[op], anymem))
|
||||||
|
{
|
||||||
|
if (t->operand_types[op].bitfield.xmmword
|
||||||
|
+ t->operand_types[op].bitfield.ymmword
|
||||||
|
+ t->operand_types[op].bitfield.zmmword <= 1)
|
||||||
|
type = &t->operand_types[op];
|
||||||
|
else if (!i.types[op].bitfield.unspecified)
|
||||||
|
type = &i.types[op];
|
||||||
|
}
|
||||||
|
else if (i.types[op].bitfield.regsimd)
|
||||||
|
{
|
||||||
|
if (i.types[op].bitfield.zmmword)
|
||||||
|
i.memshift = 6;
|
||||||
|
else if (i.types[op].bitfield.ymmword && i.memshift < 5)
|
||||||
|
i.memshift = 5;
|
||||||
|
else if (i.types[op].bitfield.xmmword && i.memshift < 4)
|
||||||
|
i.memshift = 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (type)
|
||||||
|
{
|
||||||
|
if (type->bitfield.zmmword)
|
||||||
|
i.memshift = 6;
|
||||||
|
else if (type->bitfield.ymmword)
|
||||||
|
i.memshift = 5;
|
||||||
|
else if (type->bitfield.xmmword)
|
||||||
|
i.memshift = 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* For the check in fits_in_disp8(). */
|
||||||
|
if (i.memshift == 0)
|
||||||
|
i.memshift = -1;
|
||||||
|
}
|
||||||
|
|
||||||
for (op = 0; op < i.operands; op++)
|
for (op = 0; op < i.operands; op++)
|
||||||
if (operand_type_check (i.types[op], disp)
|
if (operand_type_check (i.types[op], disp)
|
||||||
|
|
|
@ -5,8 +5,8 @@
|
||||||
.*:30: Error: .*unsupported instruction.*
|
.*:30: Error: .*unsupported instruction.*
|
||||||
.*:32: Error: .*unsupported instruction.*
|
.*:32: Error: .*unsupported instruction.*
|
||||||
.*:33: Error: .*unsupported instruction.*
|
.*:33: Error: .*unsupported instruction.*
|
||||||
.*:36: Error: .*unsupported masking.*
|
.*:36: Error: .*unsupported instruction.*
|
||||||
.*:37: Error: .*unsupported masking.*
|
.*:37: Error: .*unsupported instruction.*
|
||||||
.*:39: Error: .*unsupported instruction.*
|
.*:39: Error: .*unsupported instruction.*
|
||||||
.*:40: Error: .*unsupported instruction.*
|
.*:40: Error: .*unsupported instruction.*
|
||||||
.*:43: Error: .*unsupported instruction.*
|
.*:43: Error: .*unsupported instruction.*
|
||||||
|
|
|
@ -1,3 +1,13 @@
|
||||||
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
||||||
|
|
||||||
|
* i386-opc.h (DISP8_SHIFT_VL): New.
|
||||||
|
* i386-opc.tbl (Disp8ShiftVL): Define.
|
||||||
|
(various): Fold AVX512VL templates into their respective
|
||||||
|
AVX512F counterparts where possible, using Disp8ShiftVL and
|
||||||
|
CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
|
||||||
|
IgnoreSize) as appropriate.
|
||||||
|
* i386-tbl.h: Re-generate.
|
||||||
|
|
||||||
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
2018-07-19 Jan Beulich <jbeulich@suse.com>
|
||||||
|
|
||||||
* Makefile.am: Change dependencies and rule for
|
* Makefile.am: Change dependencies and rule for
|
||||||
|
|
|
@ -569,7 +569,8 @@ enum
|
||||||
/* Supress All Exceptions is supported. */
|
/* Supress All Exceptions is supported. */
|
||||||
SAE,
|
SAE,
|
||||||
|
|
||||||
/* Copressed Disp8*N attribute. */
|
/* Compressed Disp8*N attribute. */
|
||||||
|
#define DISP8_SHIFT_VL 7
|
||||||
Disp8MemShift,
|
Disp8MemShift,
|
||||||
|
|
||||||
/* Default mask isn't allowed. */
|
/* Default mask isn't allowed. */
|
||||||
|
|
1278
opcodes/i386-opc.tbl
1278
opcodes/i386-opc.tbl
File diff suppressed because it is too large
Load Diff
15045
opcodes/i386-tbl.h
15045
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue