[MIPS/GAS] Split Loongson CAM Instructions from loongson3a
bfd/ * elfxx-mips.c (print_mips_ases): Add CAM extension. binutils/ * readelf.c (print_mips_ases): Add CAM extension. gas/ * NEWS: Mention Loongson Content Address Memory (CAM) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and OPTION_NO_LOONGSON_CAM. (md_longopts): Likewise. (mips_ases): Define availability for CAM. (mips_convert_ase_flags): Map ASE_LOONGSON_CAM to AFL_ASE_LOONGSON_CAM. (mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a. (md_show_usage): Add help for -mloongson-cam and -mno-loongson-cam. * doc/as.texi: Document -mloongson-cam, -mno-loongson-cam. * doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam, .set loongson-cam and .set noloongson-cam. * testsuite/gas/mips/loongson-3a-2.d: Move cam test to ... * testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a-2.s: Move cam test to ... * testsuite/gas/mips/loongson-cam.s: Here. * testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag. * testsuite/gas/mips/mips.exp: Run loongson-cam test. include/ * elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM. * opcode/mips.h (ASE_LOONGSON_CAM): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add CAM to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-cam option. (print_mips_disassembler_options): Document -M loongson-cam. * mips-opc.c (LCAM): New macro. (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM instructions.
This commit is contained in:
Chenghua Xu
parent
36eb4c5f9b
commit
716c08de28
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@ -1,3 +1,7 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elfxx-mips.c (print_mips_ases): Add CAM extension.
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2018-08-27 H.J. Lu <hongjiu.lu@intel.com>
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* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Don't mask
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@ -15677,6 +15677,8 @@ print_mips_ases (FILE *file, unsigned int mask)
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fputs ("\n\tGINV ASE", file);
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if (mask & AFL_ASE_LOONGSON_MMI)
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fputs ("\n\tLoongson MMI ASE", file);
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if (mask & AFL_ASE_LOONGSON_CAM)
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fputs ("\n\tLoongson CAM ASE", file);
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if (mask == 0)
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fprintf (file, "\n\t%s", _("None"));
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else if ((mask & ~AFL_ASE_MASK) != 0)
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@ -1,3 +1,7 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* readelf.c (print_mips_ases): Add CAM extension.
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2018-08-27 H.J. Lu <hongjiu.lu@intel.com>
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* readelf.c (decode_x86_isa): Print <None> if bitmask only
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@ -15651,6 +15651,8 @@ print_mips_ases (unsigned int mask)
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fputs ("\n\tGINV ASE", stdout);
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if (mask & AFL_ASE_LOONGSON_MMI)
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fputs ("\n\tLoongson MMI ASE", stdout);
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if (mask & AFL_ASE_LOONGSON_CAM)
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fputs ("\n\tLoongson CAM ASE", stdout);
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if (mask == 0)
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fprintf (stdout, "\n\t%s", _("None"));
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else if ((mask & ~AFL_ASE_MASK) != 0)
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@ -1,3 +1,27 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* NEWS: Mention Loongson Content Address Memory (CAM)
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support.
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* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
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OPTION_NO_LOONGSON_CAM.
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(md_longopts): Likewise.
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(mips_ases): Define availability for CAM.
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(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
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AFL_ASE_LOONGSON_CAM.
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(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
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(md_show_usage): Add help for -mloongson-cam and
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-mno-loongson-cam.
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* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
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* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
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.set loongson-cam and .set noloongson-cam.
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* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
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* testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE
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flag verification.
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* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
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* testsuite/gas/mips/loongson-cam.s: Here.
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* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
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* testsuite/gas/mips/mips.exp: Run loongson-cam test.
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2018-08-27 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/i386.exp: Run property-1 and
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2
gas/NEWS
2
gas/NEWS
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@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for the MIPS Loongson Content Address Memory (CAM) ASE.
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* Add support for the C-SKY processor series.
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* Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI)
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@ -1531,6 +1531,8 @@ enum options
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OPTION_NO_GINV,
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OPTION_LOONGSON_MMI,
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OPTION_NO_LOONGSON_MMI,
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OPTION_LOONGSON_CAM,
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OPTION_NO_LOONGSON_CAM,
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OPTION_END_OF_ENUM
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};
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@ -1593,6 +1595,8 @@ struct option md_longopts[] =
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{"mno-ginv", no_argument, NULL, OPTION_NO_GINV},
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{"mloongson-mmi", no_argument, NULL, OPTION_LOONGSON_MMI},
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{"mno-loongson-mmi", no_argument, NULL, OPTION_NO_LOONGSON_MMI},
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{"mloongson-cam", no_argument, NULL, OPTION_LOONGSON_CAM},
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{"mno-loongson-cam", no_argument, NULL, OPTION_NO_LOONGSON_CAM},
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/* Old-style architecture options. Don't add more of these. */
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{"m4650", no_argument, NULL, OPTION_M4650},
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@ -1795,6 +1799,11 @@ static const struct mips_ase mips_ases[] = {
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OPTION_LOONGSON_MMI, OPTION_NO_LOONGSON_MMI,
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0, 0, -1, -1,
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-1 },
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{ "loongson-cam", ASE_LOONGSON_CAM, 0,
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OPTION_LOONGSON_CAM, OPTION_NO_LOONGSON_CAM,
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0, 0, -1, -1,
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-1 },
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};
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/* The set of ASEs that require -mfp64. */
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@ -19028,6 +19037,8 @@ mips_convert_ase_flags (int ase)
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ext_ases |= AFL_ASE_GINV;
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if (ase & ASE_LOONGSON_MMI)
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ext_ases |= AFL_ASE_LOONGSON_MMI;
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if (ase & ASE_LOONGSON_CAM)
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ext_ases |= AFL_ASE_LOONGSON_CAM;
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return ext_ases;
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}
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@ -19773,9 +19784,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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/* Broadcom SB-1A CPU core */
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{ "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
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{ "loongson3a", 0, ASE_LOONGSON_MMI, ISA_MIPS64R2, CPU_LOONGSON_3A },
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/* MIPS 64 Release 2 */
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/* Loongson CPU core */
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{ "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM, ISA_MIPS64R2,
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CPU_LOONGSON_3A },
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/* Cavium Networks Octeon CPU core */
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{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
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@ -20051,6 +20063,9 @@ MIPS options:\n\
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-mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
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-mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
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fprintf (stream, _("\
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-mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
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-mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
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fprintf (stream, _("\
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-minsn32 only generate 32-bit microMIPS instructions\n\
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-mno-insn32 generate all microMIPS instructions\n"));
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fprintf (stream, _("\
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@ -445,6 +445,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mcrc}] [@b{-mno-crc}]
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[@b{-mginv}] [@b{-mno-ginv}]
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[@b{-mloongson-mmi}] [@b{-mno-loongson-mmi}]
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[@b{-mloongson-cam}] [@b{-mno-loongson-cam}]
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[@b{-minsn32}] [@b{-mno-insn32}]
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[@b{-mfix7000}] [@b{-mno-fix7000}]
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[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
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@ -1573,6 +1574,12 @@ Application Specific Extension. This tells the assembler to accept MMI
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instructions.
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@samp{-mno-loongson-mmi} turns off this option.
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@item -mloongson-cam
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@itemx -mno-loongson-cam
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Generate code for the Loongson Content Address Memory (CAM) instructions.
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This tells the assembler to accept Loongson CAM instructions.
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@samp{-mno-loongson-cam} turns off this option.
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@item -minsn32
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@itemx -mno-insn32
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Only use 32-bit instruction encodings when generating code for the
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@ -253,6 +253,13 @@ Application Specific Extension. This tells the assembler to accept MMI
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instructions.
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@samp{-mno-loongson-mmi} turns off this option.
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@item -mloongson-cam
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@itemx -mno-loongson-cam
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Generate code for the Loongson Content Address Memory (CAM)
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Application Specific Extension. This tells the assembler to accept CAM
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instructions.
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@samp{-mno-loongson-cam} turns off this option.
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@item -minsn32
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@itemx -mno-insn32
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Only use 32-bit instruction encodings when generating code for the
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@ -1152,6 +1159,14 @@ instructions from the MMI Extension from that point on in the assembly.
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The @code{.set noloongson-mmi} directive prevents MMI instructions from
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being accepted.
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@cindex Loongson Content Address Memory (CAM) generation override
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@kindex @code{.set loongson-cam}
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@kindex @code{.set noloongson-cam}
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The directive @code{.set loongson-cam} makes the assembler accept
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instructions from the Loongson CAM from that point on in the assembly.
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The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
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from being accepted.
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Traditional MIPS assemblers do not support these directives.
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@node MIPS Floating-Point
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@ -7,10 +7,6 @@
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Disassembly of section .text:
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[0-9a-f]+ <.text>:
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.*: 70601075 campi \$2,\$3
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.*: 70a02035 campv \$4,\$5
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.*: 70e830b5 camwi \$6,\$7,\$8
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.*: 714048f5 ramri \$9,\$10
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.*: 716c0026 gsle \$11,\$12
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.*: 71ae0027 gsgt \$13,\$14
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.*: c8622010 gslble \$2,\$3,\$4
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@ -1,11 +1,6 @@
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.text
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.set noreorder
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campi $2,$3
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campv $4,$5
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camwi $6,$7,$8
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ramri $9,$10
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gsle $11,$12
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gsgt $13,$14
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@ -15,6 +15,7 @@ FP ABI: .*
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ISA Extension: Loongson 3A
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ASEs:
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Loongson MMI ASE
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Loongson CAM ASE
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FLAGS 1: .*
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FLAGS 2: .*
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@ -0,0 +1,27 @@
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#as: -mloongson-cam -mabi=64
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#objdump: -M reg-names=numeric -M loongson-cam -dp
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#name: Loongson CAM tests
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.*: file format .*
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private flags = .*
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MIPS ABI Flags Version: 0
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ISA: .*
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GPR size: .*
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CPR1 size: .*
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CPR2 size: .*
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FP ABI: .*
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ISA Extension: None
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ASEs:
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Loongson CAM ASE
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FLAGS 1: .*
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FLAGS 2: .*
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Disassembly of section .text:
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[0-9a-f]+ <.text>:
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.*: 70601075 campi \$2,\$3
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.*: 70a02035 campv \$4,\$5
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.*: 70e830b5 camwi \$6,\$7,\$8
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.*: 714048f5 ramri \$9,\$10
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@ -0,0 +1,7 @@
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.text
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.set noreorder
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campi $2,$3
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campv $4,$5
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camwi $6,$7,$8
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ramri $9,$10
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@ -1394,6 +1394,8 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "loongson-2f-mmi"
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run_dump_test "loongson-3a-mmi"
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run_dump_test "loongson-cam"
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if { $has_newabi } {
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run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
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}
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@ -1,3 +1,9 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
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(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
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* opcode/mips.h (ASE_LOONGSON_CAM): New macro.
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2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
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* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
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@ -1239,7 +1239,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
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#define AFL_ASE_RESERVED1 0x00010000 /* Reserved by MIPS Tech for WIP. */
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#define AFL_ASE_GINV 0x00020000 /* GINV ASE. */
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#define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE. */
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#define AFL_ASE_MASK 0x0006ffff /* All ASEs. */
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#define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE. */
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#define AFL_ASE_MASK 0x000effff /* All ASEs. */
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/* Values for the isa_ext word of an ABI flags structure. */
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@ -1304,6 +1304,8 @@ static const unsigned int mips_isa_table[] = {
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#define ASE_GINV 0x00100000
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/* Loongson MultiMedia extensions Instructions (MMI). */
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#define ASE_LOONGSON_MMI 0x00200000
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/* Loongson Content Address Memory (CAM). */
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#define ASE_LOONGSON_CAM 0x00400000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -1,3 +1,13 @@
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
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descriptors.
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(parse_mips_ase_option): Handle -M loongson-cam option.
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(print_mips_disassembler_options): Document -M loongson-cam.
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* mips-opc.c (LCAM): New macro.
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(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
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instructions.
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2018-08-21 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (operand_value_powerpc): Init "invalid".
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@ -630,8 +630,9 @@ const struct mips_arch_choice mips_arch_choices[] =
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NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
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{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
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ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
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NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric },
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ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM,
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mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
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mips_hwr_names_numeric },
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{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
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ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
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@ -941,6 +942,12 @@ parse_mips_ase_option (const char *option)
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return TRUE;
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}
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if (CONST_STRNEQ (option, "loongson-cam"))
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{
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mips_ase |= ASE_LOONGSON_CAM;
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return TRUE;
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}
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return FALSE;
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}
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@ -2592,6 +2599,10 @@ static struct
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N_("Recognize the Loongson MultiMedia extensions "
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"Instructions (MMI) ASE instructions.\n"),
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MIPS_OPTION_ARG_NONE },
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{ "loongson-cam",
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N_("Recognize the Loongson Content Address Memory (CAM) "
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" instructions.\n"),
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MIPS_OPTION_ARG_NONE },
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{ "gpr-names=", N_("Print GPR names according to specified ABI.\n\
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Default: based on binary being disassembled.\n"),
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MIPS_OPTION_ARG_ABI },
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@ -415,6 +415,9 @@ decode_mips_operand (const char *p)
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/* Loongson MultiMedia extensions Instructions (MMI) support. */
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#define LMMI ASE_LOONGSON_MMI
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||||
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||||
/* Loongson Content Address Memory (CAM) support. */
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||||
#define LCAM ASE_LOONGSON_CAM
|
||||
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||||
/* The order of overloaded instructions matters. Label arguments and
|
||||
register arguments look the same. Instructions that can have either
|
||||
for arguments must apear in the correct order in this table for the
|
||||
|
|
@ -459,10 +462,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
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|||
/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2
|
||||
instructions. Put them here so that disassembler will find them first.
|
||||
The assemblers uses a hash table based on the instruction name anyhow. */
|
||||
{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
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||||
{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
|
||||
{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 },
|
||||
{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 },
|
||||
{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
|
||||
{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
|
||||
{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 },
|
||||
{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
|
||||
{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 },
|
||||
{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 },
|
||||
{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue