* ppc-opc.c (powerpc_operands): Delete duplicate entries.
(BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete. (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete. (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
This commit is contained in:
Alan Modra
parent
bd7803a985
commit
717bbdf181
@ -1,3 +1,10 @@
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2007-04-21 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (powerpc_operands): Delete duplicate entries.
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(BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete.
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(VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete.
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(powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
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2007-04-20 Nathan Sidwell <nathan@codesourcery.com>
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* m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
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@ -76,7 +76,7 @@ static long extract_tbr (unsigned long, int, int *);
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/* The operands table.
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The fields are bits, shift, insert, extract, flags.
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The fields are bitm, shift, insert, extract, flags.
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We used to put parens around the various additions, like the one
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for BA just below. However, that caused trouble with feeble
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@ -94,7 +94,9 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BA field in an XL form instruction. */
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#define BA UNUSED + 1
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#define BA_MASK (0x1f << 16)
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/* The BI field in a B form or XL form instruction. */
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#define BI BA
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#define BI_MASK (0x1f << 16)
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{ 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
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/* The BA field in an XL form instruction when it must be the same
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@ -148,6 +150,8 @@ const struct powerpc_operand powerpc_operands[] =
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/* The BF field in an X or XL form instruction. */
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#define BF BDPA + 1
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/* The CRFD field in an X form instruction. */
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#define CRFD BF
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{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
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/* An optional BF field. This is used for comparison instructions,
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@ -159,14 +163,9 @@ const struct powerpc_operand powerpc_operands[] =
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#define BFA OBF + 1
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{ 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
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/* The BI field in a B form or XL form instruction. */
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#define BI BFA + 1
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#define BI_MASK (0x1f << 16)
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{ 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
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/* The BO field in a B form instruction. Certain values are
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illegal. */
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#define BO BI + 1
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#define BO BFA + 1
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#define BO_MASK (0x1f << 21)
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{ 0x1f, 21, insert_bo, extract_bo, 0 },
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@ -191,18 +190,19 @@ const struct powerpc_operand powerpc_operands[] =
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/* The CRB field in an X form instruction. */
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#define CRB CR + 1
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/* The MB field in an M form instruction. */
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#define MB CRB
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#define MB_MASK (0x1f << 6)
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{ 0x1f, 6, NULL, NULL, 0 },
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/* The CRFD field in an X form instruction. */
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#define CRFD CRB + 1
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{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
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/* The CRFS field in an X form instruction. */
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#define CRFS CRFD + 1
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#define CRFS CRB + 1
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{ 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
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/* The CT field in an X form instruction. */
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#define CT CRFS + 1
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/* The MO field in an mbar instruction. */
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#define MO CT
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The D field in a D form instruction. This is a displacement off
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@ -239,6 +239,8 @@ const struct powerpc_operand powerpc_operands[] =
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/* The FL1 field in a POWER SC form instruction. */
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#define FL1 E + 1
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/* The U field in an X form instruction. */
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#define U FL1
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{ 0xf, 12, NULL, NULL, 0 },
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/* The FL2 field in a POWER SC form instruction. */
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@ -272,7 +274,6 @@ const struct powerpc_operand powerpc_operands[] =
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/* The FXM field in an XFX instruction. */
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#define FXM FRS + 1
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#define FXM_MASK (0xff << 12)
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{ 0xff, 12, insert_fxm, extract_fxm, 0 },
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/* Power4 version for mfcr. */
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@ -305,13 +306,8 @@ const struct powerpc_operand powerpc_operands[] =
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#define LS LIA + 1
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{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The MB field in an M form instruction. */
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#define MB LS + 1
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#define MB_MASK (0x1f << 6)
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{ 0x1f, 6, NULL, NULL, 0 },
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/* The ME field in an M form instruction. */
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#define ME MB + 1
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#define ME LS + 1
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#define ME_MASK (0x1f << 1)
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{ 0x1f, 1, NULL, NULL, 0 },
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@ -330,13 +326,9 @@ const struct powerpc_operand powerpc_operands[] =
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#define MB6_MASK (0x3f << 5)
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{ 0x3f, 5, insert_mb6, extract_mb6, 0 },
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/* The MO field in an mbar instruction. */
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#define MO MB6 + 1
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The NB field in an X form instruction. The value 32 is stored as
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0. */
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#define NB MO + 1
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#define NB MB6 + 1
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{ 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
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/* The NSI field in a D form instruction. This is the same as the
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@ -399,24 +391,22 @@ const struct powerpc_operand powerpc_operands[] =
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#define RT_MASK (0x1f << 21)
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
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/* The RS field of the DS form stq instruction, which has special
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value restrictions. */
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/* The RS and RT fields of the DS form stq instruction, which have
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special value restrictions. */
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#define RSQ RS + 1
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{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
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/* The RT field of the DQ form lq instruction, which has special
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value restrictions. */
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#define RTQ RSQ + 1
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#define RTQ RSQ
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{ 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
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/* The RS field of the tlbwe instruction, which is optional. */
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#define RSO RTQ + 1
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#define RSO RSQ + 1
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#define RTO RSO
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
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/* The SH field in an X or M form instruction. */
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#define SH RSO + 1
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#define SH_MASK (0x1f << 11)
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/* The other UIMM field in a EVX form instruction. */
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#define EVUIMM SH
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{ 0x1f, 11, NULL, NULL, 0 },
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/* The SH field in an MD form instruction. This is split. */
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@ -459,7 +449,6 @@ const struct powerpc_operand powerpc_operands[] =
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/* The STRM field in an X AltiVec form instruction. */
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#define STRM SR + 1
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#define STRM_MASK (0x3 << 21)
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{ 0x3, 21, NULL, NULL, 0 },
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/* The SV field in a POWER SC form instruction. */
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@ -476,33 +465,25 @@ const struct powerpc_operand powerpc_operands[] =
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#define TO_MASK (0x1f << 21)
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{ 0x1f, 21, NULL, NULL, 0 },
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/* The U field in an X form instruction. */
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#define U TO + 1
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{ 0xf, 12, NULL, NULL, 0 },
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/* The UI field in a D form instruction. */
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#define UI U + 1
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#define UI TO + 1
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{ 0xffff, 0, NULL, NULL, 0 },
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/* The VA field in a VA, VX or VXR form instruction. */
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#define VA UI + 1
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#define VA_MASK (0x1f << 16)
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{ 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
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/* The VB field in a VA, VX or VXR form instruction. */
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#define VB VA + 1
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#define VB_MASK (0x1f << 11)
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{ 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
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/* The VC field in a VA form instruction. */
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#define VC VB + 1
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#define VC_MASK (0x1f << 6)
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{ 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
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/* The VD or VS field in a VA, VX, VXR or X form instruction. */
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#define VD VC + 1
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#define VS VD
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#define VD_MASK (0x1f << 21)
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{ 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
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/* The SIMM field in a VX form instruction. */
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@ -518,12 +499,8 @@ const struct powerpc_operand powerpc_operands[] =
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#define SHB UIMM + 1
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{ 0xf, 6, NULL, NULL, 0 },
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/* The other UIMM field in a EVX form instruction. */
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#define EVUIMM SHB + 1
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{ 0x1f, 11, NULL, NULL, 0 },
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/* The other UIMM field in a half word EVX form instruction. */
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#define EVUIMM_2 EVUIMM + 1
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#define EVUIMM_2 SHB + 1
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{ 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
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/* The other UIMM field in a word EVX form instruction. */
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@ -536,12 +513,10 @@ const struct powerpc_operand powerpc_operands[] =
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/* The WS field. */
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#define WS EVUIMM_8 + 1
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#define WS_MASK (0x7 << 11)
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{ 0x7, 11, NULL, NULL, 0 },
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/* The L field in an mtmsrd or A form instruction. */
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#define MTMSRD_L WS + 1
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#define A_L MTMSRD_L
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#define A_L WS + 1
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{ 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
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#define RMC A_L + 1
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@ -563,12 +538,8 @@ const struct powerpc_operand powerpc_operands[] =
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#define DGM DCM
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{ 0x3f, 10, NULL, NULL, 0 },
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/* The L field in an X form with the RT field fixed instruction. */
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#define XRT_L SH16 + 1
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{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The EH field in larx instruction. */
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#define EH XRT_L + 1
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#define EH SH16 + 1
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{ 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
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};
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@ -3236,7 +3207,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
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{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
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{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
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{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
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{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
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@ -3325,7 +3296,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
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{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
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{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
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{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
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{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
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