[AArch64][SVE 12/32] Remove boolean parameters from parse_address_main
In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main. I think we
can just get rid of them and leave the callers to check the addressing
modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).
The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks. This again creates a corner case where:
.equ x2, 1
ldr w0, [x1], x2
was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.
Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.
ADDR_SIMM9_2 appers to be unused. I'll send a separate patch
to remove it.
This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.
gas/
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters. Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
This commit is contained in:
Richard Sandiford
parent
e1b988bba6
commit
73866052f2
@ -1,3 +1,19 @@
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (parse_address_main): Remove reloc and
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accept_reg_post_index parameters. Parse relocations and register
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post indexes unconditionally.
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(parse_address): Remove accept_reg_post_index parameter.
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Update call to parse_address_main.
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(parse_address_reloc): Delete.
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(parse_operands): Call parse_address instead of parse_address_main.
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Update existing callers of parse_address and make them check
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inst.reloc.type where appropriate.
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* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
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in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
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Also test for invalid uses of post-index register addressing.
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* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
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@ -3173,8 +3173,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
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supported by the instruction, and to set inst.reloc.type. */
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static bfd_boolean
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parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
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int accept_reg_post_index)
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parse_address_main (char **str, aarch64_opnd_info *operand)
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{
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char *p = *str;
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const reg_entry *reg;
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@ -3190,7 +3189,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
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/* #:<reloc_op>:<symbol> */
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skip_past_char (&p, '#');
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if (reloc && skip_past_char (&p, ':'))
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if (skip_past_char (&p, ':'))
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{
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bfd_reloc_code_real_type ty;
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struct reloc_table_entry *entry;
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@ -3315,7 +3314,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
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{
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/* [Xn,#:<reloc_op>:<symbol> */
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skip_past_char (&p, '#');
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if (reloc && skip_past_char (&p, ':'))
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if (skip_past_char (&p, ':'))
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{
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struct reloc_table_entry *entry;
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@ -3388,8 +3387,8 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
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return FALSE;
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}
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if (accept_reg_post_index
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&& (reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier)))
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reg = aarch64_reg_parse_32_64 (&p, &offset_qualifier);
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if (reg)
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{
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/* [Xn],Xm */
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if (!aarch64_check_reg_type (reg, REG_TYPE_R_64))
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@ -3428,19 +3427,12 @@ parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
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return TRUE;
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}
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/* Return TRUE on success; otherwise return FALSE. */
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/* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
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on success. */
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static bfd_boolean
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parse_address (char **str, aarch64_opnd_info *operand,
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int accept_reg_post_index)
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parse_address (char **str, aarch64_opnd_info *operand)
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{
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return parse_address_main (str, operand, 0, accept_reg_post_index);
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}
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/* Return TRUE on success; otherwise return FALSE. */
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static bfd_boolean
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parse_address_reloc (char **str, aarch64_opnd_info *operand)
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{
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return parse_address_main (str, operand, 1, 0);
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return parse_address_main (str, operand);
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}
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/* Parse an operand for a MOVZ, MOVN or MOVK instruction.
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@ -5419,7 +5411,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_ADDR_PCREL19:
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case AARCH64_OPND_ADDR_PCREL21:
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case AARCH64_OPND_ADDR_PCREL26:
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po_misc_or_fail (parse_address_reloc (&str, info));
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po_misc_or_fail (parse_address (&str, info));
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if (!info->addr.pcrel)
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{
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set_syntax_error (_("invalid pc-relative address"));
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@ -5490,7 +5482,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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char *start = str;
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/* First use the normal address-parsing routines, to get
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the usual syntax errors. */
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po_misc_or_fail (parse_address (&str, info, 0));
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| !info->addr.preind || info->addr.postind
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|| info->addr.writeback)
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@ -5521,7 +5513,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_ADDR_REGOFF:
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/* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
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po_misc_or_fail (parse_address (&str, info, 0));
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || !info->addr.offset.is_reg
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|| !info->addr.preind || info->addr.postind
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|| info->addr.writeback)
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@ -5540,13 +5532,18 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_ADDR_SIMM7:
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po_misc_or_fail (parse_address (&str, info, 0));
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| (!info->addr.preind && !info->addr.postind))
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{
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set_syntax_error (_("invalid addressing mode"));
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goto failure;
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}
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if (inst.reloc.type != BFD_RELOC_UNUSED)
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{
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set_syntax_error (_("relocation not allowed"));
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goto failure;
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}
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assign_imm_if_const_or_fixup_later (&inst.reloc, info,
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/* addr_off_p */ 1,
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/* need_libopcodes_p */ 1,
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@ -5555,7 +5552,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_ADDR_SIMM9:
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case AARCH64_OPND_ADDR_SIMM9_2:
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po_misc_or_fail (parse_address_reloc (&str, info));
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| (!info->addr.preind && !info->addr.postind)
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|| (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
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@ -5576,7 +5573,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_ADDR_UIMM12:
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po_misc_or_fail (parse_address_reloc (&str, info));
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| !info->addr.preind || info->addr.writeback)
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{
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@ -5596,7 +5593,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SIMD_ADDR_POST:
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/* [<Xn|SP>], <Xm|#<amount>> */
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po_misc_or_fail (parse_address (&str, info, 1));
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po_misc_or_fail (parse_address (&str, info));
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if (!info->addr.postind || !info->addr.writeback)
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{
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set_syntax_error (_("invalid addressing mode"));
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@ -150,3 +150,11 @@
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[^:]*:264: Error: invalid floating-point constant at operand 2 -- `fmov s0,-2'
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[^:]*:266: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr'
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[^:]*:267: Error: integer or zero register expected at operand 2 -- `str x1,\[x2,sp\]'
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[^:]*:270: Error: relocation not allowed at operand 3 -- `ldnp x1,x2,\[x3,#:lo12:foo\]'
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[^:]*:271: Error: invalid addressing mode at operand 2 -- `ld1 {v0\.4s},\[x3,#:lo12:foo\]'
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[^:]*:272: Error: the optional immediate offset can only be 0 at operand 2 -- `stuminl x0,\[x3,#:lo12:foo\]'
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[^:]*:273: Error: relocation not allowed at operand 2 -- `prfum pldl1keep,\[x3,#:lo12:foo\]'
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[^:]*:275: Error: invalid addressing mode at operand 2 -- `ldr x0,\[x3\],x4'
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[^:]*:276: Error: invalid addressing mode at operand 3 -- `ldnp x1,x2,\[x3\],x4'
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[^:]*:278: Error: invalid addressing mode at operand 2 -- `stuminl x0,\[x3\],x4'
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[^:]*:279: Error: invalid addressing mode at operand 2 -- `prfum pldl1keep,\[x3\],x4'
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@ -265,3 +265,15 @@
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st2 {v0.4s, v1.4s}, [sp], xzr
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str x1, [x2, sp]
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ldr x0, [x1, #:lo12:foo] // OK
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ldnp x1, x2, [x3, #:lo12:foo]
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ld1 {v0.4s}, [x3, #:lo12:foo]
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stuminl x0, [x3, #:lo12:foo]
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prfum pldl1keep, [x3, #:lo12:foo]
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ldr x0, [x3], x4
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ldnp x1, x2, [x3], x4
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ld1 {v0.4s}, [x3], x4 // OK
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stuminl x0, [x3], x4
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prfum pldl1keep, [x3], x4
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