* mn10300_sim.h (PSW_*): Define for CC status tracking.
(REG_D0, REG_A0, REG_SP): Define. * simops.c: Implement "add", "addc" and a few other random instructions. Starting to simulate instructions for the mn10300. Executes some of the crt0 code now!
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@ -1,4 +1,9 @@
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Tue Nov 26 13:36:01 1996 Jeffrey A Law (law@cygnus.com)
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Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300_sim.h (PSW_*): Define for CC status tracking.
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(REG_D0, REG_A0, REG_SP): Define.
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* simops.c: Implement "add", "addc" and a few other random
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instructions.
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* gencode.c, interp.c: Snapshot current simulator code.
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@ -68,10 +68,19 @@ struct _state
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extern uint32 OP[4];
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extern struct simops Simops[];
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extern unsigned long insn, extension;
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#define PC (State.pc)
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#define PSW (State.sregs[0])
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#define PSW_V 0x1
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#define PSW_C 0x2
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#define PSW_N 0x4
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#define PSW_Z 0x8
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#define REG_D0 0
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#define REG_A0 4
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#define REG_SP 8
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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@ -97,9 +97,10 @@ void OP_3C ()
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{
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}
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/* mov */
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/* mov am, sp*/
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void OP_F2F0 ()
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{
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State.regs[REG_SP] = State.regs[REG_A0 + (insn & 0x3)];
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}
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/* mov */
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@ -347,9 +348,13 @@ void OP_240000 ()
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{
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}
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/* mov */
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/* mov imm32, an*/
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void OP_FCDC0000 ()
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{
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unsigned long value;
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value = (insn & 0xffff) << 16 | extension;
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
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}
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/* movbu */
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@ -402,9 +407,11 @@ void OP_FCA80000 ()
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{
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}
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/* movbu */
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/* movbu dm,(an) */
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void OP_F050 ()
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{
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store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
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State.regs[REG_D0 + (insn & 0x3)]);
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}
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/* movbu */
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@ -587,79 +594,321 @@ void OP_CF00 ()
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{
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}
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/* clr */
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/* clr dn */
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void OP_0 ()
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{
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State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
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PSW |= PSW_Z;
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PSW &= ~(PSW_V | PSW_C | PSW_N);
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}
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/* add */
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/* add dm,dn*/
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void OP_E0 ()
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{
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int z, c, n, v;
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unsigned long reg1, reg2, value;
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reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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reg2 = State.regs[REG_D0 + (insn & 0x3)];
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value = reg1 + reg2;
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State.regs[REG_D0 + (insn & 0x3)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add dm, an */
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void OP_F160 ()
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{
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int z, c, n, v;
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unsigned long reg1, reg2, value;
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reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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reg2 = State.regs[REG_A0 + (insn & 0x3)];
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value = reg1 + reg2;
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State.regs[REG_A0 + (insn & 0x3)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add am, dn*/
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void OP_F150 ()
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{
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int z, c, n, v;
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unsigned long reg1, reg2, value;
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reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
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reg2 = State.regs[REG_D0 + (insn & 0x3)];
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value = reg1 + reg2;
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State.regs[REG_D0 + (insn & 0x3)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add am,an */
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void OP_F170 ()
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{
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int z, c, n, v;
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unsigned long reg1, reg2, value;
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reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
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reg2 = State.regs[REG_A0 + (insn & 0x3)];
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value = reg1 + reg2;
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State.regs[REG_A0 + (insn & 0x3)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm8, dn */
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void OP_2800 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
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imm = SEXT8 (insn & 0xff);
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value = reg1 + imm;
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State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm16, dn */
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void OP_FAC00000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
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imm = SEXT16 (insn & 0xffff);
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value = reg1 + imm;
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State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm32,dn */
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void OP_FCC00000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 + imm;
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State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm8, an */
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void OP_2000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
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imm = insn & 0xff;
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value = reg1 + imm;
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State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm16, an */
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void OP_FAD00000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
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imm = 0xffff;
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value = reg1 + imm;
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State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm32, an */
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void OP_FCD00000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 + imm;
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State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm8, sp*/
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void OP_F8FE00 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_SP];
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imm = SEXT8 (insn & 0xff);
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value = reg1 + imm;
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State.regs[REG_SP] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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/* add imm16,sp */
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void OP_FAFE0000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_SP];
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imm = SEXT16 (insn & 0xffff);
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value = reg1 + imm;
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State.regs[REG_SP] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* add */
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void OP_FCFE0000 ()
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{
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int z, c, n, v;
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unsigned long reg1, imm, value;
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reg1 = State.regs[REG_SP];
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 + imm;
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State.regs[REG_SP] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((imm & 0x8000000) != (reg1 & 0x80000000)
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&& (imm & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* addc */
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void OP_F140 ()
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{
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int z, c, n, v;
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unsigned long reg1, reg2, value;
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reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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reg2 = State.regs[REG_D0 + (insn & 0x3)];
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value = reg1 + reg2 + ((PSW & PSW_C) != 0);
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State.regs[REG_D0 + (insn & 0x3)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x8000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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/* sub */
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@ -717,19 +966,22 @@ void OP_F270 ()
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{
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}
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/* inc */
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/* inc dn */
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void OP_40 ()
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{
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State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
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}
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/* inc */
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/* inc an */
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void OP_41 ()
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{
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State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
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}
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/* inc4 */
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void OP_50 ()
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{
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State.regs[REG_A0 + (insn & 0x3)] += 4;
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}
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/* cmp */
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@ -757,9 +1009,25 @@ void OP_B000 ()
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{
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}
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/* cmp */
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/* cmp am,an */
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void OP_B0 ()
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{
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int z, c, n, v;
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unsigned long reg1, reg2, value;
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reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
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reg2 = State.regs[REG_A0 + (insn & 0x3)];
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value = reg1 - reg2;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x8000000) != (value & 0x80000000));
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|
||||
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
||||
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
||||
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
||||
}
|
||||
|
||||
/* cmp */
|
||||
@ -955,11 +1223,19 @@ void OP_F280 ()
|
||||
/* beq */
|
||||
void OP_C800 ()
|
||||
{
|
||||
/* The dispatching code will add 2 after we return, so
|
||||
we subtract two here to make things right. */
|
||||
if (PSW & PSW_Z)
|
||||
State.pc += SEXT8 (insn & 0xff) - 2;
|
||||
}
|
||||
|
||||
/* bne */
|
||||
void OP_C900 ()
|
||||
{
|
||||
/* The dispatching code will add 2 after we return, so
|
||||
we subtract two here to make things right. */
|
||||
if (!(PSW & PSW_Z))
|
||||
State.pc += SEXT8 (insn & 0xff) - 2;
|
||||
}
|
||||
|
||||
/* bgt */
|
||||
|
Loading…
Reference in New Issue
Block a user