PowerPC PLT stub matching
This patch fixes a number of bugs in ppc32 plt stub matching code. 1) The 4-insn stubs for shared libs and PIEs weren't matched. 2) The executable stub miscalculated PLT entry address (by oring a sign-extended quantity rather than adding). 3) Comments were not accurate. In addition, the insn arrays are made const. * ppc-linux-tdep.c (powerpc32_plt_stub): Make const. (powerpc32_plt_stub_so_1): Rename from powerpc32_plt_stub_so. Remove nop. Make const. Comment. (powerpc32_plt_stub_so_2): New. (POWERPC32_PLT_CHECK_LEN): Rename from POWERPC32_PLT_STUB_LEN. Correct count. Update uses. (ppc_skip_trampoline_code): Match powerpc32_plt_stub_so_2 too. Move common code reading PLT entry word. Correct powerpc32_plt_stub PLT address calculation. * ppc64-tdep.c (ppc64_standard_linkage1): Make const. (ppc64_standard_linkage2, ppc64_standard_linkage3): Likewise. (ppc64_standard_linkage4, ppc64_standard_linkage5): Likewise. (ppc64_standard_linkage6, ppc64_standard_linkage7): Likewise. (ppc64_standard_linkage8): Likewise. * rs6000-tdep.c (ppc_insns_match_pattern): Make pattern const. Correct insns description. * ppc-tdep.h (ppc_insns_match_pattern): Update prototype. Reviewed-By: Yao Qi <qiyaoltc@gmail.com>
This commit is contained in:
Alan Modra
parent
32253bb796
commit
7433498b7f
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@ -1,3 +1,23 @@
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2018-01-26 Alan Modra <amodra@gmail.com>
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* ppc-linux-tdep.c (powerpc32_plt_stub): Make const.
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(powerpc32_plt_stub_so_1): Rename from powerpc32_plt_stub_so.
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Remove nop. Make const. Comment.
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(powerpc32_plt_stub_so_2): New.
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(POWERPC32_PLT_CHECK_LEN): Rename from POWERPC32_PLT_STUB_LEN.
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Correct count. Update uses.
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(ppc_skip_trampoline_code): Match powerpc32_plt_stub_so_2 too.
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Move common code reading PLT entry word. Correct
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powerpc32_plt_stub PLT address calculation.
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* ppc64-tdep.c (ppc64_standard_linkage1): Make const.
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(ppc64_standard_linkage2, ppc64_standard_linkage3): Likewise.
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(ppc64_standard_linkage4, ppc64_standard_linkage5): Likewise.
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(ppc64_standard_linkage6, ppc64_standard_linkage7): Likewise.
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(ppc64_standard_linkage8): Likewise.
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* rs6000-tdep.c (ppc_insns_match_pattern): Make pattern const.
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Correct insns description.
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* ppc-tdep.h (ppc_insns_match_pattern): Update prototype.
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2018-01-24 Pedro Alves <palves@redhat.com>
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GCC PR libstdc++/83906
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@ -256,8 +256,8 @@ ppc_linux_return_value (struct gdbarch *gdbarch, struct value *function,
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readbuf, writebuf);
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}
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/* PLT stub in executable. */
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static struct ppc_insn_pattern powerpc32_plt_stub[] =
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/* PLT stub in an executable. */
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static const struct ppc_insn_pattern powerpc32_plt_stub[] =
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{
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{ 0xffff0000, 0x3d600000, 0 }, /* lis r11, xxxx */
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{ 0xffff0000, 0x816b0000, 0 }, /* lwz r11, xxxx(r11) */
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@ -266,16 +266,30 @@ static struct ppc_insn_pattern powerpc32_plt_stub[] =
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{ 0, 0, 0 }
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};
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/* PLT stub in shared library. */
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static struct ppc_insn_pattern powerpc32_plt_stub_so[] =
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/* PLT stubs in a shared library or PIE.
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The first variant is used when the PLT entry is within +/-32k of
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the GOT pointer (r30). */
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static const struct ppc_insn_pattern powerpc32_plt_stub_so_1[] =
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{
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{ 0xffff0000, 0x817e0000, 0 }, /* lwz r11, xxxx(r30) */
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{ 0xffffffff, 0x7d6903a6, 0 }, /* mtctr r11 */
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{ 0xffffffff, 0x4e800420, 0 }, /* bctr */
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{ 0xffffffff, 0x60000000, 0 }, /* nop */
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{ 0, 0, 0 }
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};
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#define POWERPC32_PLT_STUB_LEN ARRAY_SIZE (powerpc32_plt_stub)
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/* The second variant is used when the PLT entry is more than +/-32k
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from the GOT pointer (r30). */
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static const struct ppc_insn_pattern powerpc32_plt_stub_so_2[] =
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{
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{ 0xffff0000, 0x3d7e0000, 0 }, /* addis r11, r30, xxxx */
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{ 0xffff0000, 0x816b0000, 0 }, /* lwz r11, xxxx(r11) */
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{ 0xffffffff, 0x7d6903a6, 0 }, /* mtctr r11 */
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{ 0xffffffff, 0x4e800420, 0 }, /* bctr */
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{ 0, 0, 0 }
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};
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/* The max number of insns we check using ppc_insns_match_pattern. */
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#define POWERPC32_PLT_CHECK_LEN (ARRAY_SIZE (powerpc32_plt_stub) - 1)
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/* Check if PC is in PLT stub. For non-secure PLT, stub is in .plt
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section. For secure PLT, stub is in .text and we need to check
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@ -306,13 +320,13 @@ powerpc_linux_in_dynsym_resolve_code (CORE_ADDR pc)
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When the execution direction is EXEC_REVERSE, scan backward to
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check whether we are in the middle of a PLT stub. Currently,
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we only look-behind at most 4 instructions (the max length of PLT
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we only look-behind at most 4 instructions (the max length of a PLT
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stub sequence. */
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static CORE_ADDR
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ppc_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
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{
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unsigned int insnbuf[POWERPC32_PLT_STUB_LEN];
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unsigned int insnbuf[POWERPC32_PLT_CHECK_LEN];
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struct gdbarch *gdbarch = get_frame_arch (frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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@ -323,40 +337,47 @@ ppc_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
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/* When reverse-debugging, scan backward to check whether we are
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in the middle of trampoline code. */
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if (execution_direction == EXEC_REVERSE)
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scan_limit = 4; /* At more 4 instructions. */
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scan_limit = 4; /* At most 4 instructions. */
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for (i = 0; i < scan_limit; i++)
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{
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if (ppc_insns_match_pattern (frame, pc, powerpc32_plt_stub, insnbuf))
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{
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/* Insn pattern is
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/* Calculate PLT entry address from
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lis r11, xxxx
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lwz r11, xxxx(r11)
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Branch target is in r11. */
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target = (ppc_insn_d_field (insnbuf[0]) << 16)
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| ppc_insn_d_field (insnbuf[1]);
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target = read_memory_unsigned_integer (target, 4, byte_order);
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lwz r11, xxxx(r11). */
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target = ((ppc_insn_d_field (insnbuf[0]) << 16)
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+ ppc_insn_d_field (insnbuf[1]));
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}
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else if (ppc_insns_match_pattern (frame, pc, powerpc32_plt_stub_so,
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else if (i < ARRAY_SIZE (powerpc32_plt_stub_so_1) - 1
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&& ppc_insns_match_pattern (frame, pc, powerpc32_plt_stub_so_1,
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insnbuf))
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{
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/* Calculate PLT entry address from
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lwz r11, xxxx(r30). */
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target = (ppc_insn_d_field (insnbuf[0])
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+ get_frame_register_unsigned (frame,
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tdep->ppc_gp0_regnum + 30));
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}
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else if (ppc_insns_match_pattern (frame, pc, powerpc32_plt_stub_so_2,
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insnbuf))
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{
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/* Insn pattern is
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lwz r11, xxxx(r30)
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Branch target is in r11. */
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target = get_frame_register_unsigned (frame,
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tdep->ppc_gp0_regnum + 30)
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+ ppc_insn_d_field (insnbuf[0]);
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target = read_memory_unsigned_integer (target, 4, byte_order);
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/* Calculate PLT entry address from
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addis r11, r30, xxxx
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lwz r11, xxxx(r11). */
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target = ((ppc_insn_d_field (insnbuf[0]) << 16)
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+ ppc_insn_d_field (insnbuf[1])
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+ get_frame_register_unsigned (frame,
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tdep->ppc_gp0_regnum + 30));
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}
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else
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{
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/* Scan backward one more instructions if doesn't match. */
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/* Scan backward one more instruction if it doesn't match. */
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pc -= 4;
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continue;
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}
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target = read_memory_unsigned_integer (target, 4, byte_order);
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return target;
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}
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@ -330,7 +330,7 @@ struct ppc_insn_pattern
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};
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extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
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struct ppc_insn_pattern *pattern,
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const struct ppc_insn_pattern *pattern,
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unsigned int *insns);
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extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
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@ -80,7 +80,7 @@ ppc64_plt_entry_point (struct frame_info *frame, CORE_ADDR plt_off)
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/* Old ELFv1 PLT call stub. */
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static struct ppc_insn_pattern ppc64_standard_linkage1[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage1[] =
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{
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/* addis r12, r2, <any> */
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{ insn_d (-1, -1, -1, 0), insn_d (15, 12, 2, 0), 0 },
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@ -119,7 +119,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage1[] =
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instructions following "cmpldi r2, 0", "bnectr+" and "b <glink_i>",
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but there isn't any need to match them. */
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static struct ppc_insn_pattern ppc64_standard_linkage2[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage2[] =
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{
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/* std r2, 40(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 40, 0), 1 },
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@ -162,7 +162,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage2[] =
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/* ELFv1 PLT call stub to access PLT entries within +/- 32k of r2. */
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static struct ppc_insn_pattern ppc64_standard_linkage3[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage3[] =
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{
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/* std r2, 40(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 40, 0), 1 },
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@ -201,7 +201,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage3[] =
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A more modern variant of ppc64_standard_linkage2 differing in
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register usage. */
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static struct ppc_insn_pattern ppc64_standard_linkage4[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage4[] =
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{
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/* std r2, 40(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 40, 0), 1 },
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@ -243,7 +243,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage4[] =
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A more modern variant of ppc64_standard_linkage3 differing in
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register usage. */
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static struct ppc_insn_pattern ppc64_standard_linkage5[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage5[] =
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{
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/* std r2, 40(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 40, 0), 1 },
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@ -280,7 +280,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage5[] =
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/* ELFv2 PLT call stub to access PLT entries more than +/- 32k from r2. */
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static struct ppc_insn_pattern ppc64_standard_linkage6[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage6[] =
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{
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/* std r2, 24(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 24, 0), 1 },
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@ -302,7 +302,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage6[] =
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/* ELFv2 PLT call stub to access PLT entries within +/- 32k of r2. */
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static struct ppc_insn_pattern ppc64_standard_linkage7[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage7[] =
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{
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/* std r2, 24(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 24, 0), 1 },
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@ -322,7 +322,7 @@ static struct ppc_insn_pattern ppc64_standard_linkage7[] =
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/* ELFv2 PLT call stub to access PLT entries more than +/- 32k from r2,
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supporting fusion. */
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static struct ppc_insn_pattern ppc64_standard_linkage8[] =
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static const struct ppc_insn_pattern ppc64_standard_linkage8[] =
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{
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/* std r2, 24(r1) <optional> */
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{ -1, insn_ds (62, 2, 1, 24, 0), 1 },
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@ -6717,17 +6717,17 @@ read_insn (struct frame_info *frame, CORE_ADDR pc)
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'struct ppc_insn_pattern' objects, terminated by an entry whose
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mask is zero.
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When the match is successful, fill INSN[i] with what PATTERN[i]
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When the match is successful, fill INSNS[i] with what PATTERN[i]
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matched. If PATTERN[i] is optional, and the instruction wasn't
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present, set INSN[i] to 0 (which is not a valid PPC instruction).
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INSN should have as many elements as PATTERN. Note that, if
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PATTERN contains optional instructions which aren't present in
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memory, then INSN will have holes, so INSN[i] isn't necessarily the
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i'th instruction in memory. */
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present, set INSNS[i] to 0 (which is not a valid PPC instruction).
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INSNS should have as many elements as PATTERN, minus the terminator.
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Note that, if PATTERN contains optional instructions which aren't
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present in memory, then INSNS will have holes, so INSNS[i] isn't
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necessarily the i'th instruction in memory. */
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int
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ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
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struct ppc_insn_pattern *pattern,
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const struct ppc_insn_pattern *pattern,
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unsigned int *insns)
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{
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int i;
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