Generate a warning in the ARM assembler if a PC-relative thumb load instruction is detected in a section with insufficient alignment.

* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
	detected in a section which does not have at least 4 byte
	alignment.
	* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
	* testsuite/gas/arm/ldr-t.s: Likewise.
	* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
	* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
	disassembly, ignoring any NOPs that may have been inserted because
	of section alignment.
	* testsuite/gas/arm/ldr-t.d: Likewise.

gas/ChangeLog

@@ -1,3 +1,16 @@
+2020-03-04  Alexandre Oliva  <oliva@adacore.com>
+
+	* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
+	detected in a section which does not have at least 4 byte
+	alignment.
+	* testsuite/gas/arm/armv8-ar-it-bad.s: Add alignment directive.
+	* testsuite/gas/arm/ldr-t.s: Likewise.
+	* testsuite/gas/arm/sp-pc-usage-t.s: Likewise.
+	* testsuite/gas/arm/sp-pc-usage-t.d: Finish test at end of
+	disassembly, ignoring any NOPs that may have been inserted because
+	of section alignment.
+	* testsuite/gas/arm/ldr-t.d: Likewise.
+
 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 
 	* config/tc-i386.c (cpu_arch): Add .sev_es entry.

gas/config/tc-arm.c

@@ -29290,6 +29290,9 @@ md_apply_fix (fixS *	fixP,
 			  (((unsigned long) fixP->fx_frag->fr_address
 			    + (unsigned long) fixP->fx_where) & ~3)
 			  + (unsigned long) value);
+	  else if (get_recorded_alignment (seg) < 2)
+	    as_warn_where (fixP->fx_file, fixP->fx_line,
+			   _("section does not have enough alignment to ensure safe PC-relative loads"));
 
 	  if (value & ~0x3fc)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,

gas/testsuite/gas/arm/armv8-ar-it-bad.s

@@ -1,6 +1,6 @@
-.syntax unified
-
-.thumb
+	.syntax unified
+	.thumb
+	.align 2
 @ Wide instruction in IT block is deprecated.
 it eq
 ldrdeq r0, [r1]

gas/testsuite/gas/arm/ldr-t.d

@@ -34,4 +34,4 @@ Disassembly of section [^>]+:
 0+4e <[^>]+> f8c1 100a 	str.w	r1, \[r1, #10\]
 0+52 <[^>]+> f842 1f0a 	str.w	r1, \[r2, #10\]!
 0+56 <[^>]+> 50d1      	str	r1, \[r2, r3\]
-
+#pass

gas/testsuite/gas/arm/ldr-t.s

@@ -3,6 +3,7 @@
 .thumb
 	.global foo
 foo:
+	.align 4
 	@ldr-immediate
 
 	@!wback && (n == t)

gas/testsuite/gas/arm/sp-pc-usage-t.d

@@ -79,4 +79,4 @@ Disassembly of section .text:
 000000f6 <foo\+0xf6> bf00      	nop
 000000f8 <foo\+0xf8> bf00      	nop
 000000fa <foo\+0xfa> bf00      	nop
-
+#pass

gas/testsuite/gas/arm/sp-pc-usage-t.s

@@ -3,7 +3,8 @@
 .text
 .thumb
 	.global foo
-foo:	
+foo:
+	.align 4
 @ Section A6.1.3 "Use of 0b1101 as a register specifier".
 
 @ R13 as the source or destination register of a mov instruction.