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gas/ 

* config/tc-aarch64.c (set_other_error): New function.
	(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
	the variable to which it points with 'o'.
	(parse_operands): Update; check for write to read-only system
	registers or read from write-only ones.

gas/testsuite/

	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/tracereg-illegal.d: New file.
	* gas/aarch64/tracereg-illegal.l: Ditto.
	* gas/aarch64/tracereg-illegal.s: Ditto.
	* gas/aarch64/tracereg.d: Ditto.
	* gas/aarch64/tracereg.s: Ditto.

include/opcode

	* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
	(aarch64_sys_reg_writeonly_p): Ditto.

opcodes/

	* aarch64-opc.c (CPENT): New define.
	(F_READONLY, F_WRITEONLY): Likewise.
	(aarch64_sys_regs): Add trace unit registers.
	(aarch64_sys_reg_readonly_p): New function.
	(aarch64_sys_reg_writeonly_p): Ditto.
This commit is contained in:
Yufeng Zhang 2013-11-15 23:40:34 +00:00
parent 650948f9dc
commit 75468c93c1
14 changed files with 1053 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
2013-11-15 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* config/tc-i386.c (check_VecOperands): Reorder checks.

41
gas/config/tc-aarch64.c
View File

@ -230,6 +230,12 @@ set_fatal_syntax_error (const char *error)
{
set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
}
static inline void
set_other_error (const char *error)
{
set_error (AARCH64_OPDE_OTHER_ERROR, error);
}
/* Number of littlenums required to hold an extended precision number. */
#define MAX_LITTLENUMS 6
@ -3267,13 +3273,15 @@ parse_barrier (char **str)
}
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
Returns the encoding for the option, or PARSE_FAIL. If SYS_REG is not
NULL, return in *SYS_REG the found descriptor.
If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
static int
parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p,
const aarch64_sys_reg ** sys_reg)
{
char *p, *q;
char buf[32];
@ -3320,6 +3328,9 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
value = o->value;
}
if (sys_reg)
*sys_reg = o;
*str = q;
return value;
}
@ -5180,17 +5191,31 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SYSREG:
if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1))
== PARSE_FAIL)
{
set_syntax_error (_("unknown or missing system register name"));
goto failure;
const aarch64_sys_reg *sys_reg = NULL;
if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1,
&sys_reg))
== PARSE_FAIL)
{
set_syntax_error (_("unknown or missing system register name"));
goto failure;
}
else if (sys_reg && i == 0 && aarch64_sys_reg_readonly_p (sys_reg))
{
set_other_error (_("read-only register"));
goto failure;
}
else if (sys_reg && i == 1 && aarch64_sys_reg_writeonly_p (sys_reg))
{
set_other_error (_("write-only register"));
goto failure;
}
inst.base.operands[i].sysreg = val;
}
inst.base.operands[i].sysreg = val;
break;
case AARCH64_OPND_PSTATEFIELD:
if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0))
if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, NULL))
== PARSE_FAIL)
{
set_syntax_error (_("unknown or missing PSTATE field name"));

10
gas/testsuite/ChangeLog
View File

@ -1,3 +1,13 @@
2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
2013-11-15 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
* gas/i386/inval-avx512f.s: Add invalid test for gather instruction

2
gas/testsuite/gas/aarch64/diagnostic.l
View File

@ -97,3 +97,5 @@
[^:]*:99: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
[^:]*:100: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
[^:]*:101: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
[^:]*:102: Error: read-only register at operand 1 -- `msr trcidr7,x7'
[^:]*:103: Error: write-only register at operand 2 -- `mrs x7,trcoslar'

2
gas/testsuite/gas/aarch64/diagnostic.s
View File

@ -99,3 +99,5 @@
cinc w0, w1, nv
cset w0, al
cset w0, nv
msr trcidr7, x7
mrs x7, trcoslar

4
gas/testsuite/gas/aarch64/tracereg-illegal.d Normal file
View File

@ -0,0 +1,4 @@
#name: Trace Unit Registers - Illegal Read/Write
#as:
#source: tracereg-illegal.s
#error-output: tracereg-illegal.l

39
gas/testsuite/gas/aarch64/tracereg-illegal.l Normal file
View File

@ -0,0 +1,39 @@
[^:]*: Assembler messages:
[^:]*:35: Error: .*`msr trcstatr,x7'
[^:]*:36: Error: .*`msr trcidr8,x7'
[^:]*:37: Error: .*`msr trcidr9,x7'
[^:]*:38: Error: .*`msr trcidr10,x7'
[^:]*:39: Error: .*`msr trcidr11,x7'
[^:]*:40: Error: .*`msr trcidr12,x7'
[^:]*:41: Error: .*`msr trcidr13,x7'
[^:]*:42: Error: .*`msr trcidr0,x7'
[^:]*:43: Error: .*`msr trcidr1,x7'
[^:]*:44: Error: .*`msr trcidr2,x7'
[^:]*:45: Error: .*`msr trcidr3,x7'
[^:]*:46: Error: .*`msr trcidr4,x7'
[^:]*:47: Error: .*`msr trcidr5,x7'
[^:]*:48: Error: .*`msr trcidr6,x7'
[^:]*:49: Error: .*`msr trcidr7,x7'
[^:]*:50: Error: .*`mrs x7,trcoslar'
[^:]*:51: Error: .*`msr trcoslsr,x7'
[^:]*:52: Error: .*`msr trcpdsr,x7'
[^:]*:53: Error: .*`msr trcdevaff0,x7'
[^:]*:54: Error: .*`msr trcdevaff1,x7'
[^:]*:55: Error: .*`mrs x7,trclar'
[^:]*:56: Error: .*`msr trclsr,x7'
[^:]*:57: Error: .*`msr trcauthstatus,x7'
[^:]*:58: Error: .*`msr trcdevarch,x7'
[^:]*:59: Error: .*`msr trcdevid,x7'
[^:]*:60: Error: .*`msr trcdevtype,x7'
[^:]*:61: Error: .*`msr trcpidr4,x7'
[^:]*:62: Error: .*`msr trcpidr5,x7'
[^:]*:63: Error: .*`msr trcpidr6,x7'
[^:]*:64: Error: .*`msr trcpidr7,x7'
[^:]*:65: Error: .*`msr trcpidr0,x7'
[^:]*:66: Error: .*`msr trcpidr1,x7'
[^:]*:67: Error: .*`msr trcpidr2,x7'
[^:]*:68: Error: .*`msr trcpidr3,x7'
[^:]*:69: Error: .*`msr trccidr0,x7'
[^:]*:70: Error: .*`msr trccidr1,x7'
[^:]*:71: Error: .*`msr trccidr2,x7'
[^:]*:72: Error: .*`msr trccidr3,x7'

72
gas/testsuite/gas/aarch64/tracereg-illegal.s Normal file
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@ -0,0 +1,72 @@
/* tracereg-illegal.s Test file for AArch64 trace unit registers.
Reject writing to registers that are read-only and reading from
registers that are write-only.
Copyright 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
.text
rw_sys_reg sys_reg=trcstatr xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr8 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr9 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr10 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr11 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr12 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr13 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr0 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr1 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr2 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr3 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr4 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr5 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr6 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcidr7 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcoslar xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcoslsr xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpdsr xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcdevaff0 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcdevaff1 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trclar xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trclsr xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcauthstatus xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcdevarch xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcdevid xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcdevtype xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr4 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr5 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr6 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr7 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr0 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr1 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr2 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcpidr3 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trccidr0 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trccidr1 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trccidr2 xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trccidr3 xreg=x7 r=0 w=1

389
gas/testsuite/gas/aarch64/tracereg.d Normal file
View File

@ -0,0 +1,389 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: d5110107 msr trcprgctlr, x7
4: d5310107 mrs x7, trcprgctlr
8: d5110207 msr trcprocselr, x7
c: d5310207 mrs x7, trcprocselr
10: d5310307 mrs x7, trcstatr
14: d5110407 msr trcconfigr, x7
18: d5310407 mrs x7, trcconfigr
1c: d5110607 msr trcauxctlr, x7
20: d5310607 mrs x7, trcauxctlr
24: d5110807 msr trceventctl0r, x7
28: d5310807 mrs x7, trceventctl0r
2c: d5110907 msr trceventctl1r, x7
30: d5310907 mrs x7, trceventctl1r
34: d5110b07 msr trcstallctlr, x7
38: d5310b07 mrs x7, trcstallctlr
3c: d5110c07 msr trctsctlr, x7
40: d5310c07 mrs x7, trctsctlr
44: d5110d07 msr trcsyncpr, x7
48: d5310d07 mrs x7, trcsyncpr
4c: d5110e07 msr trcccctlr, x7
50: d5310e07 mrs x7, trcccctlr
54: d5110f07 msr trcbbctlr, x7
58: d5310f07 mrs x7, trcbbctlr
5c: d5110027 msr trctraceidr, x7
60: d5310027 mrs x7, trctraceidr
64: d5110127 msr trcqctlr, x7
68: d5310127 mrs x7, trcqctlr
6c: d5110047 msr trcvictlr, x7
70: d5310047 mrs x7, trcvictlr
74: d5110147 msr trcviiectlr, x7
78: d5310147 mrs x7, trcviiectlr
7c: d5110247 msr trcvissctlr, x7
80: d5310247 mrs x7, trcvissctlr
84: d5110347 msr trcvipcssctlr, x7
88: d5310347 mrs x7, trcvipcssctlr
8c: d5110847 msr trcvdctlr, x7
90: d5310847 mrs x7, trcvdctlr
94: d5110947 msr trcvdsacctlr, x7
98: d5310947 mrs x7, trcvdsacctlr
9c: d5110a47 msr trcvdarcctlr, x7
a0: d5310a47 mrs x7, trcvdarcctlr
a4: d5110087 msr trcseqevr0, x7
a8: d5310087 mrs x7, trcseqevr0
ac: d5110187 msr trcseqevr1, x7
b0: d5310187 mrs x7, trcseqevr1
b4: d5110287 msr trcseqevr2, x7
b8: d5310287 mrs x7, trcseqevr2
bc: d5110687 msr trcseqrstevr, x7
c0: d5310687 mrs x7, trcseqrstevr
c4: d5110787 msr trcseqstr, x7
c8: d5310787 mrs x7, trcseqstr
cc: d5110887 msr trcextinselr, x7
d0: d5310887 mrs x7, trcextinselr
d4: d51100a7 msr trccntrldvr0, x7
d8: d53100a7 mrs x7, trccntrldvr0
dc: d51101a7 msr trccntrldvr1, x7
e0: d53101a7 mrs x7, trccntrldvr1
e4: d51102a7 msr trccntrldvr2, x7
e8: d53102a7 mrs x7, trccntrldvr2
ec: d51103a7 msr trccntrldvr3, x7
f0: d53103a7 mrs x7, trccntrldvr3
f4: d51104a7 msr trccntctlr0, x7
f8: d53104a7 mrs x7, trccntctlr0
fc: d51105a7 msr trccntctlr1, x7
100: d53105a7 mrs x7, trccntctlr1
104: d51106a7 msr trccntctlr2, x7
108: d53106a7 mrs x7, trccntctlr2
10c: d51107a7 msr trccntctlr3, x7
110: d53107a7 mrs x7, trccntctlr3
114: d51108a7 msr trccntvr0, x7
118: d53108a7 mrs x7, trccntvr0
11c: d51109a7 msr trccntvr1, x7
120: d53109a7 mrs x7, trccntvr1
124: d5110aa7 msr trccntvr2, x7
128: d5310aa7 mrs x7, trccntvr2
12c: d5110ba7 msr trccntvr3, x7
130: d5310ba7 mrs x7, trccntvr3
134: d53100c7 mrs x7, trcidr8
138: d53101c7 mrs x7, trcidr9
13c: d53102c7 mrs x7, trcidr10
140: d53103c7 mrs x7, trcidr11
144: d53104c7 mrs x7, trcidr12
148: d53105c7 mrs x7, trcidr13
14c: d51100e7 msr trcimspec0, x7
150: d53100e7 mrs x7, trcimspec0
154: d51101e7 msr trcimspec1, x7
158: d53101e7 mrs x7, trcimspec1
15c: d51102e7 msr trcimspec2, x7
160: d53102e7 mrs x7, trcimspec2
164: d51103e7 msr trcimspec3, x7
168: d53103e7 mrs x7, trcimspec3
16c: d51104e7 msr trcimspec4, x7
170: d53104e7 mrs x7, trcimspec4
174: d51105e7 msr trcimspec5, x7
178: d53105e7 mrs x7, trcimspec5
17c: d51106e7 msr trcimspec6, x7
180: d53106e7 mrs x7, trcimspec6
184: d51107e7 msr trcimspec7, x7
188: d53107e7 mrs x7, trcimspec7
18c: d53108e7 mrs x7, trcidr0
190: d53109e7 mrs x7, trcidr1
194: d5310ae7 mrs x7, trcidr2
198: d5310be7 mrs x7, trcidr3
19c: d5310ce7 mrs x7, trcidr4
1a0: d5310de7 mrs x7, trcidr5
1a4: d5310ee7 mrs x7, trcidr6
1a8: d5310fe7 mrs x7, trcidr7
1ac: d5111207 msr trcrsctlr2, x7
1b0: d5311207 mrs x7, trcrsctlr2
1b4: d5111307 msr trcrsctlr3, x7
1b8: d5311307 mrs x7, trcrsctlr3
1bc: d5111407 msr trcrsctlr4, x7
1c0: d5311407 mrs x7, trcrsctlr4
1c4: d5111507 msr trcrsctlr5, x7
1c8: d5311507 mrs x7, trcrsctlr5
1cc: d5111607 msr trcrsctlr6, x7
1d0: d5311607 mrs x7, trcrsctlr6
1d4: d5111707 msr trcrsctlr7, x7
1d8: d5311707 mrs x7, trcrsctlr7
1dc: d5111807 msr trcrsctlr8, x7
1e0: d5311807 mrs x7, trcrsctlr8
1e4: d5111907 msr trcrsctlr9, x7
1e8: d5311907 mrs x7, trcrsctlr9
1ec: d5111a07 msr trcrsctlr10, x7
1f0: d5311a07 mrs x7, trcrsctlr10
1f4: d5111b07 msr trcrsctlr11, x7
1f8: d5311b07 mrs x7, trcrsctlr11
1fc: d5111c07 msr trcrsctlr12, x7
200: d5311c07 mrs x7, trcrsctlr12
204: d5111d07 msr trcrsctlr13, x7
208: d5311d07 mrs x7, trcrsctlr13
20c: d5111e07 msr trcrsctlr14, x7
210: d5311e07 mrs x7, trcrsctlr14
214: d5111f07 msr trcrsctlr15, x7
218: d5311f07 mrs x7, trcrsctlr15
21c: d5111027 msr trcrsctlr16, x7
220: d5311027 mrs x7, trcrsctlr16
224: d5111127 msr trcrsctlr17, x7
228: d5311127 mrs x7, trcrsctlr17
22c: d5111227 msr trcrsctlr18, x7
230: d5311227 mrs x7, trcrsctlr18
234: d5111327 msr trcrsctlr19, x7
238: d5311327 mrs x7, trcrsctlr19
23c: d5111427 msr trcrsctlr20, x7
240: d5311427 mrs x7, trcrsctlr20
244: d5111527 msr trcrsctlr21, x7
248: d5311527 mrs x7, trcrsctlr21
24c: d5111627 msr trcrsctlr22, x7
250: d5311627 mrs x7, trcrsctlr22
254: d5111727 msr trcrsctlr23, x7
258: d5311727 mrs x7, trcrsctlr23
25c: d5111827 msr trcrsctlr24, x7
260: d5311827 mrs x7, trcrsctlr24
264: d5111927 msr trcrsctlr25, x7
268: d5311927 mrs x7, trcrsctlr25
26c: d5111a27 msr trcrsctlr26, x7
270: d5311a27 mrs x7, trcrsctlr26
274: d5111b27 msr trcrsctlr27, x7
278: d5311b27 mrs x7, trcrsctlr27
27c: d5111c27 msr trcrsctlr28, x7
280: d5311c27 mrs x7, trcrsctlr28
284: d5111d27 msr trcrsctlr29, x7
288: d5311d27 mrs x7, trcrsctlr29
28c: d5111e27 msr trcrsctlr30, x7
290: d5311e27 mrs x7, trcrsctlr30
294: d5111f27 msr trcrsctlr31, x7
298: d5311f27 mrs x7, trcrsctlr31
29c: d5111047 msr trcssccr0, x7
2a0: d5311047 mrs x7, trcssccr0
2a4: d5111147 msr trcssccr1, x7
2a8: d5311147 mrs x7, trcssccr1
2ac: d5111247 msr trcssccr2, x7
2b0: d5311247 mrs x7, trcssccr2
2b4: d5111347 msr trcssccr3, x7
2b8: d5311347 mrs x7, trcssccr3
2bc: d5111447 msr trcssccr4, x7
2c0: d5311447 mrs x7, trcssccr4
2c4: d5111547 msr trcssccr5, x7
2c8: d5311547 mrs x7, trcssccr5
2cc: d5111647 msr trcssccr6, x7
2d0: d5311647 mrs x7, trcssccr6
2d4: d5111747 msr trcssccr7, x7
2d8: d5311747 mrs x7, trcssccr7
2dc: d5111847 msr trcsscsr0, x7
2e0: d5311847 mrs x7, trcsscsr0
2e4: d5111947 msr trcsscsr1, x7
2e8: d5311947 mrs x7, trcsscsr1
2ec: d5111a47 msr trcsscsr2, x7
2f0: d5311a47 mrs x7, trcsscsr2
2f4: d5111b47 msr trcsscsr3, x7
2f8: d5311b47 mrs x7, trcsscsr3
2fc: d5111c47 msr trcsscsr4, x7
300: d5311c47 mrs x7, trcsscsr4
304: d5111d47 msr trcsscsr5, x7
308: d5311d47 mrs x7, trcsscsr5
30c: d5111e47 msr trcsscsr6, x7
310: d5311e47 mrs x7, trcsscsr6
314: d5111f47 msr trcsscsr7, x7
318: d5311f47 mrs x7, trcsscsr7
31c: d5111067 msr trcsspcicr0, x7
320: d5311067 mrs x7, trcsspcicr0
324: d5111167 msr trcsspcicr1, x7
328: d5311167 mrs x7, trcsspcicr1
32c: d5111267 msr trcsspcicr2, x7
330: d5311267 mrs x7, trcsspcicr2
334: d5111367 msr trcsspcicr3, x7
338: d5311367 mrs x7, trcsspcicr3
33c: d5111467 msr trcsspcicr4, x7
340: d5311467 mrs x7, trcsspcicr4
344: d5111567 msr trcsspcicr5, x7
348: d5311567 mrs x7, trcsspcicr5
34c: d5111667 msr trcsspcicr6, x7
350: d5311667 mrs x7, trcsspcicr6
354: d5111767 msr trcsspcicr7, x7
358: d5311767 mrs x7, trcsspcicr7
35c: d5111087 msr trcoslar, x7
360: d5311187 mrs x7, trcoslsr
364: d5111487 msr trcpdcr, x7
368: d5311487 mrs x7, trcpdcr
36c: d5311587 mrs x7, trcpdsr
370: d5112007 msr trcacvr0, x7
374: d5312007 mrs x7, trcacvr0
378: d5112207 msr trcacvr1, x7
37c: d5312207 mrs x7, trcacvr1
380: d5112407 msr trcacvr2, x7
384: d5312407 mrs x7, trcacvr2
388: d5112607 msr trcacvr3, x7
38c: d5312607 mrs x7, trcacvr3
390: d5112807 msr trcacvr4, x7
394: d5312807 mrs x7, trcacvr4
398: d5112a07 msr trcacvr5, x7
39c: d5312a07 mrs x7, trcacvr5
3a0: d5112c07 msr trcacvr6, x7
3a4: d5312c07 mrs x7, trcacvr6
3a8: d5112e07 msr trcacvr7, x7
3ac: d5312e07 mrs x7, trcacvr7
3b0: d5112027 msr trcacvr8, x7
3b4: d5312027 mrs x7, trcacvr8
3b8: d5112227 msr trcacvr9, x7
3bc: d5312227 mrs x7, trcacvr9
3c0: d5112427 msr trcacvr10, x7
3c4: d5312427 mrs x7, trcacvr10
3c8: d5112627 msr trcacvr11, x7
3cc: d5312627 mrs x7, trcacvr11
3d0: d5112827 msr trcacvr12, x7
3d4: d5312827 mrs x7, trcacvr12
3d8: d5112a27 msr trcacvr13, x7
3dc: d5312a27 mrs x7, trcacvr13
3e0: d5112c27 msr trcacvr14, x7
3e4: d5312c27 mrs x7, trcacvr14
3e8: d5112e27 msr trcacvr15, x7
3ec: d5312e27 mrs x7, trcacvr15
3f0: d5112047 msr trcacatr0, x7
3f4: d5312047 mrs x7, trcacatr0
3f8: d5112247 msr trcacatr1, x7
3fc: d5312247 mrs x7, trcacatr1
400: d5112447 msr trcacatr2, x7
404: d5312447 mrs x7, trcacatr2
408: d5112647 msr trcacatr3, x7
40c: d5312647 mrs x7, trcacatr3
410: d5112847 msr trcacatr4, x7
414: d5312847 mrs x7, trcacatr4
418: d5112a47 msr trcacatr5, x7
41c: d5312a47 mrs x7, trcacatr5
420: d5112c47 msr trcacatr6, x7
424: d5312c47 mrs x7, trcacatr6
428: d5112e47 msr trcacatr7, x7
42c: d5312e47 mrs x7, trcacatr7
430: d5112067 msr trcacatr8, x7
434: d5312067 mrs x7, trcacatr8
438: d5112267 msr trcacatr9, x7
43c: d5312267 mrs x7, trcacatr9
440: d5112467 msr trcacatr10, x7
444: d5312467 mrs x7, trcacatr10
448: d5112667 msr trcacatr11, x7
44c: d5312667 mrs x7, trcacatr11
450: d5112867 msr trcacatr12, x7
454: d5312867 mrs x7, trcacatr12
458: d5112a67 msr trcacatr13, x7
45c: d5312a67 mrs x7, trcacatr13
460: d5112c67 msr trcacatr14, x7
464: d5312c67 mrs x7, trcacatr14
468: d5112e67 msr trcacatr15, x7
46c: d5312e67 mrs x7, trcacatr15
470: d5112087 msr trcdvcvr0, x7
474: d5312087 mrs x7, trcdvcvr0
478: d5112487 msr trcdvcvr1, x7
47c: d5312487 mrs x7, trcdvcvr1
480: d5112887 msr trcdvcvr2, x7
484: d5312887 mrs x7, trcdvcvr2
488: d5112c87 msr trcdvcvr3, x7
48c: d5312c87 mrs x7, trcdvcvr3
490: d51120a7 msr trcdvcvr4, x7
494: d53120a7 mrs x7, trcdvcvr4
498: d51124a7 msr trcdvcvr5, x7
49c: d53124a7 mrs x7, trcdvcvr5
4a0: d51128a7 msr trcdvcvr6, x7
4a4: d53128a7 mrs x7, trcdvcvr6
4a8: d5112ca7 msr trcdvcvr7, x7
4ac: d5312ca7 mrs x7, trcdvcvr7
4b0: d51120c7 msr trcdvcmr0, x7
4b4: d53120c7 mrs x7, trcdvcmr0
4b8: d51124c7 msr trcdvcmr1, x7
4bc: d53124c7 mrs x7, trcdvcmr1
4c0: d51128c7 msr trcdvcmr2, x7
4c4: d53128c7 mrs x7, trcdvcmr2
4c8: d5112cc7 msr trcdvcmr3, x7
4cc: d5312cc7 mrs x7, trcdvcmr3
4d0: d51120e7 msr trcdvcmr4, x7
4d4: d53120e7 mrs x7, trcdvcmr4
4d8: d51124e7 msr trcdvcmr5, x7
4dc: d53124e7 mrs x7, trcdvcmr5
4e0: d51128e7 msr trcdvcmr6, x7
4e4: d53128e7 mrs x7, trcdvcmr6
4e8: d5112ce7 msr trcdvcmr7, x7
4ec: d5312ce7 mrs x7, trcdvcmr7
4f0: d5113007 msr trccidcvr0, x7
4f4: d5313007 mrs x7, trccidcvr0
4f8: d5113207 msr trccidcvr1, x7
4fc: d5313207 mrs x7, trccidcvr1
500: d5113407 msr trccidcvr2, x7
504: d5313407 mrs x7, trccidcvr2
508: d5113607 msr trccidcvr3, x7
50c: d5313607 mrs x7, trccidcvr3
510: d5113807 msr trccidcvr4, x7
514: d5313807 mrs x7, trccidcvr4
518: d5113a07 msr trccidcvr5, x7
51c: d5313a07 mrs x7, trccidcvr5
520: d5113c07 msr trccidcvr6, x7
524: d5313c07 mrs x7, trccidcvr6
528: d5113e07 msr trccidcvr7, x7
52c: d5313e07 mrs x7, trccidcvr7
530: d5113027 msr trcvmidcvr0, x7
534: d5313027 mrs x7, trcvmidcvr0
538: d5113227 msr trcvmidcvr1, x7
53c: d5313227 mrs x7, trcvmidcvr1
540: d5113427 msr trcvmidcvr2, x7
544: d5313427 mrs x7, trcvmidcvr2
548: d5113627 msr trcvmidcvr3, x7
54c: d5313627 mrs x7, trcvmidcvr3
550: d5113827 msr trcvmidcvr4, x7
554: d5313827 mrs x7, trcvmidcvr4
558: d5113a27 msr trcvmidcvr5, x7
55c: d5313a27 mrs x7, trcvmidcvr5
560: d5113c27 msr trcvmidcvr6, x7
564: d5313c27 mrs x7, trcvmidcvr6
568: d5113e27 msr trcvmidcvr7, x7
56c: d5313e27 mrs x7, trcvmidcvr7
570: d5113047 msr trccidcctlr0, x7
574: d5313047 mrs x7, trccidcctlr0
578: d5113147 msr trccidcctlr1, x7
57c: d5313147 mrs x7, trccidcctlr1
580: d5113247 msr trcvmidcctlr0, x7
584: d5313247 mrs x7, trcvmidcctlr0
588: d5113347 msr trcvmidcctlr1, x7
58c: d5313347 mrs x7, trcvmidcctlr1
590: d5117087 msr trcitctrl, x7
594: d5317087 mrs x7, trcitctrl
598: d51178c7 msr trcclaimset, x7
59c: d53178c7 mrs x7, trcclaimset
5a0: d51179c7 msr trcclaimclr, x7
5a4: d53179c7 mrs x7, trcclaimclr
5a8: d5317ac7 mrs x7, trcdevaff0
5ac: d5317bc7 mrs x7, trcdevaff1
5b0: d5117cc7 msr trclar, x7
5b4: d5317dc7 mrs x7, trclsr
5b8: d5317ec7 mrs x7, trcauthstatus
5bc: d5317fc7 mrs x7, trcdevarch
5c0: d53172e7 mrs x7, trcdevid
5c4: d53173e7 mrs x7, trcdevtype
5c8: d53174e7 mrs x7, trcpidr4
5cc: d53175e7 mrs x7, trcpidr5
5d0: d53176e7 mrs x7, trcpidr6
5d4: d53177e7 mrs x7, trcpidr7
5d8: d53178e7 mrs x7, trcpidr0
5dc: d53179e7 mrs x7, trcpidr1
5e0: d5317ae7 mrs x7, trcpidr2
5e4: d5317be7 mrs x7, trcpidr3
5e8: d5317ce7 mrs x7, trccidr0
5ec: d5317de7 mrs x7, trccidr1
5f0: d5317ee7 mrs x7, trccidr2
5f4: d5317fe7 mrs x7, trccidr3

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/* tracereg.s Test file for AArch64 trace unit registers.
Copyright 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
.text
rw_sys_reg sys_reg=trcprgctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcprocselr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcstatr xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcconfigr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcauxctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trceventctl0r xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trceventctl1r xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcstallctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trctsctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsyncpr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcccctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcbbctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trctraceidr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcqctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvictlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcviiectlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvissctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvipcssctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvdctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvdsacctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvdarcctlr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcseqevr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcseqevr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcseqevr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcseqrstevr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcseqstr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcextinselr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntrldvr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntrldvr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntrldvr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntrldvr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntctlr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntctlr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntctlr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntctlr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntvr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntvr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntvr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccntvr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcidr8 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr9 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr10 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr11 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr12 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr13 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcimspec0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcimspec7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcidr0 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr2 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr3 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr4 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr5 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr6 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcidr7 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcrsctlr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr8 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr9 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr10 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr11 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr12 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr13 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr14 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr15 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr16 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr17 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr18 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr19 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr20 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr21 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr22 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr23 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr24 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr25 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr26 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr27 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr28 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr29 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr30 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcrsctlr31 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcssccr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsscsr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcsspcicr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcoslar xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trcoslsr xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpdcr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcpdsr xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcacvr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr8 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr9 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr10 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr11 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr12 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr13 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr14 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacvr15 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr8 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr9 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr10 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr11 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr12 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr13 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr14 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcacatr15 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcvr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdvcmr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcvr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr2 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr3 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr4 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr5 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr6 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcvr7 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcctlr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trccidcctlr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcctlr0 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcvmidcctlr1 xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcitctrl xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcclaimset xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcclaimclr xreg=x7 r=1 w=1
rw_sys_reg sys_reg=trcdevaff0 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcdevaff1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trclar xreg=x7 r=0 w=1
rw_sys_reg sys_reg=trclsr xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcauthstatus xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcdevarch xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcdevid xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcdevtype xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr4 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr5 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr6 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr7 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr0 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr2 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trcpidr3 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trccidr0 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trccidr1 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trccidr2 xreg=x7 r=1 w=0
rw_sys_reg sys_reg=trccidr3 xreg=x7 r=1 w=0

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_sys_reg): New typedef.

2
include/opcode/aarch64.h
View File

@ -624,6 +624,8 @@ typedef struct
extern const aarch64_sys_reg aarch64_sys_regs [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_readonly_p (const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_writeonly_p (const aarch64_sys_reg *);
typedef struct
{

8
opcodes/ChangeLog
View File

@ -1,3 +1,11 @@
2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
2013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and

236
opcodes/aarch64-opc.c
View File

@ -2676,6 +2676,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
/* for 3.9.10 System Instructions */
#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
/* Trace unit registers. */
#define CPENT(crn,crm,op2) CPENC(2,1,(crn),(crm),(op2))
#define C0 0
#define C1 1
@ -2697,7 +2699,18 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
#ifdef F_DEPRECATED
#undef F_DEPRECATED
#endif
#ifdef F_READONLY
#undef F_READONLY
#endif
#ifdef F_WRITEONLY
#undef F_WRITEONLY
#endif
#define F_DEPRECATED 0x1 /* Deprecated system register. */
#define F_READONLY 0x2 /* Not for MSR. */
#define F_WRITEONLY 0x4 /* Not for MRS. */
/* TODO there are two more issues need to be resolved
1. handle read-only and write-only system registers
@ -3010,6 +3023,217 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
{ "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
{ "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
/* Trace unit registers. */
{ "trcprgctlr", CPENT(C0,C1,0), 0 },
{ "trcprocselr", CPENT(C0,C2,0), 0 },
{ "trcstatr", CPENT(C0,C3,0), F_READONLY },
{ "trcconfigr", CPENT(C0,C4,0), 0 },
{ "trcauxctlr", CPENT(C0,C6,0), 0 },
{ "trceventctl0r", CPENT(C0,C8,0), 0 },
{ "trceventctl1r", CPENT(C0,C9,0), 0 },
{ "trcstallctlr", CPENT(C0,C11,0), 0 },
{ "trctsctlr", CPENT(C0,C12,0), 0 },
{ "trcsyncpr", CPENT(C0,C13,0), 0 },
{ "trcccctlr", CPENT(C0,C14,0), 0 },
{ "trcbbctlr", CPENT(C0,C15,0), 0 },
{ "trctraceidr", CPENT(C0,C0,1), 0 },
{ "trcqctlr", CPENT(C0,C1,1), 0 },
{ "trcvictlr", CPENT(C0,C0,2), 0 },
{ "trcviiectlr", CPENT(C0,C1,2), 0 },
{ "trcvissctlr", CPENT(C0,C2,2), 0 },
{ "trcvipcssctlr", CPENT(C0,C3,2), 0 },
{ "trcvdctlr", CPENT(C0,C8,2), 0 },
{ "trcvdsacctlr", CPENT(C0,C9,2), 0 },
{ "trcvdarcctlr", CPENT(C0,C10,2), 0 },
{ "trcseqevr0", CPENT(C0,C0,4), 0 },
{ "trcseqevr1", CPENT(C0,C1,4), 0 },
{ "trcseqevr2", CPENT(C0,C2,4), 0 },
{ "trcseqrstevr", CPENT(C0,C6,4), 0 },
{ "trcseqstr", CPENT(C0,C7,4), 0 },
{ "trcextinselr", CPENT(C0,C8,4), 0 },
{ "trccntrldvr0", CPENT(C0,C0,5), 0 },
{ "trccntrldvr1", CPENT(C0,C1,5), 0 },
{ "trccntrldvr2", CPENT(C0,C2,5), 0 },
{ "trccntrldvr3", CPENT(C0,C3,5), 0 },
{ "trccntctlr0", CPENT(C0,C4,5), 0 },
{ "trccntctlr1", CPENT(C0,C5,5), 0 },
{ "trccntctlr2", CPENT(C0,C6,5), 0 },
{ "trccntctlr3", CPENT(C0,C7,5), 0 },
{ "trccntvr0", CPENT(C0,C8,5), 0 },
{ "trccntvr1", CPENT(C0,C9,5), 0 },
{ "trccntvr2", CPENT(C0,C10,5), 0 },
{ "trccntvr3", CPENT(C0,C11,5), 0 },
{ "trcidr8", CPENT(C0,C0,6), F_READONLY },
{ "trcidr9", CPENT(C0,C1,6), F_READONLY },
{ "trcidr10", CPENT(C0,C2,6), F_READONLY },
{ "trcidr11", CPENT(C0,C3,6), F_READONLY },
{ "trcidr12", CPENT(C0,C4,6), F_READONLY },
{ "trcidr13", CPENT(C0,C5,6), F_READONLY },
{ "trcimspec0", CPENT(C0,C0,7), 0 },
{ "trcimspec1", CPENT(C0,C1,7), 0 },
{ "trcimspec2", CPENT(C0,C2,7), 0 },
{ "trcimspec3", CPENT(C0,C3,7), 0 },
{ "trcimspec4", CPENT(C0,C4,7), 0 },
{ "trcimspec5", CPENT(C0,C5,7), 0 },
{ "trcimspec6", CPENT(C0,C6,7), 0 },
{ "trcimspec7", CPENT(C0,C7,7), 0 },
{ "trcidr0", CPENT(C0,C8,7), F_READONLY },
{ "trcidr1", CPENT(C0,C9,7), F_READONLY },
{ "trcidr2", CPENT(C0,C10,7), F_READONLY },
{ "trcidr3", CPENT(C0,C11,7), F_READONLY },
{ "trcidr4", CPENT(C0,C12,7), F_READONLY },
{ "trcidr5", CPENT(C0,C13,7), F_READONLY },
{ "trcidr6", CPENT(C0,C14,7), F_READONLY },
{ "trcidr7", CPENT(C0,C15,7), F_READONLY },
{ "trcrsctlr2", CPENT(C1,C2,0), 0 },
{ "trcrsctlr3", CPENT(C1,C3,0), 0 },
{ "trcrsctlr4", CPENT(C1,C4,0), 0 },
{ "trcrsctlr5", CPENT(C1,C5,0), 0 },
{ "trcrsctlr6", CPENT(C1,C6,0), 0 },
{ "trcrsctlr7", CPENT(C1,C7,0), 0 },
{ "trcrsctlr8", CPENT(C1,C8,0), 0 },
{ "trcrsctlr9", CPENT(C1,C9,0), 0 },
{ "trcrsctlr10", CPENT(C1,C10,0), 0 },
{ "trcrsctlr11", CPENT(C1,C11,0), 0 },
{ "trcrsctlr12", CPENT(C1,C12,0), 0 },
{ "trcrsctlr13", CPENT(C1,C13,0), 0 },
{ "trcrsctlr14", CPENT(C1,C14,0), 0 },
{ "trcrsctlr15", CPENT(C1,C15,0), 0 },
{ "trcrsctlr16", CPENT(C1,C0,1), 0 },
{ "trcrsctlr17", CPENT(C1,C1,1), 0 },
{ "trcrsctlr18", CPENT(C1,C2,1), 0 },
{ "trcrsctlr19", CPENT(C1,C3,1), 0 },
{ "trcrsctlr20", CPENT(C1,C4,1), 0 },
{ "trcrsctlr21", CPENT(C1,C5,1), 0 },
{ "trcrsctlr22", CPENT(C1,C6,1), 0 },
{ "trcrsctlr23", CPENT(C1,C7,1), 0 },
{ "trcrsctlr24", CPENT(C1,C8,1), 0 },
{ "trcrsctlr25", CPENT(C1,C9,1), 0 },
{ "trcrsctlr26", CPENT(C1,C10,1), 0 },
{ "trcrsctlr27", CPENT(C1,C11,1), 0 },
{ "trcrsctlr28", CPENT(C1,C12,1), 0 },
{ "trcrsctlr29", CPENT(C1,C13,1), 0 },
{ "trcrsctlr30", CPENT(C1,C14,1), 0 },
{ "trcrsctlr31", CPENT(C1,C15,1), 0 },
{ "trcssccr0", CPENT(C1,C0,2), 0 },
{ "trcssccr1", CPENT(C1,C1,2), 0 },
{ "trcssccr2", CPENT(C1,C2,2), 0 },
{ "trcssccr3", CPENT(C1,C3,2), 0 },
{ "trcssccr4", CPENT(C1,C4,2), 0 },
{ "trcssccr5", CPENT(C1,C5,2), 0 },
{ "trcssccr6", CPENT(C1,C6,2), 0 },
{ "trcssccr7", CPENT(C1,C7,2), 0 },
{ "trcsscsr0", CPENT(C1,C8,2), 0 },
{ "trcsscsr1", CPENT(C1,C9,2), 0 },
{ "trcsscsr2", CPENT(C1,C10,2), 0 },
{ "trcsscsr3", CPENT(C1,C11,2), 0 },
{ "trcsscsr4", CPENT(C1,C12,2), 0 },
{ "trcsscsr5", CPENT(C1,C13,2), 0 },
{ "trcsscsr6", CPENT(C1,C14,2), 0 },
{ "trcsscsr7", CPENT(C1,C15,2), 0 },
{ "trcsspcicr0", CPENT(C1,C0,3), 0 },
{ "trcsspcicr1", CPENT(C1,C1,3), 0 },
{ "trcsspcicr2", CPENT(C1,C2,3), 0 },
{ "trcsspcicr3", CPENT(C1,C3,3), 0 },
{ "trcsspcicr4", CPENT(C1,C4,3), 0 },
{ "trcsspcicr5", CPENT(C1,C5,3), 0 },
{ "trcsspcicr6", CPENT(C1,C6,3), 0 },
{ "trcsspcicr7", CPENT(C1,C7,3), 0 },
{ "trcoslar", CPENT(C1,C0,4), F_WRITEONLY },
{ "trcoslsr", CPENT(C1,C1,4), F_READONLY },
{ "trcpdcr", CPENT(C1,C4,4), 0 },
{ "trcpdsr", CPENT(C1,C5,4), F_READONLY },
{ "trcacvr0", CPENT(C2,C0,0), 0 },
{ "trcacvr1", CPENT(C2,C2,0), 0 },
{ "trcacvr2", CPENT(C2,C4,0), 0 },
{ "trcacvr3", CPENT(C2,C6,0), 0 },
{ "trcacvr4", CPENT(C2,C8,0), 0 },
{ "trcacvr5", CPENT(C2,C10,0), 0 },
{ "trcacvr6", CPENT(C2,C12,0), 0 },
{ "trcacvr7", CPENT(C2,C14,0), 0 },
{ "trcacvr8", CPENT(C2,C0,1), 0 },
{ "trcacvr9", CPENT(C2,C2,1), 0 },
{ "trcacvr10", CPENT(C2,C4,1), 0 },
{ "trcacvr11", CPENT(C2,C6,1), 0 },
{ "trcacvr12", CPENT(C2,C8,1), 0 },
{ "trcacvr13", CPENT(C2,C10,1), 0 },
{ "trcacvr14", CPENT(C2,C12,1), 0 },
{ "trcacvr15", CPENT(C2,C14,1), 0 },
{ "trcacatr0", CPENT(C2,C0,2), 0 },
{ "trcacatr1", CPENT(C2,C2,2), 0 },
{ "trcacatr2", CPENT(C2,C4,2), 0 },
{ "trcacatr3", CPENT(C2,C6,2), 0 },
{ "trcacatr4", CPENT(C2,C8,2), 0 },
{ "trcacatr5", CPENT(C2,C10,2), 0 },
{ "trcacatr6", CPENT(C2,C12,2), 0 },
{ "trcacatr7", CPENT(C2,C14,2), 0 },
{ "trcacatr8", CPENT(C2,C0,3), 0 },
{ "trcacatr9", CPENT(C2,C2,3), 0 },
{ "trcacatr10", CPENT(C2,C4,3), 0 },
{ "trcacatr11", CPENT(C2,C6,3), 0 },
{ "trcacatr12", CPENT(C2,C8,3), 0 },
{ "trcacatr13", CPENT(C2,C10,3), 0 },
{ "trcacatr14", CPENT(C2,C12,3), 0 },
{ "trcacatr15", CPENT(C2,C14,3), 0 },
{ "trcdvcvr0", CPENT(C2,C0,4), 0 },
{ "trcdvcvr1", CPENT(C2,C4,4), 0 },
{ "trcdvcvr2", CPENT(C2,C8,4), 0 },
{ "trcdvcvr3", CPENT(C2,C12,4), 0 },
{ "trcdvcvr4", CPENT(C2,C0,5), 0 },
{ "trcdvcvr5", CPENT(C2,C4,5), 0 },
{ "trcdvcvr6", CPENT(C2,C8,5), 0 },
{ "trcdvcvr7", CPENT(C2,C12,5), 0 },
{ "trcdvcmr0", CPENT(C2,C0,6), 0 },
{ "trcdvcmr1", CPENT(C2,C4,6), 0 },
{ "trcdvcmr2", CPENT(C2,C8,6), 0 },
{ "trcdvcmr3", CPENT(C2,C12,6), 0 },
{ "trcdvcmr4", CPENT(C2,C0,7), 0 },
{ "trcdvcmr5", CPENT(C2,C4,7), 0 },
{ "trcdvcmr6", CPENT(C2,C8,7), 0 },
{ "trcdvcmr7", CPENT(C2,C12,7), 0 },
{ "trccidcvr0", CPENT(C3,C0,0), 0 },
{ "trccidcvr1", CPENT(C3,C2,0), 0 },
{ "trccidcvr2", CPENT(C3,C4,0), 0 },
{ "trccidcvr3", CPENT(C3,C6,0), 0 },
{ "trccidcvr4", CPENT(C3,C8,0), 0 },
{ "trccidcvr5", CPENT(C3,C10,0), 0 },
{ "trccidcvr6", CPENT(C3,C12,0), 0 },
{ "trccidcvr7", CPENT(C3,C14,0), 0 },
{ "trcvmidcvr0", CPENT(C3,C0,1), 0 },
{ "trcvmidcvr1", CPENT(C3,C2,1), 0 },
{ "trcvmidcvr2", CPENT(C3,C4,1), 0 },
{ "trcvmidcvr3", CPENT(C3,C6,1), 0 },
{ "trcvmidcvr4", CPENT(C3,C8,1), 0 },
{ "trcvmidcvr5", CPENT(C3,C10,1), 0 },
{ "trcvmidcvr6", CPENT(C3,C12,1), 0 },
{ "trcvmidcvr7", CPENT(C3,C14,1), 0 },
{ "trccidcctlr0", CPENT(C3,C0,2), 0 },
{ "trccidcctlr1", CPENT(C3,C1,2), 0 },
{ "trcvmidcctlr0", CPENT(C3,C2,2), 0 },
{ "trcvmidcctlr1", CPENT(C3,C3,2), 0 },
{ "trcitctrl", CPENT(C7,C0,4), 0 },
{ "trcclaimset", CPENT(C7,C8,6), 0 },
{ "trcclaimclr", CPENT(C7,C9,6), 0 },
{ "trcdevaff0", CPENT(C7,C10,6), F_READONLY },
{ "trcdevaff1", CPENT(C7,C11,6), F_READONLY },
{ "trclar", CPENT(C7,C12,6), F_WRITEONLY },
{ "trclsr", CPENT(C7,C13,6), F_READONLY },
{ "trcauthstatus", CPENT(C7,C14,6), F_READONLY },
{ "trcdevarch", CPENT(C7,C15,6), F_READONLY },
{ "trcdevid", CPENT(C7,C2,7), F_READONLY },
{ "trcdevtype", CPENT(C7,C3,7), F_READONLY },
{ "trcpidr4", CPENT(C7,C4,7), F_READONLY },
{ "trcpidr5", CPENT(C7,C5,7), F_READONLY },
{ "trcpidr6", CPENT(C7,C6,7), F_READONLY },
{ "trcpidr7", CPENT(C7,C7,7), F_READONLY },
{ "trcpidr0", CPENT(C7,C8,7), F_READONLY },
{ "trcpidr1", CPENT(C7,C9,7), F_READONLY },
{ "trcpidr2", CPENT(C7,C10,7), F_READONLY },
{ "trcpidr3", CPENT(C7,C11,7), F_READONLY },
{ "trccidr0", CPENT(C7,C12,7), F_READONLY },
{ "trccidr1", CPENT(C7,C13,7), F_READONLY },
{ "trccidr2", CPENT(C7,C14,7), F_READONLY },
{ "trccidr3", CPENT(C7,C15,7), F_READONLY },
{ 0, CPENC(0,0,0,0,0), 0 },
};
@ -3019,6 +3243,18 @@ aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
return (reg->flags & F_DEPRECATED) != 0;
}
bfd_boolean
aarch64_sys_reg_readonly_p (const aarch64_sys_reg *reg)
{
return (reg->flags & F_READONLY) != 0;
}
bfd_boolean
aarch64_sys_reg_writeonly_p (const aarch64_sys_reg *reg)
{
return (reg->flags & F_WRITEONLY) != 0;
}
const struct aarch64_name_value_pair aarch64_pstatefields [] =
{
{ "spsel", 0x05 },