AArch64: Fix cfinv disassembly issues
This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
This commit is contained in:
Tamar Christina
parent
168f8c6ba0
commit
7568c93bf9
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@ -1,3 +1,9 @@
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2020-01-27 Tamar Christina <tamar.christina@arm.com>
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PR 25403
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* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
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* testsuite/gas/aarch64/armv8_4-a.s: Likewise.
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2020-01-22 Maxim Blinov <maxim.blinov@embecosm.com>
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* testsuite/gas/riscv/march-ok-s.d: sx is no longer valid and
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@ -2202,3 +2202,4 @@ Disassembly of section \.text:
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[^:]+:\s+998033fe ldapursw x30, \[sp, #3\]
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[^:]+:\s+998523fe ldapursw x30, \[sp, #82\]
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[^:]+:\s+9980d3fe ldapursw x30, \[sp, #13\]
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[^:]+:\s+d500401f cfinv
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@ -144,3 +144,6 @@ func:
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gen1reg_iter ldapursw x,", [sp]"
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gen3reg_iter ldapursw x,, [x,,,]
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gen2reg_iter_offset ldapursw x,,sp
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cfinv
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@ -1,3 +1,11 @@
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2020-01-27 Tamar Christina <tamar.christina@arm.com>
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PR 25403
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* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
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* aarch64-asm-2.c: Regenerate
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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2020-01-21 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (sysret): Drop DefaultSize.
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@ -426,14 +426,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1183: /* movz */
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value = 1183; /* --> movz. */
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break;
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case 1234: /* autibsp */
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case 1233: /* autibz */
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case 1232: /* autiasp */
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case 1231: /* autiaz */
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case 1230: /* pacibsp */
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case 1229: /* pacibz */
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case 1228: /* paciasp */
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case 1227: /* paciaz */
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case 1235: /* autibsp */
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case 1234: /* autibz */
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case 1233: /* autiasp */
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case 1232: /* autiaz */
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case 1231: /* pacibsp */
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case 1230: /* pacibz */
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case 1229: /* paciasp */
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case 1228: /* paciaz */
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case 1208: /* psb */
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case 1207: /* esb */
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case 1206: /* autib1716 */
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@ -467,125 +467,125 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1216: /* sys */
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value = 1216; /* --> sys. */
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break;
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case 2032: /* bic */
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case 1282: /* and */
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value = 1282; /* --> and. */
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case 2033: /* bic */
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case 1283: /* and */
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value = 1283; /* --> and. */
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break;
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case 1265: /* mov */
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case 1284: /* and */
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value = 1284; /* --> and. */
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case 1266: /* mov */
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case 1285: /* and */
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value = 1285; /* --> and. */
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break;
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case 1269: /* movs */
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case 1285: /* ands */
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value = 1285; /* --> ands. */
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case 1270: /* movs */
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case 1286: /* ands */
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value = 1286; /* --> ands. */
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break;
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case 2033: /* cmple */
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case 1320: /* cmpge */
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value = 1320; /* --> cmpge. */
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case 2034: /* cmple */
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case 1321: /* cmpge */
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value = 1321; /* --> cmpge. */
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break;
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case 2036: /* cmplt */
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case 1323: /* cmpgt */
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value = 1323; /* --> cmpgt. */
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case 2037: /* cmplt */
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case 1324: /* cmpgt */
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value = 1324; /* --> cmpgt. */
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break;
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case 2034: /* cmplo */
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case 1325: /* cmphi */
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value = 1325; /* --> cmphi. */
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case 2035: /* cmplo */
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case 1326: /* cmphi */
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value = 1326; /* --> cmphi. */
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break;
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case 2035: /* cmpls */
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case 1328: /* cmphs */
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value = 1328; /* --> cmphs. */
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case 2036: /* cmpls */
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case 1329: /* cmphs */
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value = 1329; /* --> cmphs. */
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break;
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case 1262: /* mov */
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case 1350: /* cpy */
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value = 1350; /* --> cpy. */
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break;
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case 1264: /* mov */
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case 1263: /* mov */
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case 1351: /* cpy */
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value = 1351; /* --> cpy. */
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break;
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case 2043: /* fmov */
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case 1267: /* mov */
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case 1265: /* mov */
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case 1352: /* cpy */
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value = 1352; /* --> cpy. */
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break;
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case 1257: /* mov */
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case 1364: /* dup */
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value = 1364; /* --> dup. */
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case 2044: /* fmov */
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case 1268: /* mov */
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case 1353: /* cpy */
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value = 1353; /* --> cpy. */
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break;
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case 1259: /* mov */
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case 1256: /* mov */
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case 1258: /* mov */
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case 1365: /* dup */
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value = 1365; /* --> dup. */
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break;
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case 2042: /* fmov */
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case 1261: /* mov */
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case 1260: /* mov */
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case 1257: /* mov */
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case 1366: /* dup */
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value = 1366; /* --> dup. */
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break;
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case 1260: /* mov */
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case 1367: /* dupm */
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value = 1367; /* --> dupm. */
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case 2043: /* fmov */
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case 1262: /* mov */
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case 1367: /* dup */
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value = 1367; /* --> dup. */
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break;
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case 2037: /* eon */
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case 1369: /* eor */
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value = 1369; /* --> eor. */
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case 1261: /* mov */
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case 1368: /* dupm */
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value = 1368; /* --> dupm. */
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break;
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case 1270: /* not */
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case 1371: /* eor */
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value = 1371; /* --> eor. */
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case 2038: /* eon */
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case 1370: /* eor */
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value = 1370; /* --> eor. */
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break;
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case 1271: /* nots */
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case 1372: /* eors */
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value = 1372; /* --> eors. */
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case 1271: /* not */
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case 1372: /* eor */
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value = 1372; /* --> eor. */
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break;
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case 2038: /* facle */
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case 1377: /* facge */
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value = 1377; /* --> facge. */
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case 1272: /* nots */
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case 1373: /* eors */
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value = 1373; /* --> eors. */
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break;
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case 2039: /* faclt */
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case 1378: /* facgt */
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value = 1378; /* --> facgt. */
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case 2039: /* facle */
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case 1378: /* facge */
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value = 1378; /* --> facge. */
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break;
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case 2040: /* fcmle */
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case 1391: /* fcmge */
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value = 1391; /* --> fcmge. */
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case 2040: /* faclt */
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case 1379: /* facgt */
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value = 1379; /* --> facgt. */
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break;
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case 2041: /* fcmlt */
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case 1393: /* fcmgt */
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value = 1393; /* --> fcmgt. */
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case 2041: /* fcmle */
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case 1392: /* fcmge */
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value = 1392; /* --> fcmge. */
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break;
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case 2042: /* fcmlt */
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case 1394: /* fcmgt */
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value = 1394; /* --> fcmgt. */
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break;
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case 1255: /* fmov */
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case 1400: /* fcpy */
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value = 1400; /* --> fcpy. */
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break;
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case 1254: /* fmov */
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case 1399: /* fcpy */
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value = 1399; /* --> fcpy. */
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case 1423: /* fdup */
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value = 1423; /* --> fdup. */
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break;
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case 1253: /* fmov */
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case 1422: /* fdup */
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value = 1422; /* --> fdup. */
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break;
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case 1255: /* mov */
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case 1753: /* orr */
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value = 1753; /* --> orr. */
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break;
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case 2044: /* orn */
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case 1256: /* mov */
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case 1754: /* orr */
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value = 1754; /* --> orr. */
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break;
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case 1258: /* mov */
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case 1756: /* orr */
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value = 1756; /* --> orr. */
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case 2045: /* orn */
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case 1755: /* orr */
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value = 1755; /* --> orr. */
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break;
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case 1268: /* movs */
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case 1757: /* orrs */
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value = 1757; /* --> orrs. */
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case 1259: /* mov */
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case 1757: /* orr */
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value = 1757; /* --> orr. */
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break;
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case 1263: /* mov */
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case 1819: /* sel */
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value = 1819; /* --> sel. */
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case 1269: /* movs */
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case 1758: /* orrs */
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value = 1758; /* --> orrs. */
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break;
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case 1266: /* mov */
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case 1264: /* mov */
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case 1820: /* sel */
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value = 1820; /* --> sel. */
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break;
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case 1267: /* mov */
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case 1821: /* sel */
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value = 1821; /* --> sel. */
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break;
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default: return NULL;
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}
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File diff suppressed because it is too large
Load Diff
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@ -309,17 +309,17 @@ static const unsigned op_enum_table [] =
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391,
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413,
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415,
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1258,
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1263,
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1256,
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1255,
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1259,
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1266,
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1268,
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1264,
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1257,
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1256,
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1260,
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1267,
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1269,
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1265,
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1271,
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1270,
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1266,
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1272,
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1271,
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131,
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};
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@ -3866,6 +3866,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
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PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
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PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
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PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
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/* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
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below it. Usually we can resolve this by setting an alias condition on the flags, however that
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depends on the disassembly masks to be able to quickly find the alias. The problem is the
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cfinv instruction has no arguments, so all bits are set in the mask. Which means it will
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potentially alias with too many instructions and so the tree can't be constructed. As a work
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around we just place cfinv before msr. This means the order between these two shouldn't be
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changed. */
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V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
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CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
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CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
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CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
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@ -5043,7 +5051,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
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FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
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FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
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/* System extensions ARMv8.4-a. */
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V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
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V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
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V8_4_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
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V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
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