Fix gas and binutils testsuite failures for am33_2.0-linux target.
gas * testsuite/gas/all/gas.exp: Add am33 to the skip lists of tests passed over by the mn10300 target. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/elf/dwarf2-11.d: Correct skip of am33 target. * testsuite/gas/elf/dwarf2-12.d: Likewise. * testsuite/gas/elf/dwarf2-13.d: Likewise. * testsuite/gas/elf/dwarf2-14.d: Likewise. * testsuite/gas/elf/dwarf2-15.d: Likewise. * testsuite/gas/elf/dwarf2-16.d: Likewise. * testsuite/gas/elf/dwarf2-17.d: Likewise. * testsuite/gas/elf/dwarf2-18.d: Likewise. * testsuite/gas/elf/dwarf2-5.d: Likewise. * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise. binutils * testsuite/binutils-all/objdump.exp (cpus_expected): Add am33-2.
This commit is contained in:
parent
262cdac76d
commit
75800d2cd6
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@ -1,3 +1,7 @@
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2017-08-02 Nick Clifton <nickc@redhat.com>
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* testsuite/binutils-all/objdump.exp (cpus_expected): Add am33-2.
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2017-08-02 Alan Modra <amodra@gmail.com>
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* readelf.c (is_32bit_abs_reloc): Add R_IA64_SECREL32MSB and
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@ -34,7 +34,7 @@ send_user "Version [binutil_version $OBJDUMP]"
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set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"]
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set cpus_expected [list]
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lappend cpus_expected aarch64 alpha arc ARC700 ARCv2 arm cris
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lappend cpus_expected aarch64 alpha am33-2 arc ARC700 ARCv2 arm cris
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lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 iamcu ip2022
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lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore mep c5 h1 MicroBlaze
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lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k
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@ -1,3 +1,20 @@
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2017-08-02 Nick Clifton <nickc@redhat.com>
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* testsuite/gas/all/gas.exp: Add am33 to the skip lists of tests
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passed over by the mn10300 target.
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* testsuite/gas/elf/elf.exp: Likewise.
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* testsuite/gas/elf/dwarf2-11.d: Correct skip of am33 target.
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* testsuite/gas/elf/dwarf2-12.d: Likewise.
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* testsuite/gas/elf/dwarf2-13.d: Likewise.
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* testsuite/gas/elf/dwarf2-14.d: Likewise.
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* testsuite/gas/elf/dwarf2-15.d: Likewise.
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* testsuite/gas/elf/dwarf2-16.d: Likewise.
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* testsuite/gas/elf/dwarf2-17.d: Likewise.
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* testsuite/gas/elf/dwarf2-18.d: Likewise.
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* testsuite/gas/elf/dwarf2-5.d: Likewise.
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* testsuite/gas/elf/dwarf2-6.d: Likewise.
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* testsuite/gas/elf/dwarf2-7.d: Likewise.
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2017-08-01 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/21874
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@ -92,6 +92,7 @@ gas_test_error "assign-bad.s" "" "== assignment for symbol already set"
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# .equ works differently on some targets.
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# linkrelax-ing prevents most forward references from working.
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case $target_triplet in {
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{ am3*-*-* } { }
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{ *c54x*-*-* } { }
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{ cr16*-*-* } { }
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{ crx*-*-* } { }
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@ -139,6 +140,7 @@ if { ![is_aout_format] } {
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# pdp11 gets unexpected reloc types.
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case $target_triplet in {
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{ alpha*-*-* } { }
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{ am3*-*-* } { }
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{ cr16*-*-* } { }
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{ crx*-*-* } { }
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{ h8300-*-* } { }
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@ -278,7 +280,7 @@ if { ![istarget *c30*-*-*]
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# The vax fails because VMS can apparently actually handle this
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# case in relocs, so gas doesn't handle it itself.
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# msp430, mn10[23]00 and riscv emit two relocs to handle the difference of two symbols.
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setup_xfail "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" "vax*-*-vms*"
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setup_xfail "am3*-*-*" "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" "vax*-*-vms*"
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do_930509a
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}
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@ -1,10 +1,10 @@
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#as:
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#readelf: -wL
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#name: DWARF2 11
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* m32c-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* m32c-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Decoded dump of debug contents of section \.debug_line:
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@ -1,10 +1,10 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 12
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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@ -1,10 +1,10 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 13
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 01 *.*
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@ -1,10 +1,10 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 14
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 01 *.*
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@ -1,10 +1,10 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 15
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 01 *.*
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@ -1,11 +1,11 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 16
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The mep target tries to relay code sections which breaks symbolic view computations.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 01 *.*
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@ -1,11 +1,11 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 17
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The mep target tries to relay code sections which breaks symbolic view computations.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 00 *.*
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@ -1,10 +1,10 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 18
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 0100 *.*
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@ -1,11 +1,11 @@
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#as:
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#readelf: -x.rodata -wlL
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#name: DWARF2 5
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 rx and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 rx and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The mep target tries to relay code sections which breaks symbolic view computations.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* rx-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* rx-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 01010201 010203 *.*
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@ -1,8 +1,8 @@
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#as:
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#readelf: -wlL
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#name: DWARF2 6
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# These targets either do not support or do not evaluate the subtraction of symbols at assembly time
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* xtensa-*
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# These targets either do not support or do not evaluate the subtraction of symbols at assembly time.
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* xtensa-*
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Raw dump of debug contents of section .debug_line:
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@ -1,10 +1,10 @@
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#as:
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#readelf: -x.rodata -wL
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#name: DWARF2 7
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# The am3 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time
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# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
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# The riscv targets do not support the subtraction of symbols.
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# The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
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#not-target: am3-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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#not-target: am3*-* avr-* cr16-* crx-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
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Hex dump of section '\.rodata':
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0x00000000 01 *.*
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@ -93,6 +93,7 @@ if { [is_elf_format] } then {
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# optimization because it interfers with link-time relaxation of
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# function prologues.
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if {![istarget "mn10300-*-*"]
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&& ![istarget "am3*-*-*"]
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&& ![istarget "xtensa*-*-*"]
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&& ![istarget "msp430*-*-*"]
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&& ![istarget "nds32*-*-*"]
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}
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case $target_triplet in {
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{ alpha*-*-* } { }
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{ am3*-*-* } { }
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{ *c54x*-*-* } { }
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{ cr16*-*-* } { }
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{ crx*-*-* } { }
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