x86: introduce operand type "instance"
Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
This commit is contained in:
Jan Beulich
parent
aa16be3993
commit
75e5731b8f
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@ -1,3 +1,14 @@
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2019-11-12 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (operand_type_set, operand_type_and,
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operand_type_and_not, operand_type_or, operand_type_xor): Handle
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"instance" field specially.
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(operand_size_match, md_assemble, match_template, process_suffix,
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check_byte_reg, check_long_reg, check_qword_reg, check_word_reg,
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process_operands, build_modrm_byte): Use "instance" instead of
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"acc" / "inoutportreg" / "shiftcount" fields.
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(optimize_imm): Adjust comment.
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2019-11-11 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/illegal-sve2.s: Add smaxp/sminp cases
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@ -1613,6 +1613,7 @@ operand_type_set (union i386_operand_type *x, unsigned int v)
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}
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x->bitfield.class = ClassNone;
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x->bitfield.instance = InstanceNone;
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}
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static INLINE int
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@ -1829,6 +1830,8 @@ operand_type_and (i386_operand_type x, i386_operand_type y)
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{
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if (x.bitfield.class != y.bitfield.class)
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x.bitfield.class = ClassNone;
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if (x.bitfield.instance != y.bitfield.instance)
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x.bitfield.instance = InstanceNone;
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switch (ARRAY_SIZE (x.array))
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{
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@ -1851,6 +1854,7 @@ static INLINE i386_operand_type
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operand_type_and_not (i386_operand_type x, i386_operand_type y)
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{
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gas_assert (y.bitfield.class == ClassNone);
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gas_assert (y.bitfield.instance == InstanceNone);
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switch (ARRAY_SIZE (x.array))
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{
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@ -1875,6 +1879,9 @@ operand_type_or (i386_operand_type x, i386_operand_type y)
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gas_assert (x.bitfield.class == ClassNone ||
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y.bitfield.class == ClassNone ||
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x.bitfield.class == y.bitfield.class);
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gas_assert (x.bitfield.instance == InstanceNone ||
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y.bitfield.instance == InstanceNone ||
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x.bitfield.instance == y.bitfield.instance);
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switch (ARRAY_SIZE (x.array))
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{
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@ -1897,6 +1904,7 @@ static INLINE i386_operand_type
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operand_type_xor (i386_operand_type x, i386_operand_type y)
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{
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gas_assert (y.bitfield.class == ClassNone);
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gas_assert (y.bitfield.instance == InstanceNone);
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switch (ARRAY_SIZE (x.array))
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{
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@ -2084,7 +2092,7 @@ operand_size_match (const insn_template *t)
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break;
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}
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if (t->operand_types[j].bitfield.acc
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if (t->operand_types[j].bitfield.instance == Accum
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&& (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
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{
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match = 0;
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@ -2121,7 +2129,7 @@ mismatch:
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&& !match_simd_size (t, j, given))
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goto mismatch;
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if (t->operand_types[j].bitfield.acc
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if (t->operand_types[j].bitfield.instance == Accum
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&& (!match_operand_size (t, j, given)
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|| !match_simd_size (t, j, given)))
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goto mismatch;
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@ -4453,9 +4461,8 @@ md_assemble (char *line)
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with 3 operands or less. */
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if (i.operands <= 3)
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for (j = 0; j < i.operands; j++)
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if (i.types[j].bitfield.inoutportreg
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|| i.types[j].bitfield.shiftcount
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|| (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
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if (i.types[j].bitfield.instance != InstanceNone
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&& !i.types[j].bitfield.xmmword)
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i.reg_operands--;
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/* ImmExt should be processed after SSE2AVX. */
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@ -5076,9 +5083,9 @@ optimize_imm (void)
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else if (i.reg_operands)
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{
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/* Figure out a suffix from the last register operand specified.
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We can't do this properly yet, ie. excluding InOutPortReg,
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but the following works for instructions with immediates.
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In any case, we can't set i.suffix yet. */
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We can't do this properly yet, i.e. excluding special register
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instances, but the following works for instructions with
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immediates. In any case, we can't set i.suffix yet. */
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for (op = i.operands; --op >= 0;)
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if (i.types[op].bitfield.class != Reg)
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continue;
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@ -5897,15 +5904,17 @@ match_template (char mnem_suffix)
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zero-extend %eax to %rax. */
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if (flag_code == CODE_64BIT
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&& t->base_opcode == 0x90
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&& i.types[0].bitfield.acc && i.types[0].bitfield.dword
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&& i.types[1].bitfield.acc && i.types[1].bitfield.dword)
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&& i.types[0].bitfield.instance == Accum
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&& i.types[0].bitfield.dword
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&& i.types[1].bitfield.instance == Accum
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&& i.types[1].bitfield.dword)
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continue;
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/* xrelease mov %eax, <disp> is another special case. It must not
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match the accumulator-only encoding of mov. */
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if (flag_code != CODE_64BIT
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&& i.hle_prefix
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&& t->base_opcode == 0xa0
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&& i.types[0].bitfield.acc
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&& i.types[0].bitfield.instance == Accum
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&& (i.flags[1] & Operand_Mem))
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continue;
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/* Fall through. */
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@ -6284,8 +6293,8 @@ process_suffix (void)
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}
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for (op = i.operands; --op >= 0;)
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if (!i.tm.operand_types[op].bitfield.inoutportreg
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&& !i.tm.operand_types[op].bitfield.shiftcount)
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if (i.tm.operand_types[op].bitfield.instance == InstanceNone
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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{
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if (i.types[op].bitfield.class != Reg)
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continue;
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@ -6502,8 +6511,10 @@ process_suffix (void)
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&& ! (i.operands == 2
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&& i.tm.base_opcode == 0x90
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&& i.tm.extension_opcode == None
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&& i.types[0].bitfield.acc && i.types[0].bitfield.qword
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&& i.types[1].bitfield.acc && i.types[1].bitfield.qword))
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&& i.types[0].bitfield.instance == Accum
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&& i.types[0].bitfield.qword
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&& i.types[1].bitfield.instance == Accum
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&& i.types[1].bitfield.qword))
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i.rex |= REX_W;
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break;
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@ -6565,7 +6576,8 @@ check_byte_reg (void)
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continue;
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/* I/O port address operands are OK too. */
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if (i.tm.operand_types[op].bitfield.inoutportreg)
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if (i.tm.operand_types[op].bitfield.instance == RegD
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&& i.tm.operand_types[op].bitfield.word)
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continue;
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/* crc32 doesn't generate this warning. */
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@ -6626,7 +6638,7 @@ check_long_reg (void)
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them. (eg. movzb) */
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else if (i.types[op].bitfield.byte
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& (i.tm.operand_types[op].bitfield.word
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|| i.tm.operand_types[op].bitfield.dword))
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{
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@ -6641,7 +6653,7 @@ check_long_reg (void)
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else if ((!quiet_warnings || flag_code == CODE_64BIT)
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&& i.types[op].bitfield.word
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& i.tm.operand_types[op].bitfield.dword)
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{
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/* Prohibit these changes in the 64bit mode, since the
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@ -6663,7 +6675,7 @@ check_long_reg (void)
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/* Warn if the r prefix on a general reg is present. */
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else if (i.types[op].bitfield.qword
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& i.tm.operand_types[op].bitfield.dword)
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{
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if (intel_syntax
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@ -6697,7 +6709,7 @@ check_qword_reg (void)
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them. (eg. movzb) */
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else if (i.types[op].bitfield.byte
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& (i.tm.operand_types[op].bitfield.word
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|| i.tm.operand_types[op].bitfield.dword))
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{
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@ -6712,7 +6724,7 @@ check_qword_reg (void)
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else if ((i.types[op].bitfield.word
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|| i.types[op].bitfield.dword)
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& i.tm.operand_types[op].bitfield.qword)
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{
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/* Prohibit these changes in the 64bit mode, since the
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@ -6747,7 +6759,7 @@ check_word_reg (void)
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them. (eg. movzb) */
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else if (i.types[op].bitfield.byte
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& (i.tm.operand_types[op].bitfield.word
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|| i.tm.operand_types[op].bitfield.dword))
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{
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@ -6763,7 +6775,7 @@ check_word_reg (void)
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&& (i.types[op].bitfield.dword
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|| i.types[op].bitfield.qword)
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&& (i.tm.operand_types[op].bitfield.class == Reg
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|| i.tm.operand_types[op].bitfield.acc)
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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&& i.tm.operand_types[op].bitfield.word)
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{
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/* Prohibit these changes in the 64bit mode, since the
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@ -6888,14 +6900,14 @@ process_operands (void)
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&& MAX_OPERANDS > dupl
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&& operand_type_equal (&i.types[dest], ®xmm));
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if (i.tm.operand_types[0].bitfield.acc
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if (i.tm.operand_types[0].bitfield.instance == Accum
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&& i.tm.operand_types[0].bitfield.xmmword)
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{
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if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
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{
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/* Keep xmm0 for instructions with VEX prefix and 3
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sources. */
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i.tm.operand_types[0].bitfield.acc = 0;
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i.tm.operand_types[0].bitfield.instance = InstanceNone;
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i.tm.operand_types[0].bitfield.class = RegSIMD;
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goto duplicate;
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}
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@ -6960,7 +6972,7 @@ duplicate:
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if (i.tm.opcode_modifier.immext)
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process_immext ();
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}
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else if (i.tm.operand_types[0].bitfield.acc
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else if (i.tm.operand_types[0].bitfield.instance == Accum
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&& i.tm.operand_types[0].bitfield.xmmword)
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{
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unsigned int j;
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@ -7207,9 +7219,11 @@ build_modrm_byte (void)
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gas_assert (i.imm_operands == 1
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|| (i.imm_operands == 0
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&& (i.tm.opcode_modifier.vexvvvv == VEXXDS
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|| i.types[0].bitfield.shiftcount)));
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|| (i.types[0].bitfield.instance == RegC
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&& i.types[0].bitfield.byte))));
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if (operand_type_check (i.types[0], imm)
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|| i.types[0].bitfield.shiftcount)
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|| (i.types[0].bitfield.instance == RegC
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&& i.types[0].bitfield.byte))
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source = 1;
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else
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source = 0;
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@ -10320,7 +10334,8 @@ i386_att_operand (char *operand_string)
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/* Special case for (%dx) while doing input/output op. */
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if (i.base_reg
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&& i.base_reg->reg_type.bitfield.inoutportreg
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&& i.base_reg->reg_type.bitfield.instance == RegD
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&& i.base_reg->reg_type.bitfield.word
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&& i.index_reg == 0
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&& i.log2_scale_factor == 0
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&& i.seg[i.mem_operands] == 0
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@ -1,3 +1,24 @@
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2019-11-12 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Adjust
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OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
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OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
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OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
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(operand_instances): New.
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(operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
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(output_operand_type): New parameter "instance". Process it.
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(process_i386_operand_type): New local variable "instance".
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(main): Adjust static assertions.
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* i386-opc.h (INSTANCE_WIDTH): Define.
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(enum operand_instance): New.
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(Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
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(union i386_operand_type): Replace acc, inoutportreg, and
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shiftcount by instance.
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* i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
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* i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
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Add Instance=.
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* i386-init.h, i386-tbl.h: Re-generate.
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2019-11-11 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
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@ -422,9 +422,9 @@ static initializer operand_type_init[] =
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{ "OPERAND_TYPE_DISP64",
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"Disp64" },
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{ "OPERAND_TYPE_INOUTPORTREG",
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"InOutPortReg" },
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"Instance=RegD|Word" },
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{ "OPERAND_TYPE_SHIFTCOUNT",
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"ShiftCount" },
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"Instance=RegC|Byte" },
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{ "OPERAND_TYPE_CONTROL",
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"Class=RegCR" },
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{ "OPERAND_TYPE_TEST",
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@ -434,7 +434,7 @@ static initializer operand_type_init[] =
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{ "OPERAND_TYPE_FLOATREG",
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"Class=Reg|Tbyte" },
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{ "OPERAND_TYPE_FLOATACC",
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"Acc|Tbyte" },
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"Instance=Accum|Tbyte" },
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{ "OPERAND_TYPE_SREG",
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"Class=SReg" },
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{ "OPERAND_TYPE_JUMPABSOLUTE",
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@ -454,13 +454,13 @@ static initializer operand_type_init[] =
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{ "OPERAND_TYPE_ESSEG",
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"EsSeg" },
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{ "OPERAND_TYPE_ACC8",
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"Acc|Byte" },
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"Instance=Accum|Byte" },
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{ "OPERAND_TYPE_ACC16",
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"Acc|Word" },
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"Instance=Accum|Word" },
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{ "OPERAND_TYPE_ACC32",
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"Acc|Dword" },
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"Instance=Accum|Dword" },
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{ "OPERAND_TYPE_ACC64",
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"Acc|Qword" },
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"Instance=Accum|Qword" },
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{ "OPERAND_TYPE_DISP16_32",
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"Disp16|Disp32" },
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{ "OPERAND_TYPE_ANYDISP",
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@ -695,6 +695,19 @@ static const struct {
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#undef CLASS
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#define INSTANCE(n) #n, n
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static const struct {
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const char *name;
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enum operand_instance value;
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} operand_instances[] = {
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INSTANCE (Accum),
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INSTANCE (RegC),
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INSTANCE (RegD),
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};
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#undef INSTANCE
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static bitfield operand_types[] =
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{
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BITFIELD (Imm1),
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@ -710,9 +723,6 @@ static bitfield operand_types[] =
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BITFIELD (Disp32),
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BITFIELD (Disp32S),
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BITFIELD (Disp64),
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BITFIELD (InOutPortReg),
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BITFIELD (ShiftCount),
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BITFIELD (Acc),
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BITFIELD (JumpAbsolute),
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BITFIELD (EsSeg),
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BITFIELD (Byte),
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@ -1147,20 +1157,21 @@ enum stage {
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static void
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output_operand_type (FILE *table, enum operand_class class,
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enum operand_instance instance,
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const bitfield *types, unsigned int size,
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enum stage stage, const char *indent)
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{
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unsigned int i;
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fprintf (table, "{ { %d, ", class);
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fprintf (table, "{ { %d, %d, ", class, instance);
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for (i = 0; i < size - 1; i++)
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{
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if (((i + 2) % 20) != 0)
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if (((i + 3) % 20) != 0)
|
||||
fprintf (table, "%d, ", types[i].value);
|
||||
else
|
||||
fprintf (table, "%d,", types[i].value);
|
||||
if (((i + 2) % 20) == 0)
|
||||
if (((i + 3) % 20) == 0)
|
||||
{
|
||||
/* We need \\ for macro. */
|
||||
if (stage == stage_macros)
|
||||
|
|
@ -1179,6 +1190,7 @@ process_i386_operand_type (FILE *table, char *op, enum stage stage,
|
|||
{
|
||||
char *str, *next, *last;
|
||||
enum operand_class class = ClassNone;
|
||||
enum operand_instance instance = InstanceNone;
|
||||
bitfield types [ARRAY_SIZE (operand_types)];
|
||||
|
||||
/* Copy the default operand type. */
|
||||
|
|
@ -1206,6 +1218,17 @@ process_i386_operand_type (FILE *table, char *op, enum stage stage,
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (str && !strncmp(str, "Instance=", 9))
|
||||
{
|
||||
for (i = 0; i < ARRAY_SIZE(operand_instances); ++i)
|
||||
if (!strcmp(str + 9, operand_instances[i].name))
|
||||
{
|
||||
instance = operand_instances[i].value;
|
||||
str = NULL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (str)
|
||||
{
|
||||
|
|
@ -1226,8 +1249,8 @@ process_i386_operand_type (FILE *table, char *op, enum stage stage,
|
|||
set_bitfield("Disp32S", types, 1, ARRAY_SIZE (types), lineno);
|
||||
}
|
||||
}
|
||||
output_operand_type (table, class, types, ARRAY_SIZE (types), stage,
|
||||
indent);
|
||||
output_operand_type (table, class, instance, types, ARRAY_SIZE (types),
|
||||
stage, indent);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -1717,9 +1740,11 @@ main (int argc, char **argv)
|
|||
|
||||
/* Check the unused bitfield in i386_operand_type. */
|
||||
#ifdef OTUnused
|
||||
static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH == OTNum + 1);
|
||||
static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH + INSTANCE_WIDTH
|
||||
== OTNum + 1);
|
||||
#else
|
||||
static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH == OTNum);
|
||||
static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH + INSTANCE_WIDTH
|
||||
== OTNum);
|
||||
|
||||
c = OTNumOfBits - OTMax - 1;
|
||||
if (c)
|
||||
|
|
|
|||
|
|
@ -1365,196 +1365,196 @@
|
|||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG \
|
||||
{ { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGYMM \
|
||||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGZMM \
|
||||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMASK \
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGBND \
|
||||
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYIMM \
|
||||
{ { 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
|
|
|||
|
|
@ -719,12 +719,23 @@ enum operand_class
|
|||
RegBND, /* Bound register */
|
||||
};
|
||||
|
||||
/* Special operand instances. */
|
||||
|
||||
#define INSTANCE_WIDTH 3
|
||||
enum operand_instance
|
||||
{
|
||||
InstanceNone,
|
||||
Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
|
||||
RegC, /* Register to hold shift count = %cl */
|
||||
RegD, /* Register to hold in/out port addr = %dx */
|
||||
};
|
||||
|
||||
/* Position of operand_type bits. */
|
||||
|
||||
enum
|
||||
{
|
||||
/* Class */
|
||||
Class = CLASS_WIDTH - 1,
|
||||
/* Class and Instance */
|
||||
ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
|
||||
/* 1 bit immediate */
|
||||
Imm1,
|
||||
/* 8 bit immediate */
|
||||
|
|
@ -756,14 +767,8 @@ enum
|
|||
Disp32S,
|
||||
/* 64 bit displacement */
|
||||
Disp64,
|
||||
/* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
|
||||
Acc,
|
||||
/* Register which can be used for base or index in memory operand. */
|
||||
BaseIndex,
|
||||
/* Register to hold in/out port addr = dx */
|
||||
InOutPortReg,
|
||||
/* Register to hold shift count = cl */
|
||||
ShiftCount,
|
||||
/* Absolute address for jump. */
|
||||
JumpAbsolute,
|
||||
/* String insn operand with fixed es segment */
|
||||
|
|
@ -809,6 +814,7 @@ typedef union i386_operand_type
|
|||
struct
|
||||
{
|
||||
unsigned int class:CLASS_WIDTH;
|
||||
unsigned int instance:INSTANCE_WIDTH;
|
||||
unsigned int imm1:1;
|
||||
unsigned int imm8:1;
|
||||
unsigned int imm8s:1;
|
||||
|
|
@ -821,10 +827,7 @@ typedef union i386_operand_type
|
|||
unsigned int disp32:1;
|
||||
unsigned int disp32s:1;
|
||||
unsigned int disp64:1;
|
||||
unsigned int acc:1;
|
||||
unsigned int baseindex:1;
|
||||
unsigned int inoutportreg:1;
|
||||
unsigned int shiftcount:1;
|
||||
unsigned int jumpabsolute:1;
|
||||
unsigned int esseg:1;
|
||||
unsigned int byte:1;
|
||||
|
|
|
|||
|
|
@ -27,6 +27,10 @@
|
|||
#define Reg32 Class=Reg|Dword
|
||||
#define Reg64 Class=Reg|Qword
|
||||
|
||||
#define Acc Instance=Accum
|
||||
#define ShiftCount Instance=RegC|Byte
|
||||
#define InOutPortReg Instance=RegD|Word
|
||||
|
||||
#define FloatAcc Acc|Tbyte
|
||||
#define FloatReg Class=Reg|Tbyte
|
||||
|
||||
|
|
|
|||
|
|
@ -19,10 +19,10 @@
|
|||
// 02110-1301, USA.
|
||||
|
||||
// Make %st first as we test for it.
|
||||
st, Class=Reg|Acc|Tbyte, 0, 0, 11, 33
|
||||
st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
|
||||
// 8 bit regs
|
||||
al, Class=Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
|
||||
cl, Class=Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
|
||||
al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
|
||||
cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
|
||||
dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
|
||||
bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
|
||||
ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
|
||||
|
|
@ -46,9 +46,9 @@ r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
|
|||
r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
|
||||
r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
|
||||
// 16 bit regs
|
||||
ax, Class=Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
|
||||
ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
|
||||
cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
|
||||
dx, Class=Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
|
||||
dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
|
||||
bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
|
||||
sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
|
||||
bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
|
||||
|
|
@ -63,7 +63,7 @@ r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
|
|||
r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// 32 bit regs
|
||||
eax, Class=Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval
|
||||
eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
|
||||
ecx, Class=Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval
|
||||
edx, Class=Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval
|
||||
ebx, Class=Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval
|
||||
|
|
@ -79,7 +79,7 @@ r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
|
|||
r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
rax, Class=Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0
|
||||
rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
|
||||
rcx, Class=Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2
|
||||
rdx, Class=Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1
|
||||
rbx, Class=Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3
|
||||
|
|
@ -180,7 +180,7 @@ mm4, Class=RegMMX, 0, 4, 33, 45
|
|||
mm5, Class=RegMMX, 0, 5, 34, 46
|
||||
mm6, Class=RegMMX, 0, 6, 35, 47
|
||||
mm7, Class=RegMMX, 0, 7, 36, 48
|
||||
xmm0, Class=RegSIMD|Acc|Xmmword, 0, 0, 21, 17
|
||||
xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
|
||||
xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
|
||||
xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
|
||||
xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
|
||||
|
|
@ -292,7 +292,7 @@ eip, Dword, RegRex64, RegIP, 8, Dw2Inval
|
|||
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
|
||||
eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
|
||||
// fp regs.
|
||||
st(0), Class=Reg|Acc|Tbyte, 0, 0, 11, 33
|
||||
st(0), Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
|
||||
st(1), Class=Reg|Tbyte, 0, 1, 12, 34
|
||||
st(2), Class=Reg|Tbyte, 0, 2, 13, 35
|
||||
st(3), Class=Reg|Tbyte, 0, 3, 14, 36
|
||||
|
|
|
|||
28156
opcodes/i386-tbl.h
28156
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue