R_PPC64_PCREL_OPT
The loads and stores handled in the second instruction of a sequence marked by R_PPC64_PCREL_OPT may be a prefix instruction. For example: pld ra,symbol@got@pcrel 0: pld rt,off(ra) .reloc 0b-8,R_PPC64_PCREL_OPT,(.-8)-(0b-8) can be optimised to pld rt,symbol+off@pcrel pnop * elf64-ppc.c (xlate_pcrel_opt): Handle prefix loads and stores in second instruction. (ppc64_elf_relocate_section): Likewise.
This commit is contained in:
Alan Modra
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89bdc77eab
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77486630b1
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@ -1,3 +1,9 @@
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2019-09-05 Alan Modra <amodra@gmail.com>
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* elf64-ppc.c (xlate_pcrel_opt): Handle prefix loads and stores
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in second instruction.
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(ppc64_elf_relocate_section): Likewise.
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2019-09-05 Alan Modra <amodra@gmail.com>
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PR 24955
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@ -8282,12 +8282,31 @@ ok_lo_toc_insn (unsigned int insn, enum elf_ppc64_reloc_type r_type)
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static bfd_boolean
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xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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{
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uint32_t insn2 = *pinsn2 >> 32;
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uint64_t i1new;
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uint64_t insn1 = *pinsn1;
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uint64_t insn2 = *pinsn2;
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bfd_signed_vma off;
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if ((insn2 & (63ULL << 58)) == 1ULL << 58)
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{
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/* Check that regs match. */
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if (((insn2 >> 16) & 31) != ((insn1 >> 21) & 31))
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return FALSE;
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/* P8LS or PMLS form, non-pcrel. */
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if ((insn2 & (-1ULL << 50) & ~(1ULL << 56)) != (1ULL << 58))
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return FALSE;
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*pinsn1 = (insn2 & ~(31 << 16) & ~0x3ffff0000ffffULL) | (1ULL << 52);
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*pinsn2 = PNOP;
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off = ((insn2 >> 16) & 0x3ffff0000ULL) | (insn2 & 0xffff);
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*poff = (off ^ 0x200000000ULL) - 0x200000000ULL;
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return TRUE;
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}
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insn2 >>= 32;
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/* Check that regs match. */
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if (((insn2 >> 16) & 31) != ((*pinsn1 >> 21) & 31))
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if (((insn2 >> 16) & 31) != ((insn1 >> 21) & 31))
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return FALSE;
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switch ((insn2 >> 26) & 63)
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@ -8308,7 +8327,7 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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case 54: /* stfd */
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/* These are the PMLS cases, where we just need to tack a prefix
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on the insn. */
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i1new = ((1ULL << 58) | (2ULL << 56) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (2ULL << 56) | (1ULL << 52)
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| (insn2 & ((63ULL << 26) | (31ULL << 21))));
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off = insn2 & 0xffff;
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break;
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@ -8316,7 +8335,7 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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case 58: /* lwa, ld */
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if ((insn2 & 1) != 0)
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return FALSE;
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i1new = ((1ULL << 58) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| (insn2 & 2 ? 41ULL << 26 : 57ULL << 26)
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| (insn2 & (31ULL << 21)));
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off = insn2 & 0xfffc;
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@ -8325,7 +8344,7 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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case 57: /* lxsd, lxssp */
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if ((insn2 & 3) < 2)
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return FALSE;
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i1new = ((1ULL << 58) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| ((40ULL | (insn2 & 3)) << 26)
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| (insn2 & (31ULL << 21)));
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off = insn2 & 0xfffc;
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@ -8336,14 +8355,14 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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return FALSE;
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else if ((insn2 & 3) >= 2)
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{
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i1new = ((1ULL << 58) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| ((44ULL | (insn2 & 3)) << 26)
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| (insn2 & (31ULL << 21)));
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off = insn2 & 0xfffc;
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}
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else
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{
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i1new = ((1ULL << 58) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| ((50ULL | (insn2 & 4) | ((insn2 & 8) >> 3)) << 26)
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| (insn2 & (31ULL << 21)));
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off = insn2 & 0xfff0;
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@ -8351,7 +8370,7 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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break;
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case 56: /* lq */
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i1new = ((1ULL << 58) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| (insn2 & ((63ULL << 26) | (31ULL << 21))));
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off = insn2 & 0xffff;
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break;
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@ -8359,14 +8378,14 @@ xlate_pcrel_opt (uint64_t *pinsn1, uint64_t *pinsn2, bfd_signed_vma *poff)
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case 62: /* std, stq */
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if ((insn2 & 1) != 0)
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return FALSE;
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i1new = ((1ULL << 58) | (1ULL << 52)
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insn1 = ((1ULL << 58) | (1ULL << 52)
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| ((insn2 & 2) == 0 ? 61ULL << 26 : 60ULL << 26)
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| (insn2 & (31ULL << 21)));
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off = insn2 & 0xfffc;
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break;
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}
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*pinsn1 = i1new;
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*pinsn1 = insn1;
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*pinsn2 = (uint64_t) NOP << 32;
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*poff = (off ^ 0x8000) - 0x8000;
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return TRUE;
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@ -15413,7 +15432,12 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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pinsn2 = bfd_get_32 (input_bfd, contents + off2);
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pinsn2 <<= 32;
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if ((pinsn2 & (63ULL << 58)) == 1ULL << 58)
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break;
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{
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if (off2 + 8 > input_section->size)
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break;
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pinsn2 |= bfd_get_32 (input_bfd,
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contents + off2 + 4);
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}
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if (xlate_pcrel_opt (&pinsn, &pinsn2, &addend_off))
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{
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addend += addend_off;
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@ -15424,6 +15448,9 @@ ppc64_elf_relocate_section (bfd *output_bfd,
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contents + offset + 4);
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bfd_put_32 (input_bfd, pinsn2 >> 32,
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contents + off2);
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if ((pinsn2 & (63ULL << 58)) == 1ULL << 58)
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bfd_put_32 (input_bfd, pinsn2,
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contents + off2 + 4);
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}
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}
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}
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@ -1,3 +1,9 @@
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2019-09-05 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/pcrelopt.s,
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* testsuite/ld-powerpc/pcrelopt.d: Test offset and prefix in
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second instruction.
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2019-08-29 Alan Modra <amodra@gmail.com>
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PR ld/24406
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@ -80,10 +80,17 @@ Disassembly of section \.text:
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.*: (04 10 00 01|01 00 10 04) pstxv vs0,66028
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.*: (d8 00 01 ec|ec 01 00 d8)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 00 01|01 00 10 04) pld r9,66008
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.*: (e5 20 01 d8|d8 01 20 e5)
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.*: (e8 09 00 00|00 00 09 e8) ld r0,0\(r9\)
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.*: (06 10 00 01|01 00 10 06) plbz r3,70676
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.*: (88 60 14 14|14 14 60 88)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (06 10 00 01|01 00 10 06) pla r7,66000
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.*: (38 e0 01 d0|d0 01 e0 38)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (04 10 12 35|35 12 10 04) plq r4,305485896
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.*: (e0 80 58 48|48 58 80 e0)
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.*: (07 00 00 00|00 00 00 07) pnop
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.*: (00 00 00 00|00 00 00 00)
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.*: (04 10 00 01|01 00 10 04) pld r9,65976
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.*: (e5 20 01 b8|b8 01 20 e5)
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.*: (e8 09 00 00|00 00 09 e8) ld r0,0\(r9\)
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.*: (06 10 00 01|01 00 10 06) pla r7,65972
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.*: (38 e0 01 b4|b4 01 e0 38)
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.*: (88 c7 00 00|00 00 c7 88) lbz r6,0\(r7\)
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@ -103,6 +103,18 @@ _start:
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.reloc .-8,R_PPC64_PCREL_OPT,0f-(.-8)
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0: stxv 0,0(9)
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#offsets are allowed too
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pld 9,sym@got@pcrel
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0:
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lbz 3,0x1234(9)
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.reloc 0b-8,R_PPC64_PCREL_OPT,(.-4)-(0b-8)
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#and prefix insns as the second insn
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pld 9,sym@got@pcrel
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0:
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plq 4,0x12345678(9)
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.reloc 0b-8,R_PPC64_PCREL_OPT,(.-8)-(0b-8)
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# This should not optimize
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.extern i
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.type i,@object
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