* mn10200-opc.c: Create mn10200 opcode table.
* mn10200-dis.c: Flesh out mn10200 disassembler. Not ready,
but moving along nicely.
Checkpointing today's mn10200 work.
This commit is contained in:
Jeff Law
parent
559c664adb
commit
781766e7e1
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@ -1,3 +1,9 @@
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Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com)
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* mn10200-opc.c: Create mn10200 opcode table.
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* mn10200-dis.c: Flesh out mn10200 disassembler. Not ready,
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but moving along nicely.
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Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de)
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* Makefile.in (ALL_MACHINES): Add mips16-opc.o.
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@ -22,13 +22,359 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "opcode/mn10200.h"
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#include "dis-asm.h"
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static void disassemble PARAMS ((bfd_vma memaddr,
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struct disassemble_info *info,
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unsigned long insn));
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static void disassemble PARAMS ((bfd_vma, struct disassemble_info *,
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unsigned long insn, unsigned long,
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unsigned int));
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int
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print_insn_mn10200 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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int status;
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bfd_byte buffer[4];
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unsigned long insn;
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unsigned long extension;
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unsigned int consume;
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/* First figure out how big the opcode is. */
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status = (*info->read_memory_func) (memaddr, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = *(unsigned char *) buffer;
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/* These are one byte insns. */
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if ((insn & 0xf3) == 0x00
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|| (insn & 0xf0) == 0x10
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|| (insn & 0xfc) == 0x3c
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|| (insn & 0xf3) == 0x41
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|| (insn & 0xf3) == 0x40
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|| (insn & 0xfc) == 0x50
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|| (insn & 0xfc) == 0x54
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|| (insn & 0xf0) == 0x60
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|| (insn & 0xf0) == 0x70
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|| ((insn & 0xf0) == 0x80
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| ((insn & 0xf0) == 0x90
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| ((insn & 0xf0) == 0xa0
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| ((insn & 0xf0) == 0xb0
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&& (insn & 0x0c) >> 2 != (insn & 0x03))
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|| (insn & 0xff) == 0xcb
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|| (insn & 0xfc) == 0xd0
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|| (insn & 0xfc) == 0xd4
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|| (insn & 0xfc) == 0xd8
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|| (insn & 0xf0) == 0xe0)
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{
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extension = 0;
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consume = 1;
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}
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/* These are two byte insns. */
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else if ((insn & 0xf0) == 0x80
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|| (insn & 0xf0) == 0x90
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|| (insn & 0xf0) == 0xa0
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|| (insn & 0xf0) == 0xb0
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|| (insn & 0xfc) == 0x20
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|| (insn & 0xfc) == 0x28
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|| (insn & 0xf3) == 0x43
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|| (insn & 0xf3) == 0x42
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|| (insn & 0xfc) == 0x58
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|| (insn & 0xfc) == 0x5c
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|| ((insn & 0xf0) == 0xc0
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&& (insn & 0xff) != 0xcb
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&& (insn & 0xff) != 0xcc
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&& (insn & 0xff) != 0xcd)
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|| (insn & 0xff) == 0xf0
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|| (insn & 0xff) == 0xf1
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|| (insn & 0xff) == 0xf2
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|| (insn & 0xff) == 0xf3
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|| (insn & 0xff) == 0xf4
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|| (insn & 0xff) == 0xf5
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|| (insn & 0xff) == 0xf6)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb16 (buffer);
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extension = 0;
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consume = 2;
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}
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/* These are three byte insns. */
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else if ((insn & 0xff) == 0xf8
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|| (insn & 0xff) == 0xcc
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|| (insn & 0xff) == 0xf9
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|| (insn & 0xf3) == 0x01
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|| (insn & 0xf3) == 0x02
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|| (insn & 0xf3) == 0x03
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|| (insn & 0xfc) == 0x24
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|| (insn & 0xfc) == 0x2c
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|| (insn & 0xfc) == 0x30
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|| (insn & 0xfc) == 0x34
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|| (insn & 0xfc) == 0x38
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|| (insn & 0xff) == 0xde
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|| (insn & 0xff) == 0xdf
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|| (insn & 0xff) == 0xcc)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb16 (buffer);
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insn <<= 8;
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status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn |= *(unsigned char *)buffer;
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extension = 0;
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consume = 3;
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}
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/* These are four byte insns. */
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else if ((insn & 0xff) == 0xfa
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|| (insn & 0xff) == 0xfb)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb32 (buffer);
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extension = 0;
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consume = 4;
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}
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/* These are five byte insns. */
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else if ((insn & 0xff) == 0xcd
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|| (insn & 0xff) == 0xdc)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb32 (buffer);
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status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr + 4, info);
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return -1;
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}
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extension = *(unsigned char *) buffer;
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consume = 5;
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}
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/* These are six byte insns. */
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else if ((insn & 0xff) == 0xfd
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|| (insn & 0xff) == 0xfc)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb32 (buffer);
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status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr + 4, info);
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return -1;
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}
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extension = bfd_getb16 (buffer);
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consume = 6;
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}
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/* Else its a seven byte insns (in theory). */
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else
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{
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getb32 (buffer);
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status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr + 4, info);
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return -1;
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}
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extension = bfd_getb16 (buffer);
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extension <<= 8;
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status = (*info->read_memory_func) (memaddr + 6, buffer, 1, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr + 6, info);
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return -1;
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}
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extension |= *(unsigned char *)buffer;
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consume = 7;
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}
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disassemble (memaddr, info, insn, extension, consume);
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return consume;
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}
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static void
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disassemble (memaddr, info, insn, extension, size)
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bfd_vma memaddr;
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struct disassemble_info *info;
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unsigned long insn;
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unsigned long extension;
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unsigned int size;
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{
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struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes;
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const struct mn10200_operand *operand;
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int match = 0;
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/* Find the opcode. */
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while (op->name)
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{
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int mysize, extra_shift;
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#if 0
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if (op->format == FMT_S0)
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mysize = 1;
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else if (op->format == FMT_S1
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|| op->format == FMT_D0)
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mysize = 2;
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else if (op->format == FMT_S2
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|| op->format == FMT_D1)
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mysize = 3;
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else if (op->format == FMT_S4)
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mysize = 5;
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else if (op->format == FMT_D2)
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mysize = 4;
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else if (op->format == FMT_D4)
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mysize = 6;
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else
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mysize = 7;
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if (op->format == FMT_D1 || op->format == FMT_S1)
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extra_shift = 8;
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else if (op->format == FMT_D2 || op->format == FMT_D4
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|| op->format == FMT_S2 || op->format == FMT_S4
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|| op->format == FMT_S6 || op->format == FMT_D5)
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extra_shift = 16;
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else
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extra_shift = 0;
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#endif
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if ((op->mask & insn) == op->opcode
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&& size == mysize)
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{
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const unsigned char *opindex_ptr;
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unsigned int nocomma;
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int paren = 0;
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match = 1;
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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/* Now print the operands. */
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for (opindex_ptr = op->operands, nocomma = 1;
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*opindex_ptr != 0;
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opindex_ptr++)
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{
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unsigned long value;
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operand = &mn10200_operands[*opindex_ptr];
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if ((operand->flags & MN10200_OPERAND_SPLIT) != 0)
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{
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unsigned long temp;
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value = insn & ((1 << operand->bits) - 1);
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value <<= (32 - operand->bits);
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temp = extension >> operand->shift;
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temp &= ((1 << (32 - operand->bits)) - 1);
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value |= temp;
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}
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else
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{
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value = ((insn >> (operand->shift))
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& ((1 << operand->bits) - 1));
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}
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if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
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value = ((long)(value << (32 - operand->bits))
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>> (32 - operand->bits));
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if (!nocomma
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&& (!paren
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|| ((operand->flags & MN10200_OPERAND_PAREN) == 0)))
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(*info->fprintf_func) (info->stream, ",");
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nocomma = 0;
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if ((operand->flags & MN10200_OPERAND_DREG) != 0)
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{
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value = ((insn >> (operand->shift + extra_shift))
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& ((1 << operand->bits) - 1));
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(*info->fprintf_func) (info->stream, "d%d", value);
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}
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else if ((operand->flags & MN10200_OPERAND_AREG) != 0)
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{
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value = ((insn >> (operand->shift + extra_shift))
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& ((1 << operand->bits) - 1));
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(*info->fprintf_func) (info->stream, "a%d", value);
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}
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else if ((operand->flags & MN10200_OPERAND_PSW) != 0)
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(*info->fprintf_func) (info->stream, "psw");
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else if ((operand->flags & MN10200_OPERAND_MDR) != 0)
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(*info->fprintf_func) (info->stream, "mdr");
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else if ((operand->flags & MN10200_OPERAND_PAREN) != 0)
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{
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if (paren)
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(*info->fprintf_func) (info->stream, ")");
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else
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{
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(*info->fprintf_func) (info->stream, "(");
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nocomma = 1;
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}
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paren = !paren;
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}
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else if ((operand->flags & MN10200_OPERAND_PCREL) != 0)
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(*info->print_address_func) (value + memaddr, info);
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else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0)
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(*info->print_address_func) (value, info);
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else
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(*info->fprintf_func) (info->stream, "%d", value);
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}
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/* All done. */
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break;
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}
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op++;
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}
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if (!match)
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{
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(*info->fprintf_func) (info->stream, "unknown\t0x%04x", insn);
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}
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}
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@ -21,9 +21,121 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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const struct mn10200_operand mn10200_operands[] = {
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#define UNUSED 0
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{ 0, 0, 0 },
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{0, 0, 0},
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/* dn register in the first register operand position. */
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#define DN0 (UNUSED+1)
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{2, 0, MN10200_OPERAND_DREG},
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/* dn register in the second register operand position. */
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#define DN1 (DN0+1)
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{2, 2, MN10200_OPERAND_DREG},
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/* dm register in the first register operand position. */
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#define DM0 (DN1+1)
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{2, 0, MN10200_OPERAND_DREG},
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/* dm register in the second register operand position. */
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#define DM1 (DM0+1)
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{2, 2, MN10200_OPERAND_DREG},
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/* an register in the first register operand position. */
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#define AN0 (DM1+1)
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{2, 0, MN10200_OPERAND_AREG},
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/* an register in the second register operand position. */
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#define AN1 (AN0+1)
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{2, 2, MN10200_OPERAND_AREG},
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/* am register in the first register operand position. */
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#define AM0 (AN1+1)
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{2, 0, MN10200_OPERAND_AREG},
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/* am register in the second register operand position. */
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#define AM1 (AM0+1)
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{2, 2, MN10200_OPERAND_AREG},
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/* 8 bit unsigned immediate which may promote to a 16bit
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unsigned immediate. */
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#define IMM8 (AM1+1)
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{8, 0, MN10200_OPERAND_PROMOTE},
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/* 16 bit unsigned immediate which may promote to a 32bit
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unsigned immediate. */
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#define IMM16 (IMM8+1)
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{16, 0, MN10200_OPERAND_PROMOTE},
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/* 16 bit pc-relative immediate which may promote to a 16bit
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pc-relative immediate. */
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#define IMM16_PCREL (IMM16+1)
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{16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_PCREL},
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/* 16bit unsigned dispacement in a memory operation which
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may promote to a 32bit displacement. */
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#define IMM16_MEM (IMM16_PCREL+1)
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{16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},
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/* 24 immediate, low 16 bits in the main instruction
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word, 8 in the extension word. */
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#define IMM24 (IMM16_MEM+1)
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{24, 0, MN10200_OPERAND_EXTENDED},
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/* 32bit pc-relative offset. */
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#define IMM24_PCREL (IMM24+1)
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{24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL},
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/* 32bit memory offset. */
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#define IMM24_MEM (IMM24_PCREL+1)
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{24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},
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/* Processor status word. */
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#define PSW (IMM24_MEM+1)
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{0, 0, MN10200_OPERAND_PSW},
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/* MDR register. */
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#define MDR (PSW+1)
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{0, 0, MN10200_OPERAND_MDR},
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/* Index register. */
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#define DI (MDR+1)
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{2, 2, MN10200_OPERAND_DREG},
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/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
|
||||
#define SD8 (DI+1)
|
||||
{8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
|
||||
|
||||
/* 16 bit signed displacement, may promote to 32bit dispacement. */
|
||||
#define SD16 (SD8+1)
|
||||
{16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
|
||||
|
||||
/* 8 bit pc-relative displacement. */
|
||||
#define SD8N_PCREL (SD16+1)
|
||||
{8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL},
|
||||
|
||||
/* 8 bit signed immediate which may promote to 16bit signed immediate. */
|
||||
#define SIMM8 (SD8N_PCREL+1)
|
||||
{8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
|
||||
|
||||
/* 16 bit signed immediate which may promote to 32bit immediate. */
|
||||
#define SIMM16 (SIMM8+1)
|
||||
{16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
|
||||
|
||||
/* Either an open paren or close paren. */
|
||||
#define PAREN (SIMM16+1)
|
||||
{0, 0, MN10200_OPERAND_PAREN},
|
||||
|
||||
/* dn register that appears in the first and second register positions. */
|
||||
#define DN01 (PAREN+1)
|
||||
{2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},
|
||||
|
||||
/* an register that appears in the first and second register positions. */
|
||||
#define AN01 (DN01+1)
|
||||
{2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
|
||||
} ;
|
||||
|
||||
#define MEM(ADDR) PAREN, ADDR, PAREN
|
||||
#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
|
||||
|
||||
/* The opcode table.
|
||||
|
||||
|
|
@ -43,7 +155,185 @@ const struct mn10200_operand mn10200_operands[] = {
|
|||
sorted by major opcode. */
|
||||
|
||||
const struct mn10200_opcode mn10200_opcodes[] = {
|
||||
{ 0, 0, 0, {0}, } } ;
|
||||
{ "mov", 0x8000, 0xfc00, FMT_5, {SIMM8, DN01}},
|
||||
{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}},
|
||||
{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
|
||||
{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}},
|
||||
{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
|
||||
{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
|
||||
{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
|
||||
{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
|
||||
{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
|
||||
{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}},
|
||||
{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
|
||||
{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
|
||||
{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
|
||||
{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
|
||||
{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
|
||||
{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
|
||||
{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
|
||||
{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
|
||||
{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
|
||||
{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
|
||||
{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}},
|
||||
{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}},
|
||||
{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}},
|
||||
{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}},
|
||||
{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
|
||||
{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
|
||||
{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
|
||||
{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
|
||||
{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
|
||||
{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
|
||||
{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}},
|
||||
{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
|
||||
{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}},
|
||||
{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}},
|
||||
{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}},
|
||||
{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
|
||||
{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
|
||||
{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
|
||||
{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
|
||||
|
||||
{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
|
||||
{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
|
||||
{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
|
||||
{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
|
||||
{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
|
||||
{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
|
||||
|
||||
{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
|
||||
{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
|
||||
{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
|
||||
{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
|
||||
{ "movb", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
|
||||
{ "movb", 0x10, 0xf0, FMT_1, {DM1, MEM(AN0)}},
|
||||
{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
|
||||
{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
|
||||
{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
|
||||
{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
|
||||
{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
|
||||
{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
|
||||
|
||||
{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}},
|
||||
{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
|
||||
{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
|
||||
{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
|
||||
{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
|
||||
{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
|
||||
{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
|
||||
|
||||
{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}},
|
||||
{ "extx", 0xb0, 0xfc, FMT_1, {DN0}},
|
||||
{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}},
|
||||
{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}},
|
||||
{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}},
|
||||
|
||||
{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}},
|
||||
{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
|
||||
{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}},
|
||||
{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}},
|
||||
{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
|
||||
{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
|
||||
{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}},
|
||||
{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
|
||||
{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
|
||||
{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}},
|
||||
{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
|
||||
|
||||
{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}},
|
||||
{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
|
||||
{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}},
|
||||
{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}},
|
||||
{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}},
|
||||
{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}},
|
||||
{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}},
|
||||
{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
|
||||
{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
|
||||
{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
|
||||
{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
|
||||
{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
|
||||
{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}},
|
||||
{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}},
|
||||
{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
|
||||
{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
|
||||
{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}},
|
||||
{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}},
|
||||
{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
|
||||
|
||||
{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}},
|
||||
{ "and", 0xf7000000, 0xfffc0000, FMT_6, {IMM16, DN0}},
|
||||
{ "and", 0xf7100000, 0xffff0000, FMT_6, {IMM16, PSW}},
|
||||
{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}},
|
||||
{ "or", 0xf7400000, 0xfffc0000, FMT_6, {IMM16, DN0}},
|
||||
{ "or", 0xf7140000, 0xffff0000, FMT_6, {IMM16, PSW}},
|
||||
{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}},
|
||||
{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {IMM16, DN0}},
|
||||
{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}},
|
||||
|
||||
{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}},
|
||||
{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}},
|
||||
{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}},
|
||||
{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}},
|
||||
|
||||
{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}},
|
||||
{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {IMM16, DN0}},
|
||||
{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
|
||||
{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
|
||||
|
||||
{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}},
|
||||
|
||||
{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
||||
|
||||
{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}},
|
||||
{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}},
|
||||
{ "jmp", 0xf000, 0xfffc, FMT_4, {PAREN,AN1,PAREN}},
|
||||
{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}},
|
||||
{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}},
|
||||
{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
|
||||
|
||||
{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}},
|
||||
|
||||
{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}},
|
||||
{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}},
|
||||
{ 0, 0, 0, 0, {0}},
|
||||
|
||||
} ;
|
||||
|
||||
const int mn10200_num_opcodes =
|
||||
sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
|
||||
|
|
|
|||
Loading…
Reference in New Issue