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Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and LD4R. 

PR binutils/21380
opcodes	* aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
	LD3R and LD4R.

gas	* testsuite/gas/aarch64/illegal-3.s: New file.
	* testsuite/gas/aarch64/illegal-3.d: New file.
This commit is contained in:
Nick Clifton 2017-04-21 12:18:06 +01:00
parent 73b58fda3b
commit 792f174f8a
5 changed files with 43 additions and 8 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2017-04-21 Nick Clifton <nickc@redhat.com>
PR binutils/21380
* testsuite/gas/aarch64/illegal-3.s: New file.
* testsuite/gas/aarch64/illegal-3.d: New file.
2017-04-11 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (md_show_usage): Delete mention of -mhtm.

14
gas/testsuite/gas/aarch64/illegal-3.d Normal file
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@ -0,0 +1,14 @@
#name: Illegal Instructions - 3
#as:
#source: illegal-3.s
#objdump: -d
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
0: 4dc2d4ec .inst 0x4dc2d4ec ; undefined
4: 4de2d4fc .inst 0x4de2d4fc ; undefined
8: 4dc2f4ec .inst 0x4dc2f4ec ; undefined
c: 4de2f4fc .inst 0x4de2f4fc ; undefined

9
gas/testsuite/gas/aarch64/illegal-3.s Normal file
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@ -0,0 +1,9 @@
// Test the disassembler's detection of illegal binary sequences.
// PR 21380:
.inst 0x4dc2d4ec
.inst 0x4de2d4fc
.inst 0x4dc2f4ec
.inst 0x4de2f4fc

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2017-04-21 Nick Clifton <nickc@redhat.com>
PR binutils/21380
* aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
LD3R and LD4R.
2017-04-13 Alan Modra <amodra@gmail.com>
* epiphany-desc.c: Regenerate.

16
opcodes/aarch64-tbl.h
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@ -2552,12 +2552,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
SIMD_INSN ("st4", 0xd202000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)),
SIMD_INSN ("ld1", 0xd400000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)),
SIMD_INSN ("ld3", 0xd402000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)),
SIMD_INSN ("ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
SIMD_INSN ("ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)),
SIMD_INSN ("ld1r", 0xd40c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
SIMD_INSN ("ld3r", 0xd40e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)),
SIMD_INSN ("ld2", 0xd600000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)),
SIMD_INSN ("ld4", 0xd602000, 0xbfff2000, asisdlso, 0, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)),
SIMD_INSN ("ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)),
SIMD_INSN ("ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)),
SIMD_INSN ("ld2r", 0xd60c000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)),
SIMD_INSN ("ld4r", 0xd60e000, 0xbffff000, asisdlso, 0, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)),
/* AdvSIMD load/store single structure (post-indexed). */
SIMD_INSN ("st1", 0xd800000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)),
SIMD_INSN ("st3", 0xd802000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)),
@ -2565,12 +2565,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
SIMD_INSN ("st4", 0xda02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)),
SIMD_INSN ("ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)),
SIMD_INSN ("ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)),
SIMD_INSN ("ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
SIMD_INSN ("ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)),
SIMD_INSN ("ld1r", 0xdc0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
SIMD_INSN ("ld3r", 0xdc0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)),
SIMD_INSN ("ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)),
SIMD_INSN ("ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)),
SIMD_INSN ("ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)),
SIMD_INSN ("ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)),
SIMD_INSN ("ld2r", 0xde0c000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)),
SIMD_INSN ("ld4r", 0xde0e000, 0xbfe0f000, asisdlsop, 0, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)),
/* AdvSIMD scalar two-reg misc. */
SIMD_INSN ("suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE),
SIMD_INSN ("sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE),