gas/testsuite/
* gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d, gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions and expanded PC-relative offsets. opcodes/ * arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove generic coprocessor instructions for FPA loads and stores. (print_insn_coprocessor): Remove %C support. Display address for PC-relative offsets in %A.
This commit is contained in:
Daniel Jacobowitz
parent
fa78c13aad
commit
79862e4574
@ -1,3 +1,9 @@
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2009-11-12 Daniel Jacobowitz <dan@codesourcery.com>
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* gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d,
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gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions
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and expanded PC-relative offsets.
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2009-11-11 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/prefix.d: Swap order of ADDR and REP prefixes.
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@ -13,12 +13,12 @@ Disassembly of section .text:
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0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
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0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
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0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
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0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\]
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0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo>
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0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
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0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
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0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.*
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0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
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0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\]
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0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar>
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0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
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0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\}
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0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\}
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@ -119,13 +119,13 @@ Disassembly of section .text:
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0+1bc <[^>]+> 0ef3f114 ? cnfeeq f3, f4
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0+1c0 <[^>]+> 0ef4f117 ? cnfeeq f4, f7
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0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0
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0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\)
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0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\)
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0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
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0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\]
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0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\].*
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0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!.*
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0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020.*
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0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] ; \(ldcl 2, cr6, \[pc\]\)
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0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12 ; \(stc 2, cr15, \[r8\], #12\)
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0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] ; .* <l\+.*>
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0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12
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0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\].*
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0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\].*
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0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!.*
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@ -6,4 +6,4 @@
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.*: *file format .*arm.*
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Disassembly of section .text:
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0+00 <[^>]*> ed2dc203[ ]+sfm[ ]+f4, 1, \[sp, #-12\]! ; \(stc 2, cr12, \[sp, #-12\]!\)
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0+00 <[^>]*> ed2dc203[ ]+sfm[ ]+f4, 1, \[sp, #-12\]!
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@ -24,11 +24,11 @@ Disassembly of section .text:
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0+34 <[^>]*> ec600101 ? stfe f0, \[r0\], #-4
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0+38 <[^>]*> edc08100 ? stfp f0, \[r0\]
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0+3c <[^>]*> ec608101 ? stfp f0, \[r0\], #-4
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0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\)
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0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] ; \(ldc 2, cr0, \[r0\]\)
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0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\]
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0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\]
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0+48 <[^>]*> ed10020c ? lfm f0, 4, \[r0, #-48\].*
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0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\] ; \(stc 2, cr0, \[r0\]\)
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0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\]
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0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, #-48\].*
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0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\] ; \(stc 2, cr0, \[r0\]\)
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0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\]
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0+58 <[^>]*> 5d800100 ? stfpls f0, \[r0\]
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0+5c <[^>]*> 5d800100 ? stfpls f0, \[r0\]
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@ -1,3 +1,10 @@
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2009-11-12 Daniel Jacobowitz <dan@codesourcery.com>
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* arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove
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generic coprocessor instructions for FPA loads and stores.
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(print_insn_coprocessor): Remove %C support. Display address for
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PC-relative offsets in %A.
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2009-11-11 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (all_prefixes): New.
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@ -69,7 +69,6 @@ struct opcode16
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%u print condition code (unconditional in ARM mode)
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%A print address for ldc/stc/ldf/stf instruction
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%B print vstm/vldm register list
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%C print vstr/vldr address operand
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%I print cirrus signed shift immediate: bits 0..3|4..6
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%F print the COUNT field of a LFM/SFM instruction.
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%P print floating point precision in arithmetic insn
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@ -248,8 +247,8 @@ static const struct opcode32 coprocessor_opcodes[] =
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{FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
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{FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
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{FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
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{FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A\t; (stc%22'l%c %8-11d, cr%12-15d, %A)"},
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{FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A\t; (ldc%22'l%c %8-11d, cr%12-15d, %A)"},
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{FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
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{FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
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/* Register load/store. */
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
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@ -258,8 +257,8 @@ static const struct opcode32 coprocessor_opcodes[] =
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
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{FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
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{FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
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{FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
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{FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
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@ -1808,19 +1807,26 @@ print_insn_coprocessor (bfd_vma pc,
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case 'A':
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{
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int offset = given & 0xff;
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int rn = (given >> 16) & 0xf;
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int offset = given & 0xff;
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func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
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value_in_comment = offset * 4;
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if (NEGATIVE_BIT_SET)
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value_in_comment = - value_in_comment;
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if (PRE_BIT_SET || WRITEBACK_BIT_SET)
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{
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/* Not unindexed. The offset is scaled. */
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offset = offset * 4;
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if (NEGATIVE_BIT_SET)
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offset = - offset;
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if (rn != 15)
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value_in_comment = offset;
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}
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if (PRE_BIT_SET)
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{
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if (offset)
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func (stream, ", #%d]%s",
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value_in_comment,
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offset,
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WRITEBACK_BIT_SET ? "!" : "");
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else
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func (stream, "]");
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@ -1832,7 +1838,7 @@ print_insn_coprocessor (bfd_vma pc,
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if (WRITEBACK_BIT_SET)
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{
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if (offset)
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func (stream, ", #%d", value_in_comment);
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func (stream, ", #%d", offset);
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}
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else
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{
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@ -1840,6 +1846,12 @@ print_insn_coprocessor (bfd_vma pc,
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value_in_comment = offset;
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}
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}
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if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
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{
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func (stream, "\t; ");
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info->print_address_func (offset + pc
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+ info->bytes_per_chunk * 2, info);
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}
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}
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break;
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@ -1857,33 +1869,6 @@ print_insn_coprocessor (bfd_vma pc,
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}
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break;
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case 'C':
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{
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int rn = (given >> 16) & 0xf;
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int offset = (given & 0xff) * 4;
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func (stream, "[%s", arm_regnames[rn]);
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if (offset)
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{
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if (NEGATIVE_BIT_SET)
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offset = - offset;
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func (stream, ", #%d", offset);
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if (rn != 15)
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value_in_comment = offset;
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}
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func (stream, "]");
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if (rn == 15)
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{
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func (stream, "\t; ");
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/* FIXME: Unsure if info->bytes_per_chunk is the
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right thing to use here. */
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info->print_address_func (offset + pc
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+ info->bytes_per_chunk * 2, info);
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}
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}
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break;
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case 'c':
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func (stream, "%s", arm_conditional[cond]);
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break;
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