x86: Improve -malign-branch
According to intel SDM manual, not all compare flag-modifying instructions are marcro-fusible with subsequent jcc instructions. For those non-fusible instructions, -malign-branch doesn't need to align them, only jcc itself needs to be aligned. Here are 2 restrictions which separate macro-fusible instruction from not Restriction 1: If TEST/AND/CMP/ADD/SUB/INC/DEC is one of the following format: cmp m, imm add m, imm sub m, imm test m, imm and m, imm inc m dec m it is unfusible with any jcc instruction. Restriction 2: /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture Note it also works for Skylake and Cascadelake. --------------------------------------------------------------------- | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | ------ | ----------- | ------- | -------- | | Jo | N | N | Y | | Jno | N | N | Y | | Jc/Jb | Y | N | Y | | Jae/Jnb | Y | N | Y | | Je/Jz | Y | Y | Y | | Jne/Jnz | Y | Y | Y | | Jna/Jbe | Y | N | Y | | Ja/Jnbe | Y | N | Y | | Js | N | N | Y | | Jns | N | N | Y | | Jp/Jpe | N | N | Y | | Jnp/Jpo | N | N | Y | | Jl/Jnge | Y | Y | Y | | Jge/Jnl | Y | Y | Y | | Jle/Jng | Y | Y | Y | | Jg/Jnle | Y | Y | Y | Update maybe_fused_with_jcc_p to check if operands of CMP like instructions can be fused with condition jump. * gas/config/tc-i386.h (i386_tc_frag_data): Add member mf_type. (TC_FRAG_INIT): Init mf_type. * gas/config/tc-i386.c (enum mf_jcc_kind): New enum. (enum mf_cmp_kind): Ditto. (maybe_fused_with_jcc_p): Add argument mf_cmp_p to get mf_type of corresponding instructons, exclude unfusible instructions. (add_fused_jcc_padding_frag_p): Likewise. (add_branch_padding_frag_p): Likewise. (output_insn): Record mf_type for corresponding instructions. (i386_macro_fusible_p): New function. (i386_next_fusible_jcc_frag): Rename from i386_next_jcc_frag, add argument cmp_fragP to return next fusible jcc frag only. (i386_classify_machine_dependant_frag): Seperate macro-fusible instructions from condition jump. * gas/testsuite/gas/i386/align-branch-9.s: New file. * gas/testsuite/gas/i386/align-branch-9.d: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.s: Ditto. * gas/testsuite/gas/i386/x86-64-align-branch-9.d: Ditto. * gas/testsuite/gas/i386/i386.exp: Run new tests.
This commit is contained in:
Hongtao Liu
H.J. Lu
parent
bb7b70ab85
commit
79d72f45a7
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@ -687,6 +687,27 @@ static unsigned int align_branch = (align_branch_jcc_bit
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| align_branch_fused_bit
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| align_branch_jmp_bit);
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/* Types of condition jump used by macro-fusion. */
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enum mf_jcc_kind
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{
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mf_jcc_jo = 0, /* base opcode 0x70 */
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mf_jcc_jc, /* base opcode 0x72 */
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mf_jcc_je, /* base opcode 0x74 */
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mf_jcc_jna, /* base opcode 0x76 */
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mf_jcc_js, /* base opcode 0x78 */
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mf_jcc_jp, /* base opcode 0x7a */
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mf_jcc_jl, /* base opcode 0x7c */
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mf_jcc_jle, /* base opcode 0x7e */
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};
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/* Types of compare flag-modifying insntructions used by macro-fusion. */
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enum mf_cmp_kind
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{
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mf_cmp_test_and, /* test/cmp */
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mf_cmp_alu_cmp, /* add/sub/cmp */
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mf_cmp_incdec /* inc/dec */
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};
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/* The maximum padding size for fused jcc. CMP like instruction can
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be 9 bytes and jcc can be 6 bytes. Leave room just in case for
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prefixes. */
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@ -8374,10 +8395,22 @@ encoding_length (const fragS *start_frag, offsetT start_off,
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}
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/* Return 1 for test, and, cmp, add, sub, inc and dec which may
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be macro-fused with conditional jumps. */
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be macro-fused with conditional jumps.
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NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
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or is one of the following format:
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cmp m, imm
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add m, imm
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sub m, imm
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test m, imm
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and m, imm
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inc m
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dec m
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it is unfusible. */
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static int
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maybe_fused_with_jcc_p (void)
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maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
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{
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/* No RIP address. */
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if (i.base_reg && i.base_reg->reg_num == RegIP)
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@ -8387,36 +8420,54 @@ maybe_fused_with_jcc_p (void)
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if (is_any_vex_encoding (&i.tm))
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return 0;
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/* and, add, sub with destination register. */
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if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
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|| i.tm.base_opcode <= 5
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/* add, sub without add/sub m, imm. */
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if (i.tm.base_opcode <= 5
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|| (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
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|| ((i.tm.base_opcode | 3) == 0x83
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&& ((i.tm.extension_opcode | 1) == 0x5
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&& (i.tm.extension_opcode == 0x5
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|| i.tm.extension_opcode == 0x0)))
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return (i.types[1].bitfield.class == Reg
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|| i.types[1].bitfield.instance == Accum);
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{
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*mf_cmp_p = mf_cmp_alu_cmp;
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return !(i.mem_operands && i.imm_operands);
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}
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/* test, cmp with any register. */
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/* and without and m, imm. */
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if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
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|| ((i.tm.base_opcode | 3) == 0x83
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&& i.tm.extension_opcode == 0x4))
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{
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*mf_cmp_p = mf_cmp_test_and;
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return !(i.mem_operands && i.imm_operands);
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}
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/* test without test m imm. */
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if ((i.tm.base_opcode | 1) == 0x85
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|| (i.tm.base_opcode | 1) == 0xa9
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|| ((i.tm.base_opcode | 1) == 0xf7
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&& i.tm.extension_opcode == 0)
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|| (i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
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&& i.tm.extension_opcode == 0))
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{
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*mf_cmp_p = mf_cmp_test_and;
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return !(i.mem_operands && i.imm_operands);
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}
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/* cmp without cmp m, imm. */
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if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
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|| ((i.tm.base_opcode | 3) == 0x83
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&& (i.tm.extension_opcode == 0x7)))
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return (i.types[0].bitfield.class == Reg
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|| i.types[0].bitfield.instance == Accum
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|| i.types[1].bitfield.class == Reg
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|| i.types[1].bitfield.instance == Accum);
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{
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*mf_cmp_p = mf_cmp_alu_cmp;
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return !(i.mem_operands && i.imm_operands);
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}
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/* inc, dec with any register. */
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/* inc, dec without inc/dec m. */
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if ((i.tm.cpu_flags.bitfield.cpuno64
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&& (i.tm.base_opcode | 0xf) == 0x4f)
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|| ((i.tm.base_opcode | 1) == 0xff
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&& i.tm.extension_opcode <= 0x1))
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return (i.types[0].bitfield.class == Reg
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|| i.types[0].bitfield.instance == Accum);
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{
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*mf_cmp_p = mf_cmp_incdec;
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return !i.mem_operands;
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}
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return 0;
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}
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@ -8424,7 +8475,7 @@ maybe_fused_with_jcc_p (void)
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/* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
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static int
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add_fused_jcc_padding_frag_p (void)
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add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p)
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{
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/* NB: Don't work with COND_JUMP86 without i386. */
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if (!align_branch_power
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@ -8433,7 +8484,7 @@ add_fused_jcc_padding_frag_p (void)
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|| !(align_branch & align_branch_fused_bit))
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return 0;
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if (maybe_fused_with_jcc_p ())
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if (maybe_fused_with_jcc_p (mf_cmp_p))
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{
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if (last_insn.kind == last_insn_other
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|| last_insn.seg != now_seg)
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@ -8481,7 +8532,8 @@ add_branch_prefix_frag_p (void)
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/* Return 1 if a BRANCH_PADDING frag should be generated. */
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static int
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add_branch_padding_frag_p (enum align_branch_kind *branch_p)
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add_branch_padding_frag_p (enum align_branch_kind *branch_p,
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enum mf_jcc_kind *mf_jcc_p)
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{
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int add_padding;
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@ -8503,6 +8555,9 @@ add_branch_padding_frag_p (enum align_branch_kind *branch_p)
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}
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else
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{
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/* Because J<cc> and JN<cc> share same group in macro-fusible table,
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igore the lowest bit. */
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*mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
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*branch_p = align_branch_jcc;
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if ((align_branch & align_branch_jcc_bit))
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add_padding = 1;
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@ -8573,6 +8628,10 @@ output_insn (void)
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offsetT insn_start_off;
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fragS *fragP = NULL;
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enum align_branch_kind branch = align_branch_none;
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/* The initializer is arbitrary just to avoid uninitialized error.
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it's actually either assigned in add_branch_padding_frag_p
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or never be used. */
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enum mf_jcc_kind mf_jcc = mf_jcc_jo;
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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if (IS_ELF && x86_used_note)
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@ -8665,7 +8724,7 @@ output_insn (void)
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insn_start_frag = frag_now;
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insn_start_off = frag_now_fix ();
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if (add_branch_padding_frag_p (&branch))
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if (add_branch_padding_frag_p (&branch, &mf_jcc))
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{
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char *p;
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/* Branch can be 8 bytes. Leave some room for prefixes. */
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@ -8686,6 +8745,7 @@ output_insn (void)
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ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
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NULL, 0, p);
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fragP->tc_frag_data.mf_type = mf_jcc;
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fragP->tc_frag_data.branch_type = branch;
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fragP->tc_frag_data.max_bytes = max_branch_padding_size;
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}
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@ -8705,6 +8765,7 @@ output_insn (void)
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unsigned char *q;
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unsigned int j;
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unsigned int prefix;
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enum mf_cmp_kind mf_cmp;
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if (avoid_fence
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&& (i.tm.base_opcode == 0xfaee8
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@ -8731,7 +8792,7 @@ output_insn (void)
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if (branch)
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/* Skip if this is a branch. */
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;
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else if (add_fused_jcc_padding_frag_p ())
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else if (add_fused_jcc_padding_frag_p (&mf_cmp))
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{
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/* Make room for padding. */
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frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
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@ -8743,6 +8804,7 @@ output_insn (void)
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ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
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NULL, 0, p);
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fragP->tc_frag_data.mf_type = mf_cmp;
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fragP->tc_frag_data.branch_type = align_branch_fused;
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fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
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}
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@ -10948,6 +11010,42 @@ elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
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}
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#endif
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/* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
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Note also work for Skylake and Cascadelake.
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---------------------------------------------------------------------
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| JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
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| ------ | ----------- | ------- | -------- |
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| Jo | N | N | Y |
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| Jno | N | N | Y |
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| Jc/Jb | Y | N | Y |
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| Jae/Jnb | Y | N | Y |
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| Je/Jz | Y | Y | Y |
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| Jne/Jnz | Y | Y | Y |
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| Jna/Jbe | Y | N | Y |
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| Ja/Jnbe | Y | N | Y |
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| Js | N | N | Y |
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| Jns | N | N | Y |
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| Jp/Jpe | N | N | Y |
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| Jnp/Jpo | N | N | Y |
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| Jl/Jnge | Y | Y | Y |
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| Jge/Jnl | Y | Y | Y |
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| Jle/Jng | Y | Y | Y |
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| Jg/Jnle | Y | Y | Y |
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--------------------------------------------------------------------- */
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static int
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i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
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{
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if (mf_cmp == mf_cmp_alu_cmp)
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return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
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|| mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
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if (mf_cmp == mf_cmp_incdec)
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return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
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|| mf_jcc == mf_jcc_jle);
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if (mf_cmp == mf_cmp_test_and)
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return 1;
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return 0;
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}
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/* Return the next non-empty frag. */
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static fragS *
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@ -10967,20 +11065,23 @@ i386_next_non_empty_frag (fragS *fragP)
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/* Return the next jcc frag after BRANCH_PADDING. */
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static fragS *
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i386_next_jcc_frag (fragS *fragP)
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i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
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{
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if (!fragP)
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fragS *branch_fragP;
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if (!pad_fragP)
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return NULL;
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if (fragP->fr_type == rs_machine_dependent
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&& (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
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if (pad_fragP->fr_type == rs_machine_dependent
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&& (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
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== BRANCH_PADDING))
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{
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fragP = i386_next_non_empty_frag (fragP);
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if (fragP->fr_type != rs_machine_dependent)
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branch_fragP = i386_next_non_empty_frag (pad_fragP);
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if (branch_fragP->fr_type != rs_machine_dependent)
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return NULL;
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if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == COND_JUMP)
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return fragP;
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if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
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&& i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
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pad_fragP->tc_frag_data.mf_type))
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return branch_fragP;
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}
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return NULL;
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@ -11025,7 +11126,7 @@ i386_classify_machine_dependent_frag (fragS *fragP)
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*/
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cmp_fragP = i386_next_non_empty_frag (next_fragP);
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pad_fragP = i386_next_non_empty_frag (cmp_fragP);
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branch_fragP = i386_next_jcc_frag (pad_fragP);
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branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
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if (branch_fragP)
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{
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/* The BRANCH_PADDING frag is merged with the
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@ -273,6 +273,7 @@ struct i386_tc_frag_data
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unsigned char prefix_length;
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unsigned char default_prefix;
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unsigned char cmp_size;
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unsigned int mf_type : 3;
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unsigned int classified : 1;
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unsigned int branch_type : 3;
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};
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@ -299,6 +300,7 @@ struct i386_tc_frag_data
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(FRAGP)->tc_frag_data.cmp_size = 0; \
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(FRAGP)->tc_frag_data.classified = 0; \
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(FRAGP)->tc_frag_data.branch_type = 0; \
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(FRAGP)->tc_frag_data.mf_type = 0; \
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} \
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while (0)
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@ -0,0 +1,78 @@
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#as: -mbranches-within-32B-boundaries
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#objdump: -dw
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo>:
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0: 65 a3 01 00 00 00 mov %eax,%gs:0x1
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6: 55 push %ebp
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7: 55 push %ebp
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8: 55 push %ebp
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9: 55 push %ebp
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a: 89 e5 mov %esp,%ebp
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c: 89 7d f8 mov %edi,-0x8\(%ebp\)
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f: 89 75 f4 mov %esi,-0xc\(%ebp\)
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12: 89 75 f4 mov %esi,-0xc\(%ebp\)
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15: 89 75 f4 mov %esi,-0xc\(%ebp\)
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18: 89 75 f4 mov %esi,-0xc\(%ebp\)
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1b: 89 75 f4 mov %esi,-0xc\(%ebp\)
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1e: 39 c5 cmp %eax,%ebp
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20: 70 62 jo 84 <foo\+0x84>
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22: 89 73 f4 mov %esi,-0xc\(%ebx\)
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25: 89 75 f4 mov %esi,-0xc\(%ebp\)
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28: 89 7d f8 mov %edi,-0x8\(%ebp\)
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2b: 89 75 f4 mov %esi,-0xc\(%ebp\)
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2e: 89 75 f4 mov %esi,-0xc\(%ebp\)
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31: 89 75 f4 mov %esi,-0xc\(%ebp\)
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34: 89 75 f4 mov %esi,-0xc\(%ebp\)
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37: 89 75 f4 mov %esi,-0xc\(%ebp\)
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3a: 5d pop %ebp
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3b: 5d pop %ebp
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3c: 5d pop %ebp
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3d: 74 45 je 84 <foo\+0x84>
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3f: 5d pop %ebp
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40: 74 42 je 84 <foo\+0x84>
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42: 89 44 24 fc mov %eax,-0x4\(%esp\)
|
||||
46: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
49: 89 7d f8 mov %edi,-0x8\(%ebp\)
|
||||
4c: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
4f: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
52: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
55: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
58: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
5b: 5d pop %ebp
|
||||
5c: eb 2c jmp 8a <foo\+0x8a>
|
||||
5e: 66 90 xchg %ax,%ax
|
||||
60: eb 28 jmp 8a <foo\+0x8a>
|
||||
62: eb 26 jmp 8a <foo\+0x8a>
|
||||
64: 89 45 fc mov %eax,-0x4\(%ebp\)
|
||||
67: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
6a: 89 7d f8 mov %edi,-0x8\(%ebp\)
|
||||
6d: 5d pop %ebp
|
||||
6e: 5d pop %ebp
|
||||
6f: 40 inc %eax
|
||||
70: 72 12 jb 84 <foo\+0x84>
|
||||
72: 36 36 89 45 fc ss mov %eax,%ss:-0x4\(%ebp\)
|
||||
77: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
7a: 89 7d f8 mov %edi,-0x8\(%ebp\)
|
||||
7d: 89 75 f4 mov %esi,-0xc\(%ebp\)
|
||||
80: 21 c3 and %eax,%ebx
|
||||
82: 7c 06 jl 8a <foo\+0x8a>
|
||||
84: 8b 45 f4 mov -0xc\(%ebp\),%eax
|
||||
87: 89 45 fc mov %eax,-0x4\(%ebp\)
|
||||
8a: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
90: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
96: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
9c: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
a2: 89 75 0c mov %esi,0xc\(%ebp\)
|
||||
a5: e9 fc ff ff ff jmp a6 <foo\+0xa6>
|
||||
aa: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
b0: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
b6: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
bc: 89 b5 50 fb ff ff mov %esi,-0x4b0\(%ebp\)
|
||||
c2: 89 75 00 mov %esi,0x0\(%ebp\)
|
||||
c5: 74 c3 je 8a <foo\+0x8a>
|
||||
c7: 74 c1 je 8a <foo\+0x8a>
|
||||
#pass
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
.text
|
||||
.globl foo
|
||||
.p2align 4
|
||||
foo:
|
||||
movl %eax, %gs:0x1
|
||||
pushl %ebp
|
||||
pushl %ebp
|
||||
pushl %ebp
|
||||
pushl %ebp
|
||||
movl %esp, %ebp
|
||||
movl %edi, -8(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
cmp %eax, %ebp
|
||||
jo .L_2
|
||||
movl %esi, -12(%ebx)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %edi, -8(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
popl %ebp
|
||||
popl %ebp
|
||||
popl %ebp
|
||||
je .L_2
|
||||
popl %ebp
|
||||
je .L_2
|
||||
movl %eax, -4(%esp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %edi, -8(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
popl %ebp
|
||||
jmp .L_3
|
||||
jmp .L_3
|
||||
jmp .L_3
|
||||
movl %eax, -4(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %edi, -8(%ebp)
|
||||
popl %ebp
|
||||
popl %ebp
|
||||
inc %eax
|
||||
jc .L_2
|
||||
movl %eax, -4(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
movl %edi, -8(%ebp)
|
||||
movl %esi, -12(%ebp)
|
||||
and %eax, %ebx
|
||||
jl .L_3
|
||||
.L_2:
|
||||
movl -12(%ebp), %eax
|
||||
movl %eax, -4(%ebp)
|
||||
.L_3:
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, 12(%ebp)
|
||||
jmp bar
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, -1200(%ebp)
|
||||
movl %esi, (%ebp)
|
||||
je .L_3
|
||||
je .L_3
|
||||
|
|
@ -525,6 +525,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "align-branch-6"
|
||||
run_dump_test "align-branch-7"
|
||||
run_dump_test "align-branch-8"
|
||||
run_dump_test "align-branch-9"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
|
|
@ -1100,6 +1101,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-align-branch-6"
|
||||
run_dump_test "x86-64-align-branch-7"
|
||||
run_dump_test "x86-64-align-branch-8"
|
||||
run_dump_test "x86-64-align-branch-9"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
#as: -mbranches-within-32B-boundaries
|
||||
#objdump: -dw
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <foo>:
|
||||
0: c1 e9 02 shr \$0x2,%ecx
|
||||
3: c1 e9 02 shr \$0x2,%ecx
|
||||
6: c1 e9 02 shr \$0x2,%ecx
|
||||
9: 89 d1 mov %edx,%ecx
|
||||
b: 31 c0 xor %eax,%eax
|
||||
d: c1 e9 02 shr \$0x2,%ecx
|
||||
10: c1 e9 02 shr \$0x2,%ecx
|
||||
13: c1 e9 02 shr \$0x2,%ecx
|
||||
16: c1 e9 02 shr \$0x2,%ecx
|
||||
19: c1 e9 02 shr \$0x2,%ecx
|
||||
1c: c1 e9 02 shr \$0x2,%ecx
|
||||
1f: 80 fa 02 cmp \$0x2,%dl
|
||||
22: 70 df jo 3 <foo\+0x3>
|
||||
24: 2e 2e 2e 2e 31 c0 cs cs cs cs xor %eax,%eax
|
||||
2a: c1 e9 02 shr \$0x2,%ecx
|
||||
2d: c1 e9 02 shr \$0x2,%ecx
|
||||
30: c1 e9 02 shr \$0x2,%ecx
|
||||
33: 89 d1 mov %edx,%ecx
|
||||
35: 31 c0 xor %eax,%eax
|
||||
37: c1 e9 02 shr \$0x2,%ecx
|
||||
3a: c1 e9 02 shr \$0x2,%ecx
|
||||
3d: c1 e9 02 shr \$0x2,%ecx
|
||||
40: f6 c2 02 test \$0x2,%dl
|
||||
43: 75 e8 jne 2d <foo\+0x2d>
|
||||
45: 31 c0 xor %eax,%eax
|
||||
47: c1 e9 02 shr \$0x2,%ecx
|
||||
4a: c1 e9 02 shr \$0x2,%ecx
|
||||
4d: 89 d1 mov %edx,%ecx
|
||||
4f: c1 e9 02 shr \$0x2,%ecx
|
||||
52: c1 e9 02 shr \$0x2,%ecx
|
||||
55: 89 d1 mov %edx,%ecx
|
||||
57: c1 e9 02 shr \$0x2,%ecx
|
||||
5a: 89 d1 mov %edx,%ecx
|
||||
5c: 31 c0 xor %eax,%eax
|
||||
5e: ff c0 inc %eax
|
||||
60: 76 cb jbe 2d <foo\+0x2d>
|
||||
62: 31 c0 xor %eax,%eax
|
||||
#pass
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
.text
|
||||
.p2align 4,,15
|
||||
foo:
|
||||
shrl $2, %ecx
|
||||
.L1:
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
movl %edx, %ecx
|
||||
xorl %eax, %eax
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
cmpb $2, %dl
|
||||
jo .L1
|
||||
xorl %eax, %eax
|
||||
shrl $2, %ecx
|
||||
.L2:
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
movl %edx, %ecx
|
||||
xorl %eax, %eax
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
testb $2, %dl
|
||||
jne .L2
|
||||
xorl %eax, %eax
|
||||
.L3:
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
movl %edx, %ecx
|
||||
shrl $2, %ecx
|
||||
shrl $2, %ecx
|
||||
movl %edx, %ecx
|
||||
shrl $2, %ecx
|
||||
movl %edx, %ecx
|
||||
xorl %eax, %eax
|
||||
inc %eax
|
||||
jbe .L2
|
||||
xorl %eax, %eax
|
||||
Loading…
Reference in New Issue