Foixes for PR16116 and ER15940 - improve parallel insn handling.
This commit is contained in:
Nick Clifton
parent
f79ebb2c0f
commit
7a0f469b1c
@ -1,3 +1,13 @@
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Mon Jun 8 18:32:01 1998 Nick Clifton <nickc@cygnus.com>
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* config/tc-d30v.c (md_assemble): Fix handling of reverse
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sequential word multiply instructions.
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(do_assemble): Add extra command line argument, to allow mul32
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attribute to be preserved across parallel insns.
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(md_assemble): Insert NOPs between explicitly parallel insns which
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contain an 32 bit multiply and a 16 multiply.
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start-sanitize-sky
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Mon Jun 8 15:41:43 1998 Doug Evans <devans@canuck.cygnus.com>
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@ -111,7 +111,7 @@ static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, Fix
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static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1,
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struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx));
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static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode,
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int shortp));
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int shortp, int is_parallel));
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static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1,
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struct d30v_insn *opcode2, unsigned long insn2,
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exec_type_enum exec_type));
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@ -159,7 +159,7 @@ reg_name_search (name)
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int cmp;
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low = 0;
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high = reg_name_cnt() - 1;
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high = reg_name_cnt () - 1;
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do
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{
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@ -245,7 +245,7 @@ void
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md_show_usage (stream)
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FILE *stream;
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{
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fprintf(stream, _("\nD30V options:\n\
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fprintf (stream, _("\nD30V options:\n\
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-O Make adjacent short instructions parallel if possible.\n\
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-n Warn about all NOPs inserted by the assembler.\n\
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-N Warn about NOPs inserted after word multiplies.\n"));
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@ -352,7 +352,7 @@ void
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md_begin ()
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{
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struct d30v_opcode *opcode;
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d30v_hash = hash_new();
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d30v_hash = hash_new ();
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/* Insert opcode names into a hash table. */
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for (opcode = (struct d30v_opcode *)d30v_opcode_table; opcode->name; opcode++)
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@ -409,14 +409,14 @@ get_reloc (op, rel_flag)
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break;
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case 12:
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if (!(op->flags & OPERAND_SHIFT))
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as_warn(_("unexpected 12-bit reloc type"));
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as_warn (_("unexpected 12-bit reloc type"));
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if (rel_flag == RELOC_PCREL)
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return BFD_RELOC_D30V_15_PCREL;
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else
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return BFD_RELOC_D30V_15;
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case 18:
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if (!(op->flags & OPERAND_SHIFT))
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as_warn(_("unexpected 18-bit reloc type"));
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as_warn (_("unexpected 18-bit reloc type"));
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if (rel_flag == RELOC_PCREL)
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return BFD_RELOC_D30V_21_PCREL;
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else
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@ -585,7 +585,7 @@ build_insn (opcode, opers)
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as_fatal (_("too many fixups"));
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fixups->fix[fixups->fc].reloc =
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get_reloc((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag);
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get_reloc ((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag);
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fixups->fix[fixups->fc].size = 4;
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fixups->fix[fixups->fc].exp = opers[i];
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fixups->fix[fixups->fc].operand = form->operands[i];
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@ -598,7 +598,7 @@ build_insn (opcode, opers)
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/* truncate to the proper number of bits */
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if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
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as_bad(_("operand out of range: %d"),number);
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as_bad (_("operand out of range: %d"),number);
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if (bits < 31)
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number &= 0x7FFFFFFF >> (31 - bits);
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if (flags & OPERAND_SHIFT)
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@ -626,7 +626,7 @@ write_long (opcode, insn, fx)
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Fixups *fx;
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{
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int i, where;
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char *f = frag_more(8);
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char *f = frag_more (8);
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insn |= FM11;
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d30v_number_to_chars (f, insn, 8);
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@ -655,7 +655,7 @@ write_1_short (opcode, insn, fx)
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long long insn;
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Fixups *fx;
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{
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char *f = frag_more(8);
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char *f = frag_more (8);
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int i, where;
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if (warn_nops == NOP_ALL)
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@ -700,7 +700,7 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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char *f;
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int i,j, where;
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if(exec_type != EXEC_PARALLEL &&
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if (exec_type != EXEC_PARALLEL &&
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((opcode1->op->flags_used & (FLAG_JSR | FLAG_DELAY)) == FLAG_JSR))
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{
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/* subroutines must be called from 32-bit boundaries */
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@ -782,11 +782,11 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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break;
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default:
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as_fatal(_("unknown execution type passed to write_2_short()"));
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as_fatal (_("unknown execution type passed to write_2_short()"));
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}
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/* printf("writing out %llx\n",insn); */
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f = frag_more(8);
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f = frag_more (8);
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d30v_number_to_chars (f, insn, 8);
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/* If the previous instruction was a 32-bit multiply but it is put into a
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@ -1030,7 +1030,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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mod_reg[0][2] = mod_reg[1][2] = 0;
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}
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for(j = 0; j < 3; j++)
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for (j = 0; j < 3; j++)
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{
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/* If the second instruction depends on the first, we obviously
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cannot parallelize. Note, the mod flag implies use, so
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@ -1078,7 +1078,7 @@ md_assemble (str)
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if ((prev_insn != -1) && prev_seg
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&& ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
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d30v_cleanup();
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d30v_cleanup ();
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if (d30v_current_align < 3)
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d30v_align (3, NULL, d30v_last_label);
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@ -1116,10 +1116,10 @@ md_assemble (str)
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/* if two instructions are present and we already have one saved
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then first write it out */
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d30v_cleanup();
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d30v_cleanup ();
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/* assemble first instruction and save it */
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prev_insn = do_assemble (str, &prev_opcode, 1);
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prev_insn = do_assemble (str, &prev_opcode, 1, 0);
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if (prev_insn == -1)
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as_fatal (_("Cannot assemble instruction"));
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if (prev_opcode.form->form >= LONG)
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@ -1132,7 +1132,8 @@ md_assemble (str)
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}
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insn = do_assemble (str, &opcode,
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(extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN));
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(extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
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extype == EXEC_PARALLEL);
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if (insn == -1)
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{
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if (extype != EXEC_UNKNOWN)
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@ -1151,11 +1152,12 @@ md_assemble (str)
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/* Word multiply instructions must not be followed by either a load or a
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16-bit multiply instruction in the next cycle. */
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if (prev_mul32_p && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
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if ( (extype != EXEC_REVSEQ)
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&& prev_mul32_p
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&& (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
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{
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/* However, load and multiply should able to be combined in a parallel
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operation, so check for that first. */
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if (prev_insn != -1
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&& (opcode.op->flags_used & FLAG_MEM)
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&& opcode.form->form < LONG
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@ -1169,14 +1171,47 @@ md_assemble (str)
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prev_insn = -1;
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return;
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}
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/* Can't parallelize, flush current instruction and emit a word of NOPS */
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else
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{
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char *f;
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d30v_cleanup();
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/* Can't parallelize, flush previous instruction and emit a word of NOPS,
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unless the previous instruction is a NOP, in whcih case just flush it,
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as this will generate a word of NOPs for us. */
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f = frag_more(8);
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if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
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{
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d30v_cleanup ();
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}
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else
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{
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char * f;
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d30v_cleanup ();
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f = frag_more (8);
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d30v_number_to_chars (f, NOP2, 8);
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if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
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{
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if (opcode.op->flags_used & FLAG_MEM)
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as_warn (_("word of NOPs added between word multiply and load"));
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else
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as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
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}
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}
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extype = EXEC_UNKNOWN;
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}
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}
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else if ( (extype == EXEC_REVSEQ)
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&& cur_mul32_p
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&& (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
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{
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/* Can't parallelize, flush current instruction and emit a word of NOPS */
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write_1_short (& opcode, (long) insn, fixups->next->next);
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if (strcmp (opcode.op->name, "nop") != 0)
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{
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char * f;
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f = frag_more (8);
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d30v_number_to_chars (f, NOP2, 8);
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if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
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{
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@ -1185,34 +1220,40 @@ md_assemble (str)
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else
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as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
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}
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extype = EXEC_UNKNOWN;
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}
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/* Make the previous instruction the current one. */
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extype = EXEC_UNKNOWN;
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insn = prev_insn;
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now_seg = prev_seg;
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now_subseg = prev_subseg;
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prev_insn = -1;
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cur_mul32_p = prev_mul32_p;
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prev_mul32_p = 0;
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}
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/* if this is a long instruction, write it and any previous short instruction */
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/* If this is a long instruction, write it and any previous short instruction. */
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if (opcode.form->form >= LONG)
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{
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if (extype)
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as_fatal(_("Unable to mix instructions as specified"));
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d30v_cleanup();
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if (extype != EXEC_UNKNOWN)
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as_fatal (_("Unable to mix instructions as specified"));
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d30v_cleanup ();
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write_long (&opcode, insn, fixups);
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prev_insn = -1;
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return;
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}
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if ((prev_insn != -1) &&
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else if ((prev_insn != -1) &&
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(write_2_short (&prev_opcode, (long)prev_insn, &opcode, (long)insn, extype, fixups) == 0))
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{
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/* no instructions saved */
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/* No instructions saved. */
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prev_insn = -1;
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}
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else
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{
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if (extype)
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as_fatal(_("Unable to mix instructions as specified"));
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/* save off last instruction so it may be packed on next pass */
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memcpy(&prev_opcode, &opcode, sizeof(prev_opcode));
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if (extype != EXEC_UNKNOWN)
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as_fatal (_("Unable to mix instructions as specified"));
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/* Save off last instruction so it may be packed on next pass. */
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memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
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prev_insn = insn;
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prev_seg = now_seg;
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prev_subseg = now_subseg;
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@ -1225,10 +1266,11 @@ md_assemble (str)
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/* it returns -1 (an invalid opcode) on error */
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static long long
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do_assemble (str, opcode, shortp)
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do_assemble (str, opcode, shortp, is_parallel)
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char *str;
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struct d30v_insn *opcode;
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int shortp;
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int is_parallel;
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{
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unsigned char *op_start, *save;
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unsigned char *op_end;
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@ -1249,7 +1291,7 @@ do_assemble (str, opcode, shortp)
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&& !is_end_of_line[*op_end] && *op_end != ' ';
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op_end++)
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{
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name[nlen] = tolower(op_start[nlen]);
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name[nlen] = tolower (op_start[nlen]);
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nlen++;
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}
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@ -1262,13 +1304,13 @@ do_assemble (str, opcode, shortp)
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if (*op_end == '/')
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{
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int i = 0;
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while ( (i < ECC_MAX) && strncasecmp(d30v_ecc_names[i],op_end+1,2))
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while ( (i < ECC_MAX) && strncasecmp (d30v_ecc_names[i],op_end+1,2))
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i++;
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if (i == ECC_MAX)
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{
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char tmp[4];
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strncpy(tmp,op_end+1,2);
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strncpy (tmp,op_end+1,2);
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tmp[2] = 0;
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as_fatal (_("unknown condition code: %s"),tmp);
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return -1;
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@ -1282,7 +1324,7 @@ do_assemble (str, opcode, shortp)
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/* CMP and CMPU change their name based on condition codes */
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if (!strncmp(name,"cmp",3))
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if (!strncmp (name,"cmp",3))
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{
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int p,i;
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char **str = (char **)d30v_cc_names;
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@ -1291,7 +1333,7 @@ do_assemble (str, opcode, shortp)
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else
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p = 3;
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for(i=1; *str && strncmp(*str,&name[p],2); i++, str++)
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for (i=1; *str && strncmp (*str,&name[p],2); i++, str++)
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;
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/* cmpu only supports some condition codes */
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@ -1336,14 +1378,14 @@ do_assemble (str, opcode, shortp)
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/* find the first opcode with the proper name */
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opcode->op = (struct d30v_opcode *)hash_find (d30v_hash, name);
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if (opcode->op == NULL)
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as_fatal (_("unknown opcode: %s"),name);
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as_fatal (_("unknown opcode: %s"),name);
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save = input_line_pointer;
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input_line_pointer = op_end;
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while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
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{
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opcode->op++;
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if (strcmp(opcode->op->name,name))
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if (strcmp (opcode->op->name,name))
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as_fatal (_("operands for opcode `%s' do not match any valid format"), name);
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}
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input_line_pointer = save;
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@ -1353,8 +1395,13 @@ do_assemble (str, opcode, shortp)
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/* Propigate multiply status */
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if (insn != -1)
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{
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prev_mul32_p = cur_mul32_p;
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cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
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if (is_parallel && prev_mul32_p)
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cur_mul32_p = 1;
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else
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{
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prev_mul32_p = cur_mul32_p;
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cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
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}
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}
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return (insn);
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@ -1460,8 +1507,8 @@ find_format (opcode, myops, fsize, cmp_hack)
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match = 0;
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}
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else if (X_op == O_symbol
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&& S_IS_DEFINED(myops[j].X_add_symbol)
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&& S_GET_SEGMENT(myops[j].X_add_symbol) == now_seg
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&& S_IS_DEFINED (myops[j].X_add_symbol)
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&& S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
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&& opcode->reloc_flag == RELOC_PCREL)
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{
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/* If the symbol is defined, see if the value will fit
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@ -1474,8 +1521,8 @@ find_format (opcode, myops, fsize, cmp_hack)
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value = 0;
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for (f = frchain_now->frch_root; f; f = f->fr_next)
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value += f->fr_fix + f->fr_offset;
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value = (S_GET_VALUE(myops[j].X_add_symbol) - value
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- (obstack_next_free(&frchain_now->frch_obstack)
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value = (S_GET_VALUE (myops[j].X_add_symbol) - value
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- (obstack_next_free (&frchain_now->frch_obstack)
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- frag_now->fr_literal));
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if (check_range (value, bits, flags))
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match = 0;
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@ -1709,15 +1756,15 @@ d30v_number_to_chars (buf, value, n)
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/* then write out any unwritten instructions */
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void
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d30v_start_line()
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d30v_start_line ()
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{
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char *c = input_line_pointer;
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while(isspace(*c))
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while (isspace (*c))
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c++;
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if (*c == '.')
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d30v_cleanup();
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if (*c == '.')
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d30v_cleanup ();
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}
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static void
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@ -1749,7 +1796,7 @@ d30v_frob_label (lab)
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symbolS *lab;
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{
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/* Emit any pending instructions. */
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d30v_cleanup();
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||||
d30v_cleanup ();
|
||||
|
||||
/* Update the label's address with the current output pointer. */
|
||||
lab->sy_frag = frag_now;
|
||||
@ -1797,7 +1844,7 @@ d30v_align (n, pfill, label)
|
||||
if (d30v_current_align >= n && !switched_seg_p)
|
||||
return;
|
||||
|
||||
d30v_cleanup();
|
||||
d30v_cleanup ();
|
||||
|
||||
if (pfill == NULL)
|
||||
{
|
||||
@ -1833,7 +1880,7 @@ d30v_align (n, pfill, label)
|
||||
|
||||
old_frag = label->sy_frag;
|
||||
old_value = S_GET_VALUE (label);
|
||||
new_value = (valueT) frag_now_fix();
|
||||
new_value = (valueT) frag_now_fix ();
|
||||
|
||||
/* It is possible to have more than one label at a particular
|
||||
address, especially if debugging is enabled, so we must
|
||||
@ -1859,7 +1906,7 @@ d30v_align (n, pfill, label)
|
||||
}
|
||||
}
|
||||
|
||||
record_alignment(now_seg, n);
|
||||
record_alignment (now_seg, n);
|
||||
}
|
||||
|
||||
/* Handle the .align pseudo-op. This aligns to a power of two. We
|
||||
|
||||
Loading…
Reference in New Issue
Block a user