[AArch64] Fix +sve documentation
The documentation entry for the SVE feature incorrectly said that it was enabled by default for ARMv8-A or later. This patch fixes that and also mentions that +sve implies +simd. (It also implies +fp, but that follows by transitivity.) gas/ * doc/c-aarch64.texi: Fix sve entry.
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@ -1,3 +1,7 @@
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2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
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* doc/c-aarch64.texi: Fix sve entry.
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2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
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* config/tc-arc.c (md_convert_frag): Remove @pcl relocation
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@ -155,8 +155,8 @@ automatically cause those extensions to be disabled.
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@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable Advanced SIMD extensions. This implies @code{fp}.
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@item @code{sve} @tab ARMv8-A @tab ARMv8-A or later
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@tab Enable the Scalable Vector Extensions.
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@item @code{sve} @tab ARMv8-A @tab No
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@tab Enable the Scalable Vector Extensions. This implies @code{simd}.
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@end multitable
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@node AArch64 Syntax
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