* config/m88k/tm-m88k.h: white space and comment changes. include
ieee-float.h. expanded to cope with m88110 extended registers. (R0_REGNUM, XFP_REGNUM, X0_REGNUM): new macros. (SHIFT_INST_REGS): becomes a real macro.
This commit is contained in:
K. Richard Pixley
parent
804506f6e8
commit
7b11cf9684
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@ -18,8 +18,11 @@ You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "ieee-float.h"
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/* g++ support is not yet included. */
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/* Define the bit, byte, and word ordering of the machine. */
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#define TARGET_BYTE_ORDER BIG_ENDIAN
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/* We cache information about saved registers in the frame structure,
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@ -106,76 +109,110 @@ extern CORE_ADDR skip_prologue ();
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/* Number of machine registers */
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#define NUM_REGS 38
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#define GP_REGS (38)
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#define FP_REGS (32)
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#define NUM_REGS (GP_REGS + FP_REGS)
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/* Initializer for an array of names of registers.
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There should be NUM_REGS strings in this initializer. */
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#define REGISTER_NAMES {\
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"r0",\
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"r1",\
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"r2",\
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"r3",\
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"r4",\
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"r5",\
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"r6",\
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"r7",\
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"r8",\
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"r9",\
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"r10",\
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"r11",\
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"r12",\
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"r13",\
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"r14",\
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"r15",\
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"r16",\
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"r17",\
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"r18",\
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"r19",\
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"r20",\
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"r21",\
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"r22",\
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"r23",\
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"r24",\
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"r25",\
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"r26",\
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"r27",\
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"r28",\
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"r29",\
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"r30",\
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"r31",\
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"psr",\
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"fpsr",\
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"fpcr",\
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"sxip",\
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"snip",\
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"sfip",\
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"vbr",\
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"dmt0",\
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"dmd0",\
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"dma0",\
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"dmt1",\
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"dmd1",\
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"dma1",\
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"dmt2",\
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"dmd2",\
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"dma2",\
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"sr0",\
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"sr1",\
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"sr2",\
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"sr3",\
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"fpecr",\
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"fphs1",\
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"fpls1",\
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"fphs2",\
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"fpls2",\
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"fppt",\
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"fprh",\
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"fprl",\
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"fpit",\
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"fpsr",\
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"fpcr",\
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}
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"r0",\
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"r1",\
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"r2",\
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"r3",\
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"r4",\
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"r5",\
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"r6",\
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"r7",\
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"r8",\
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"r9",\
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"r10",\
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"r11",\
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"r12",\
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"r13",\
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"r14",\
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"r15",\
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"r16",\
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"r17",\
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"r18",\
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"r19",\
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"r20",\
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"r21",\
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"r22",\
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"r23",\
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"r24",\
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"r25",\
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"r26",\
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"r27",\
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"r28",\
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"r29",\
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"r30",\
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"r31",\
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"psr",\
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"fpsr",\
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"fpcr",\
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"sxip",\
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"snip",\
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"sfip",\
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"x0",\
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"x1",\
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"x2",\
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"x3",\
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"x4",\
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"x5",\
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"x6",\
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"x7",\
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"x8",\
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"x9",\
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"x10",\
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"x11",\
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"x12",\
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"x13",\
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"x14",\
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"x15",\
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"x16",\
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"x17",\
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"x18",\
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"x19",\
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"x20",\
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"x21",\
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"x22",\
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"x23",\
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"x24",\
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"x25",\
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"x26",\
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"x27",\
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"x28",\
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"x29",\
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"x30",\
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"x31",\
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"vbr",\
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"dmt0",\
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"dmd0",\
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"dma0",\
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"dmt1",\
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"dmd1",\
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"dma1",\
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"dmt2",\
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"dmd2",\
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"dma2",\
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"sr0",\
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"sr1",\
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"sr2",\
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"sr3",\
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"fpecr",\
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"fphs1",\
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"fpls1",\
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"fphs2",\
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"fpls2",\
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"fppt",\
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"fprh",\
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"fprl",\
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"fpit",\
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"fpsr",\
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"fpcr",\
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}
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/* Register numbers of various important registers.
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@ -185,19 +222,64 @@ extern CORE_ADDR skip_prologue ();
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to be actual register numbers as far as the user is concerned
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but do serve to get the desired values when passed to read_register. */
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#define R0_REGNUM 0 /* Contains the constant zero */
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#define SRP_REGNUM 1 /* Contains subroutine return pointer */
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#define RV_REGNUM 2 /* Contains simple return values */
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#define SRA_REGNUM 12 /* Contains address of struct return values */
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#define SP_REGNUM 31 /* Contains address of top of stack */
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#define SXIP_REGNUM 35 /* Contains Shadow Execute Instruction Pointer */
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#define SNIP_REGNUM 36 /* Contains Shadow Next Instruction Pointer */
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/* Instruction pointer notes...
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On the m88100:
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* cr04 = sxip. On exception, contains the excepting pc (probably).
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On rte, is ignored.
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* cr05 = snip. On exception, contains the NPC (next pc). On rte,
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pc is loaded from here.
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* cr06 = sfip. On exception, contains the NNPC (next next pc). On
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rte, the NPC is loaded from here.
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* lower two bits of each are flag bits. Bit 1 is V means address
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is valid. If address is not valid, bit 0 is ignored. Otherwise,
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bit 0 is E and asks for an exception to be taken if this
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instruction is executed.
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On the m88110:
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* cr04 = exip. On exception, contains the address of the excepting
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pc (always). On rte, pc is loaded from here. Bit 0, aka the D
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bit, is a flag saying that the offending instruction was in a
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branch delay slot. If set, then cr05 contains the NPC.
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* cr05 = enip. On exception, if the instruction pointed to by cr04
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was in a delay slot as indicated by the bit 0 of cr04, aka the D
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bit, the cr05 contains the NPC. Otherwise ignored.
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* cr06 is invalid */
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#define SXIP_REGNUM 35 /* On m88100, Contains Shadow Execute
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Instruction Pointer. */
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#define SNIP_REGNUM 36 /* On m88100, Contains Shadow Next
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Instruction Pointer. */
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#define SFIP_REGNUM 37 /* On m88100, Contains Shadow Fetched
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Intruction pointer. */
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#define EXIP_REGNUM 35 /* On m88110, Contains Exception
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Executing Instruction Pointer. */
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#define ENIP_REGNUM 36 /* On m88110, Contains the Exception
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Next Instruction Pointer. */
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#define PC_REGNUM SXIP_REGNUM /* Program Counter */
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#define NPC_REGNUM SNIP_REGNUM /* Next Program Counter */
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#define NNPC_REGNUM SFIP_REGNUM /* Next Next Program Counter */
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#define PSR_REGNUM 32 /* Processor Status Register */
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#define FPSR_REGNUM 33 /* Floating Point Status Register */
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#define FPCR_REGNUM 34 /* Floating Point Control Register */
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#define SFIP_REGNUM 37 /* Contains Shadow Fetched Intruction pointer */
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#define NNPC_REGNUM SFIP_REGNUM /* Next Next Program Counter */
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#define XFP_REGNUM 38 /* First Extended Float Register */
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#define X0_REGNUM XFP_REGNUM /* Which also contains the constant zero */
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/* This is rather a confusing lie. Our m88k port using a stack pointer value
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for the frame address. Hence, the frame address and the frame pointer are
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@ -220,75 +302,122 @@ extern CORE_ADDR skip_prologue ();
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#define PSR_IND 0x00000002
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#define PSR_SFRZ 0x00000001
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/* BCS requires that the SXIP_REGNUM (or PC_REGNUM) contain the address
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of the next instr to be executed when a breakpoint occurs. Because
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the kernel gets the next instr (SNIP_REGNUM), the instr in SNIP needs
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to be put back into SFIP, and the instr in SXIP should be shifted
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to SNIP */
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/* Are you sitting down? It turns out that the 88K BCS (binary compatibility
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standard) folks originally felt that the debugger should be responsible
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for backing up the IPs, not the kernel (as is usually done). Well, they
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have reversed their decision, and in future releases our kernel will be
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handling the backing up of the IPs. So, eventually, we won't need to
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do the SHIFT_INST_REGS stuff. But, for now, since there are 88K systems out
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there that do need the debugger to do the IP shifting, and since there
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will be systems where the kernel does the shifting, the code is a little
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more complex than perhaps it needs to be (we still go inside SHIFT_INST_REGS,
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and if the shifting hasn't occurred then gdb goes ahead and shifts). */
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#define SHIFT_INST_REGS
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/* The following two comments come from the days prior to the m88110
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port. The m88110 handles the instruction pointers differently. I
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do not know what any m88110 kernels do as the m88110 port I'm
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working with is for an embedded system. rich@cygnus.com
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13-sept-93. */
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/* Number of bytes of storage in the actual machine representation
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for register N. */
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/* BCS requires that the SXIP_REGNUM (or PC_REGNUM) contain the
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address of the next instr to be executed when a breakpoint occurs.
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Because the kernel gets the next instr (SNIP_REGNUM), the instr in
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SNIP needs to be put back into SFIP, and the instr in SXIP should
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be shifted to SNIP */
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#define REGISTER_RAW_SIZE(N) 4
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/* Are you sitting down? It turns out that the 88K BCS (binary
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compatibility standard) folks originally felt that the debugger
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should be responsible for backing up the IPs, not the kernel (as is
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usually done). Well, they have reversed their decision, and in
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future releases our kernel will be handling the backing up of the
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IPs. So, eventually, we won't need to do the SHIFT_INST_REGS
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stuff. But, for now, since there are 88K systems out there that do
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need the debugger to do the IP shifting, and since there will be
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systems where the kernel does the shifting, the code is a little
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more complex than perhaps it needs to be (we still go inside
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SHIFT_INST_REGS, and if the shifting hasn't occurred then gdb goes
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ahead and shifts). */
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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extern int target_is_m88110;
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#define SHIFT_INST_REGS() \
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if (!target_is_m88110) \
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{ \
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CORE_ADDR pc = read_register (PC_REGNUM); \
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CORE_ADDR npc = read_register (NPC_REGNUM); \
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if (pc != npc) \
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{ \
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write_register (NNPC_REGNUM, npc); \
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write_register (NPC_REGNUM, pc); \
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} \
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}
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#define REGISTER_BYTES (NUM_REGS * REGISTER_RAW_SIZE(0))
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/* Storing the following registers is a no-op. */
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#define CANNOT_STORE_REGISTER(regno) (((regno) == R0_REGNUM) \
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|| ((regno) == X0_REGNUM))
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/* Index within `registers' of the first byte of the space for
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register N. */
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/* Number of bytes of storage in the actual machine representation
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for register N. On the m88k, the general purpose registers are 4
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bytes and the 88110 extended registers are 10 bytes. */
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#define REGISTER_BYTE(N) ((N)*REGISTER_RAW_SIZE(0))
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#define REGISTER_RAW_SIZE(N) ((N) < XFP_REGNUM ? 4 : 10)
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/* Number of bytes of storage in the program's representation
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for register N. */
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/* Total amount of space needed to store our copies of the machine's
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register state, the array `registers'. */
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#define REGISTER_VIRTUAL_SIZE(N) (REGISTER_RAW_SIZE(N))
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#define REGISTER_BYTES ((GP_REGS * REGISTER_RAW_SIZE(0)) \
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+ (FP_REGS * REGISTER_RAW_SIZE(XFP_REGNUM)))
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/* Largest value REGISTER_RAW_SIZE can have. */
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/* Index within `registers' of the first byte of the space for
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register N. */
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#define MAX_REGISTER_RAW_SIZE (REGISTER_RAW_SIZE(0))
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#define REGISTER_BYTE(N) (((N) * REGISTER_RAW_SIZE(0)) \
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+ ((N) >= XFP_REGNUM \
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? (((N) - XFP_REGNUM) \
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* REGISTER_RAW_SIZE(XFP_REGNUM)) \
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: 0))
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/* Largest value REGISTER_VIRTUAL_SIZE can have.
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Are FPS1, FPS2, FPR "virtual" regisers? */
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/* Number of bytes of storage in the program's representation for
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register N. On the m88k, all registers are 4 bytes excepting the
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m88110 extended registers which are 8 byte doubles. */
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#define MAX_REGISTER_VIRTUAL_SIZE (REGISTER_RAW_SIZE(0))
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#define REGISTER_VIRTUAL_SIZE(N) ((N) < XFP_REGNUM ? 4 : 8)
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/* Nonzero if register N requires conversion
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from raw format to virtual format. */
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/* Largest value REGISTER_RAW_SIZE can have. */
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#define REGISTER_CONVERTIBLE(N) (0)
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#define MAX_REGISTER_RAW_SIZE (REGISTER_RAW_SIZE(XFP_REGNUM))
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/* Convert data from raw format for register REGNUM
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to virtual format for register REGNUM. */
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/* Largest value REGISTER_VIRTUAL_SIZE can have.
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Are FPS1, FPS2, FPR "virtual" regisers? */
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#define MAX_REGISTER_VIRTUAL_SIZE (REGISTER_RAW_SIZE(XFP_REGNUM))
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/* Nonzero if register N requires conversion
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from raw format to virtual format. */
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#define REGISTER_CONVERTIBLE(N) ((N) >= XFP_REGNUM)
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/* Convert data from raw format for register REGNUM
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to virtual format for register REGNUM. */
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extern const struct ext_format ext_format_m88110;
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#define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,FROM,TO) \
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{memcpy ((TO), (FROM), REGISTER_RAW_SIZE (REGNUM));}
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{ \
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if ((REGNUM) < XFP_REGNUM) \
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memcpy ((TO), (FROM), REGISTER_RAW_SIZE (REGNUM)); \
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else ieee_extended_to_double(&ext_format_m88110, \
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(FROM), (double *)(TO)); \
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}
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/* Convert data from virtual format for register REGNUM
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to raw format for register REGNUM. */
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#define REGISTER_CONVERT_TO_RAW(REGNUM,FROM,TO) \
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{memcpy ((TO), (FROM), REGISTER_RAW_SIZE (REGNUM));}
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{ \
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if ((REGNUM) < XFP_REGNUM) \
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memcpy ((TO), (FROM), REGISTER_RAW_SIZE (REGNUM)); \
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else double_to_ieee_extended (&ext_format_m88110, \
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(double *)(FROM), (TO)); \
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}
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/* Return the GDB type object for the "standard" data type
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of data in register N. */
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#define REGISTER_VIRTUAL_TYPE(N) (builtin_type_int)
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#define REGISTER_VIRTUAL_TYPE(N) \
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((N) >= XFP_REGNUM \
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? builtin_type_double \
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: ((N) == PC_REGNUM || (N) == FP_REGNUM || (N) == SP_REGNUM \
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? lookup_pointer_type (builtin_type_void) : builtin_type_int))
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/* The 88k call/return conventions call for "small" values to be returned
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into consecutive registers starting from r2. */
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