gdbserver: remove support for CRIS
This port has been unmaintained for years and the upstream Linux kernel does not support this architecture anymore, remove it. gdbserver/ChangeLog: * Makefile.in (SFILES): Remove linux-cris-low.c. * configure.srv: Remove cris cases. * linux-cris-low.cc, linux-crisv32-low.cc: Remove. Change-Id: Ib3ff436b03373548215f15540a47f39cbec5f512
This commit is contained in:
Simon Marchi
parent
1fa29f56ba
commit
7b46bf6f83
@ -1,3 +1,9 @@
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2020-06-12 Simon Marchi <simon.marchi@efficios.com>
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* Makefile.in (SFILES): Remove linux-cris-low.c.
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* configure.srv: Remove cris cases.
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* linux-cris-low.cc, linux-crisv32-low.cc: Remove.
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2020-06-12 Simon Marchi <simon.marchi@efficios.com>
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* Makefile.in (SFILES): Remove linux-bfin-low.c.
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@ -180,8 +180,6 @@ SFILES = \
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$(srcdir)/inferiors.cc \
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$(srcdir)/linux-aarch64-low.cc \
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$(srcdir)/linux-arm-low.cc \
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$(srcdir)/linux-cris-low.cc \
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$(srcdir)/linux-crisv32-low.cc \
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$(srcdir)/linux-ia64-low.cc \
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$(srcdir)/linux-low.cc \
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$(srcdir)/linux-m32r-low.cc \
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@ -81,16 +81,6 @@ case "${gdbserver_host}" in
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srv_mingw=yes
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srv_mingwce=yes
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;;
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crisv32-*-linux*) srv_regobj=reg-crisv32.o
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srv_tgtobj="$srv_linux_obj linux-crisv32-low.o"
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srv_linux_regsets=yes
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srv_linux_thread_db=yes
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;;
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cris-*-linux*) srv_regobj=reg-cris.o
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srv_tgtobj="$srv_linux_obj linux-cris-low.o"
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srv_linux_usrregs=yes
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srv_linux_thread_db=yes
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;;
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i[34567]86-*-cygwin*) srv_regobj=""
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srv_tgtobj="x86-low.o nat/x86-dregs.o win32-low.o"
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srv_tgtobj="${srv_tgtobj} win32-i386-low.o"
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@ -1,169 +0,0 @@
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/* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
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Copyright (C) 1995-2020 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include "nat/gdb_ptrace.h"
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/* Linux target op definitions for the CRIS architecture. */
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class cris_target : public linux_process_target
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{
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public:
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const regs_info *get_regs_info () override;
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const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
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protected:
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void low_arch_setup () override;
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bool low_cannot_fetch_register (int regno) override;
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bool low_cannot_store_register (int regno) override;
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bool low_supports_breakpoints () override;
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CORE_ADDR low_get_pc (regcache *regcache) override;
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void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
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bool low_breakpoint_at (CORE_ADDR pc) override;
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};
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/* The singleton target ops object. */
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static cris_target the_cris_target;
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bool
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cris_target::low_supports_breakpoints ()
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{
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return true;
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}
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CORE_ADDR
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cris_target::low_get_pc (regcache *regcache)
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{
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return linux_get_pc_32bit (regcache);
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}
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void
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cris_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
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{
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linux_set_pc_32bit (regcache, pc);
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}
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/* Defined in auto-generated file reg-cris.c. */
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void init_registers_cris (void);
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extern const struct target_desc *tdesc_cris;
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/* CRISv10 */
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#define cris_num_regs 32
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/* Locations need to match <include/asm/arch/ptrace.h>. */
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static int cris_regmap[] = {
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15*4, 14*4, 13*4, 12*4,
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11*4, 10*4, 9*4, 8*4,
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7*4, 6*4, 5*4, 4*4,
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3*4, 2*4, 23*4, 19*4,
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-1, -1, -1, -1,
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-1, 17*4, -1, 16*4,
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-1, -1, -1, 18*4,
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-1, 17*4, -1, -1
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};
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bool
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cris_target::low_cannot_store_register (int regno)
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{
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if (cris_regmap[regno] == -1)
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return true;
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return (regno >= cris_num_regs);
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}
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bool
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cris_target::low_cannot_fetch_register (int regno)
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{
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if (cris_regmap[regno] == -1)
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return true;
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return (regno >= cris_num_regs);
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}
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static const unsigned short cris_breakpoint = 0xe938;
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#define cris_breakpoint_len 2
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/* Implementation of target ops method "sw_breakpoint_from_kind". */
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const gdb_byte *
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cris_target::sw_breakpoint_from_kind (int kind, int *size)
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{
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*size = cris_breakpoint_len;
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return (const gdb_byte *) &cris_breakpoint;
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}
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bool
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cris_target::low_breakpoint_at (CORE_ADDR where)
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{
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unsigned short insn;
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read_memory (where, (unsigned char *) &insn, cris_breakpoint_len);
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if (insn == cris_breakpoint)
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return true;
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/* If necessary, recognize more trap instructions here. GDB only uses the
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one. */
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return false;
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}
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void
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cris_target::low_arch_setup ()
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{
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current_process ()->tdesc = tdesc_cris;
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}
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static struct usrregs_info cris_usrregs_info =
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{
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cris_num_regs,
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cris_regmap,
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};
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static struct regs_info myregs_info =
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{
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NULL, /* regset_bitmap */
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&cris_usrregs_info,
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};
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const regs_info *
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cris_target::get_regs_info ()
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{
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return &myregs_info;
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}
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/* The linux target ops object. */
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linux_process_target *the_linux_target = &the_cris_target;
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void
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initialize_low_arch (void)
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{
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init_registers_cris ();
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}
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@ -1,472 +0,0 @@
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/* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
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Copyright (C) 1995-2020 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include "nat/gdb_ptrace.h"
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/* Linux target op definitions for the CRIS architecture. */
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class crisv32_target : public linux_process_target
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{
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public:
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const regs_info *get_regs_info () override;
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const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
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bool supports_z_point_type (char z_type) override;
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protected:
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void low_arch_setup () override;
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bool low_cannot_fetch_register (int regno) override;
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bool low_cannot_store_register (int regno) override;
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bool low_supports_breakpoints () override;
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CORE_ADDR low_get_pc (regcache *regcache) override;
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void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
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bool low_breakpoint_at (CORE_ADDR pc) override;
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int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
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int size, raw_breakpoint *bp) override;
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int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
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int size, raw_breakpoint *bp) override;
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bool low_stopped_by_watchpoint () override;
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CORE_ADDR low_stopped_data_address () override;
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};
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/* The singleton target ops object. */
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static crisv32_target the_crisv32_target;
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bool
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crisv32_target::low_cannot_fetch_register (int regno)
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{
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gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
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"is not implemented by the target");
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}
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bool
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crisv32_target::low_cannot_store_register (int regno)
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{
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gdb_assert_not_reached ("linux target op low_cannot_store_register "
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"is not implemented by the target");
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}
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bool
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crisv32_target::low_supports_breakpoints ()
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{
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return true;
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}
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CORE_ADDR
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crisv32_target::low_get_pc (regcache *regcache)
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{
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return linux_get_pc_32bit (regcache);
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}
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void
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crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
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{
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linux_set_pc_32bit (regcache, pc);
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}
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/* Defined in auto-generated file reg-crisv32.c. */
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void init_registers_crisv32 (void);
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extern const struct target_desc *tdesc_crisv32;
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/* CRISv32 */
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#define cris_num_regs 49
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#ifndef PTRACE_GET_THREAD_AREA
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#define PTRACE_GET_THREAD_AREA 25
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#endif
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/* Note: Ignoring USP (having the stack pointer in two locations causes trouble
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without any significant gain). */
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/* Locations need to match <include/asm/arch/ptrace.h>. */
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static int cris_regmap[] = {
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1*4, 2*4, 3*4, 4*4,
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5*4, 6*4, 7*4, 8*4,
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9*4, 10*4, 11*4, 12*4,
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13*4, 14*4, 24*4, 15*4,
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-1, -1, -1, 16*4,
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-1, 22*4, 23*4, 17*4,
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-1, -1, 21*4, 20*4,
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-1, 19*4, -1, 18*4,
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25*4,
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26*4, -1, -1, 29*4,
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30*4, 31*4, 32*4, 33*4,
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34*4, 35*4, 36*4, 37*4,
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38*4, 39*4, 40*4, -1
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};
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static const unsigned short cris_breakpoint = 0xe938;
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#define cris_breakpoint_len 2
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/* Implementation of target ops method "sw_breakpoint_from_kind". */
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const gdb_byte *
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crisv32_target::sw_breakpoint_from_kind (int kind, int *size)
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{
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*size = cris_breakpoint_len;
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return (const gdb_byte *) &cris_breakpoint;
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}
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bool
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crisv32_target::low_breakpoint_at (CORE_ADDR where)
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{
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unsigned short insn;
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read_memory (where, (unsigned char *) &insn, cris_breakpoint_len);
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if (insn == cris_breakpoint)
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return true;
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/* If necessary, recognize more trap instructions here. GDB only uses the
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one. */
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return false;
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}
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static void
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cris_write_data_breakpoint (struct regcache *regcache,
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int bp, unsigned long start, unsigned long end)
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{
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switch (bp)
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{
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case 0:
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supply_register_by_name (regcache, "s3", &start);
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supply_register_by_name (regcache, "s4", &end);
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break;
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case 1:
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supply_register_by_name (regcache, "s5", &start);
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supply_register_by_name (regcache, "s6", &end);
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break;
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case 2:
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supply_register_by_name (regcache, "s7", &start);
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supply_register_by_name (regcache, "s8", &end);
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break;
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case 3:
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supply_register_by_name (regcache, "s9", &start);
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supply_register_by_name (regcache, "s10", &end);
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break;
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case 4:
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supply_register_by_name (regcache, "s11", &start);
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supply_register_by_name (regcache, "s12", &end);
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break;
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case 5:
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supply_register_by_name (regcache, "s13", &start);
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supply_register_by_name (regcache, "s14", &end);
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break;
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}
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}
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bool
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crisv32_target::supports_z_point_type (char z_type)
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{
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switch (z_type)
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{
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case Z_PACKET_WRITE_WP:
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case Z_PACKET_READ_WP:
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case Z_PACKET_ACCESS_WP:
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return true;
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default:
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return false;
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}
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}
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int
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crisv32_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
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int len, raw_breakpoint *bp)
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{
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int bp;
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unsigned long bp_ctrl;
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unsigned long start, end;
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unsigned long ccs;
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struct regcache *regcache;
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regcache = get_thread_regcache (current_thread, 1);
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/* Read watchpoints are set as access watchpoints, because of GDB's
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inability to deal with pure read watchpoints. */
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if (type == raw_bkpt_type_read_wp)
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type = raw_bkpt_type_access_wp;
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/* Get the configuration register. */
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collect_register_by_name (regcache, "s0", &bp_ctrl);
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/* The watchpoint allocation scheme is the simplest possible.
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For example, if a region is watched for read and
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a write watch is requested, a new watchpoint will
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be used. Also, if a watch for a region that is already
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covered by one or more existing watchpoints, a new
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watchpoint will be used. */
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/* First, find a free data watchpoint. */
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for (bp = 0; bp < 6; bp++)
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{
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/* Each data watchpoint's control registers occupy 2 bits
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(hence the 3), starting at bit 2 for D0 (hence the 2)
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with 4 bits between for each watchpoint (yes, the 4). */
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if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
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break;
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}
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if (bp > 5)
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{
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/* We're out of watchpoints. */
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return -1;
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}
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/* Configure the control register first. */
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if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
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{
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/* Trigger on read. */
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bp_ctrl |= (1 << (2 + bp * 4));
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}
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if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
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{
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/* Trigger on write. */
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bp_ctrl |= (2 << (2 + bp * 4));
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}
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/* Setup the configuration register. */
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supply_register_by_name (regcache, "s0", &bp_ctrl);
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/* Setup the range. */
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start = addr;
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end = addr + len - 1;
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/* Configure the watchpoint register. */
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cris_write_data_breakpoint (regcache, bp, start, end);
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collect_register_by_name (regcache, "ccs", &ccs);
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/* Set the S1 flag to enable watchpoints. */
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ccs |= (1 << 19);
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supply_register_by_name (regcache, "ccs", &ccs);
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return 0;
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}
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int
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crisv32_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
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int len, raw_breakpoint *bp)
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{
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int bp;
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||||
unsigned long bp_ctrl;
|
||||
unsigned long start, end;
|
||||
struct regcache *regcache;
|
||||
unsigned long bp_d_regs[12];
|
||||
|
||||
regcache = get_thread_regcache (current_thread, 1);
|
||||
|
||||
/* Read watchpoints are set as access watchpoints, because of GDB's
|
||||
inability to deal with pure read watchpoints. */
|
||||
if (type == raw_bkpt_type_read_wp)
|
||||
type = raw_bkpt_type_access_wp;
|
||||
|
||||
/* Get the configuration register. */
|
||||
collect_register_by_name (regcache, "s0", &bp_ctrl);
|
||||
|
||||
/* Try to find a watchpoint that is configured for the
|
||||
specified range, then check that read/write also matches. */
|
||||
|
||||
/* Ugly pointer arithmetic, since I cannot rely on a
|
||||
single switch (addr) as there may be several watchpoints with
|
||||
the same start address for example. */
|
||||
|
||||
/* Get all range registers to simplify search. */
|
||||
collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
|
||||
collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
|
||||
collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
|
||||
collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
|
||||
collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
|
||||
collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
|
||||
collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
|
||||
collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
|
||||
collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
|
||||
collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
|
||||
collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
|
||||
collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
|
||||
|
||||
for (bp = 0; bp < 6; bp++)
|
||||
{
|
||||
if (bp_d_regs[bp * 2] == addr
|
||||
&& bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
|
||||
/* Matching range. */
|
||||
int bitpos = 2 + bp * 4;
|
||||
int rw_bits;
|
||||
|
||||
/* Read/write bits for this BP. */
|
||||
rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
|
||||
|
||||
if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
|
||||
|| (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
|
||||
|| (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
|
||||
{
|
||||
/* Read/write matched. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (bp > 5)
|
||||
{
|
||||
/* No watchpoint matched. */
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Found a matching watchpoint. Now, deconfigure it by
|
||||
both disabling read/write in bp_ctrl and zeroing its
|
||||
start/end addresses. */
|
||||
bp_ctrl &= ~(3 << (2 + (bp * 4)));
|
||||
/* Setup the configuration register. */
|
||||
supply_register_by_name (regcache, "s0", &bp_ctrl);
|
||||
|
||||
start = end = 0;
|
||||
/* Configure the watchpoint register. */
|
||||
cris_write_data_breakpoint (regcache, bp, start, end);
|
||||
|
||||
/* Note that we don't clear the S1 flag here. It's done when continuing. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool
|
||||
crisv32_target::low_stopped_by_watchpoint ()
|
||||
{
|
||||
unsigned long exs;
|
||||
struct regcache *regcache = get_thread_regcache (current_thread, 1);
|
||||
|
||||
collect_register_by_name (regcache, "exs", &exs);
|
||||
|
||||
return (((exs & 0xff00) >> 8) == 0xc);
|
||||
}
|
||||
|
||||
CORE_ADDR
|
||||
crisv32_target::low_stopped_data_address ()
|
||||
{
|
||||
unsigned long eda;
|
||||
struct regcache *regcache = get_thread_regcache (current_thread, 1);
|
||||
|
||||
collect_register_by_name (regcache, "eda", &eda);
|
||||
|
||||
/* FIXME: Possibly adjust to match watched range. */
|
||||
return eda;
|
||||
}
|
||||
|
||||
ps_err_e
|
||||
ps_get_thread_area (struct ps_prochandle *ph,
|
||||
lwpid_t lwpid, int idx, void **base)
|
||||
{
|
||||
if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
|
||||
return PS_ERR;
|
||||
|
||||
/* IDX is the bias from the thread pointer to the beginning of the
|
||||
thread descriptor. It has to be subtracted due to implementation
|
||||
quirks in libthread_db. */
|
||||
*base = (void *) ((char *) *base - idx);
|
||||
return PS_OK;
|
||||
}
|
||||
|
||||
static void
|
||||
cris_fill_gregset (struct regcache *regcache, void *buf)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < cris_num_regs; i++)
|
||||
{
|
||||
if (cris_regmap[i] != -1)
|
||||
collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
cris_store_gregset (struct regcache *regcache, const void *buf)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < cris_num_regs; i++)
|
||||
{
|
||||
if (cris_regmap[i] != -1)
|
||||
supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
crisv32_target::low_arch_setup ()
|
||||
{
|
||||
current_process ()->tdesc = tdesc_crisv32;
|
||||
}
|
||||
|
||||
static struct regset_info cris_regsets[] = {
|
||||
{ PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
|
||||
GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
|
||||
NULL_REGSET
|
||||
};
|
||||
|
||||
|
||||
static struct regsets_info cris_regsets_info =
|
||||
{
|
||||
cris_regsets, /* regsets */
|
||||
0, /* num_regsets */
|
||||
NULL, /* disabled_regsets */
|
||||
};
|
||||
|
||||
static struct usrregs_info cris_usrregs_info =
|
||||
{
|
||||
cris_num_regs,
|
||||
cris_regmap,
|
||||
};
|
||||
|
||||
static struct regs_info myregs_info =
|
||||
{
|
||||
NULL, /* regset_bitmap */
|
||||
&cris_usrregs_info,
|
||||
&cris_regsets_info
|
||||
};
|
||||
|
||||
const regs_info *
|
||||
crisv32_target::get_regs_info ()
|
||||
{
|
||||
return &myregs_info;
|
||||
}
|
||||
|
||||
/* The linux target ops object. */
|
||||
|
||||
linux_process_target *the_linux_target = &the_crisv32_target;
|
||||
|
||||
void
|
||||
initialize_low_arch (void)
|
||||
{
|
||||
init_registers_crisv32 ();
|
||||
|
||||
initialize_regsets_info (&cris_regsets_info);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user