Add support for the Freescale s12z processor.

bfd	* Makefile.am: Add s12z files.
	* Makefile.in: Regenerate.
	* archures.c: Add bfd_s12z_arch.
	* bfd-in.h: Add exports of bfd_putb24 and bfd_putl24.
	* bfd-in2.h: Regenerate.
	* config.bfd: Add s12z target.
	* configure.ac: Add s12z target.
	* configure: Regenerate.
	* cpu-s12z.c: New file.
	* elf32-s12z.c: New file.
	* libbfd.c (bfd_putb24): New function.
	(bfd_putl24): New function.
	* libbfd.h: Regenerate.
	* reloc.c: Add s12z relocations.
	(bfd_get_reloc_size): Handle size 5 relocs.
	* targets.c: Add s12z_elf32_vec.

opcodes	* Makefile.am: Add support for s12z architecture.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* s12z-dis.c: New file.
	* s12z.h: New file.

include	* elf/s12z.h: New header.

ld	* Makefile.am: Add support for s12z architecture.
	* configure.tgt: Likewise.
	* Makefile.in: Regenerate.
	* emulparams/m9s12zelf.sh: New file.
	* scripttempl/elfm9s12z.sc: New file.
	* testsuite/ld-discard/static.d: Expect to fail for the s12z
	target.
	* testsuite/ld-elf/endsym.d: Likewise.
	* testsuite/ld-elf/merge.d: Likewise.
	* testsuite/ld-elf/pr14926.d: Skip for the s12z target.
	* testsuite/ld-elf/sec64k.exp: Likewise.
	* testsuite/ld-s12z: New directory.
	* testsuite/ld-s12z/opr-linking.d: New file.
	* testsuite/ld-s12z/opr-linking.s: New file.
	* testsuite/ld-s12z/relative-linking.d: New file.
	* testsuite/ld-s12z/relative-linking.s: New file.
	* testsuite/ld-s12z/z12s.exp: New file.

gas	* Makefile.am: Add support for s12z target.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new support.
	* config/tc-s12z.c: New file.
	* config/tc-s12z.h: New file.
	* configure.tgt: Add  s12z support.
	* doc/Makefile.am: Likewise.
	* doc/Makefile.in: Regenerate.
	* doc/all.texi: Add s12z documentation.
	* doc/as.textinfo: Likewise.
	* doc/c-s12z.texi: New file.
	* testsuite/gas/s12z: New directory.
	* testsuite/gas/s12z/abs.d: New file.
	* testsuite/gas/s12z/abs.s: New file.
	* testsuite/gas/s12z/adc-imm.d: New file.
	* testsuite/gas/s12z/adc-imm.s: New file.
	* testsuite/gas/s12z/adc-opr.d: New file.
	* testsuite/gas/s12z/adc-opr.s: New file.
	* testsuite/gas/s12z/add-imm.d: New file.
	* testsuite/gas/s12z/add-imm.s: New file.
	* testsuite/gas/s12z/add-opr.d: New file.
	* testsuite/gas/s12z/add-opr.s: New file.
	* testsuite/gas/s12z/and-imm.d: New file.
	* testsuite/gas/s12z/and-imm.s: New file.
	* testsuite/gas/s12z/and-opr.d: New file.
	* testsuite/gas/s12z/and-opr.s: New file.
	* testsuite/gas/s12z/and-or-cc.d: New file.
	* testsuite/gas/s12z/and-or-cc.s: New file.
	* testsuite/gas/s12z/bfext-special.d: New file.
	* testsuite/gas/s12z/bfext-special.s: New file.
	* testsuite/gas/s12z/bfext.d: New file.
	* testsuite/gas/s12z/bfext.s: New file.
	* testsuite/gas/s12z/bit-manip.d: New file.
	* testsuite/gas/s12z/bit-manip.s: New file.
	* testsuite/gas/s12z/bit.d: New file.
	* testsuite/gas/s12z/bit.s: New file.
	* testsuite/gas/s12z/bra-expression-defined.d: New file.
	* testsuite/gas/s12z/bra-expression-defined.s: New file.
	* testsuite/gas/s12z/bra-expression-undef.d: New file.
	* testsuite/gas/s12z/bra-expression-undef.s: New file.
	* testsuite/gas/s12z/bra.d: New file.
	* testsuite/gas/s12z/bra.s: New file.
	* testsuite/gas/s12z/brclr-symbols.d: New file.
	* testsuite/gas/s12z/brclr-symbols.s: New file.
	* testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file.
	* testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file.
	* testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file.
	* testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file.
	* testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file.
	* testsuite/gas/s12z/clb.d: New file.
	* testsuite/gas/s12z/clb.s: New file.
	* testsuite/gas/s12z/clr-opr.d: New file.
	* testsuite/gas/s12z/clr-opr.s: New file.
	* testsuite/gas/s12z/clr.d: New file.
	* testsuite/gas/s12z/clr.s: New file.
	* testsuite/gas/s12z/cmp-imm.d: New file.
	* testsuite/gas/s12z/cmp-imm.s: New file.
	* testsuite/gas/s12z/cmp-opr-inc.d: New file.
	* testsuite/gas/s12z/cmp-opr-inc.s: New file.
	* testsuite/gas/s12z/cmp-opr-rdirect.d: New file.
	* testsuite/gas/s12z/cmp-opr-rdirect.s: New file.
	* testsuite/gas/s12z/cmp-opr-reg.d: New file.
	* testsuite/gas/s12z/cmp-opr-reg.s: New file.
	* testsuite/gas/s12z/cmp-opr-rindirect.d: New file.
	* testsuite/gas/s12z/cmp-opr-rindirect.s: New file.
	* testsuite/gas/s12z/cmp-opr-sxe4.d: New file.
	* testsuite/gas/s12z/cmp-opr-sxe4.s: New file.
	* testsuite/gas/s12z/cmp-opr-xys.d: New file.
	* testsuite/gas/s12z/cmp-opr-xys.s: New file.
	* testsuite/gas/s12z/cmp-s-imm.d: New file.
	* testsuite/gas/s12z/cmp-s-imm.s: New file.
	* testsuite/gas/s12z/cmp-s-opr.d: New file.
	* testsuite/gas/s12z/cmp-s-opr.s: New file.
	* testsuite/gas/s12z/cmp-xy.d: New file.
	* testsuite/gas/s12z/cmp-xy.s: New file.
	* testsuite/gas/s12z/com-opr.d: New file.
	* testsuite/gas/s12z/com-opr.s: New file.
	* testsuite/gas/s12z/complex-shifts.d: New file.
	* testsuite/gas/s12z/complex-shifts.s: New file.
	* testsuite/gas/s12z/db-tb-cc-opr.d: New file.
	* testsuite/gas/s12z/db-tb-cc-opr.s: New file.
	* testsuite/gas/s12z/db-tb-cc-reg.d: New file.
	* testsuite/gas/s12z/db-tb-cc-reg.s: New file.
	* testsuite/gas/s12z/dbCC.d: New file.
	* testsuite/gas/s12z/dbCC.s: New file.
	* testsuite/gas/s12z/dec-opr.d: New file.
	* testsuite/gas/s12z/dec-opr.s: New file.
	* testsuite/gas/s12z/dec.d: New file.
	* testsuite/gas/s12z/dec.s: New file.
	* testsuite/gas/s12z/div.d: New file.
	* testsuite/gas/s12z/div.s: New file.
	* testsuite/gas/s12z/eor.d: New file.
	* testsuite/gas/s12z/eor.s: New file.
	* testsuite/gas/s12z/exg.d: New file.
	* testsuite/gas/s12z/exg.s: New file.
	* testsuite/gas/s12z/ext24-ld-xy.d: New file.
	* testsuite/gas/s12z/ext24-ld-xy.s: New file.
	* testsuite/gas/s12z/inc-opr.d: New file.
	* testsuite/gas/s12z/inc-opr.s: New file.
	* testsuite/gas/s12z/inc.d: New file.
	* testsuite/gas/s12z/inc.s: New file.
	* testsuite/gas/s12z/inh.d: New file.
	* testsuite/gas/s12z/inh.s: New file.
	* testsuite/gas/s12z/jmp.d: New file.
	* testsuite/gas/s12z/jmp.s: New file.
	* testsuite/gas/s12z/jsr.d: New file.
	* testsuite/gas/s12z/jsr.s: New file.
	* testsuite/gas/s12z/ld-imm-page2.d: New file.
	* testsuite/gas/s12z/ld-imm-page2.s: New file.
	* testsuite/gas/s12z/ld-imm.d: New file.
	* testsuite/gas/s12z/ld-imm.s: New file.
	* testsuite/gas/s12z/ld-immu18.d: New file.
	* testsuite/gas/s12z/ld-immu18.s: New file.
	* testsuite/gas/s12z/ld-large-direct.d: New file.
	* testsuite/gas/s12z/ld-large-direct.s: New file.
	* testsuite/gas/s12z/ld-opr.d: New file.
	* testsuite/gas/s12z/ld-opr.s: New file.
	* testsuite/gas/s12z/ld-s-opr.d: New file.
	* testsuite/gas/s12z/ld-s-opr.s: New file.
	* testsuite/gas/s12z/ld-small-direct.d: New file.
	* testsuite/gas/s12z/ld-small-direct.s: New file.
	* testsuite/gas/s12z/lea-immu18.d: New file.
	* testsuite/gas/s12z/lea-immu18.s: New file.
	* testsuite/gas/s12z/lea.d: New file.
	* testsuite/gas/s12z/lea.s: New file.
	* testsuite/gas/s12z/mac.d: New file.
	* testsuite/gas/s12z/mac.s: New file.
	* testsuite/gas/s12z/min-max.d: New file.
	* testsuite/gas/s12z/min-max.s: New file.
	* testsuite/gas/s12z/mod.d: New file.
	* testsuite/gas/s12z/mod.s: New file.
	* testsuite/gas/s12z/mov.d: New file.
	* testsuite/gas/s12z/mov.s: New file.
	* testsuite/gas/s12z/mul-imm.d: New file.
	* testsuite/gas/s12z/mul-imm.s: New file.
	* testsuite/gas/s12z/mul-opr-opr.d: New file.
	* testsuite/gas/s12z/mul-opr-opr.s: New file.
	* testsuite/gas/s12z/mul-opr.d: New file.
	* testsuite/gas/s12z/mul-opr.s: New file.
	* testsuite/gas/s12z/mul-reg.d: New file.
	* testsuite/gas/s12z/mul-reg.s: New file.
	* testsuite/gas/s12z/mul.d: New file.
	* testsuite/gas/s12z/mul.s: New file.
	* testsuite/gas/s12z/neg-opr.d: New file.
	* testsuite/gas/s12z/neg-opr.s: New file.
	* testsuite/gas/s12z/not-so-simple-shifts.d: New file.
	* testsuite/gas/s12z/not-so-simple-shifts.s: New file.
	* testsuite/gas/s12z/opr-18u.d: New file.
	* testsuite/gas/s12z/opr-18u.s: New file.
	* testsuite/gas/s12z/opr-expr.d: New file.
	* testsuite/gas/s12z/opr-expr.s: New file.
	* testsuite/gas/s12z/opr-ext-18.d: New file.
	* testsuite/gas/s12z/opr-ext-18.s: New file.
	* testsuite/gas/s12z/opr-idx-24-reg.d: New file.
	* testsuite/gas/s12z/opr-idx-24-reg.s: New file.
	* testsuite/gas/s12z/opr-idx3-reg.d: New file.
	* testsuite/gas/s12z/opr-idx3-reg.s: New file.
	* testsuite/gas/s12z/opr-idx3-xysp-24.d: New file.
	* testsuite/gas/s12z/opr-idx3-xysp-24.s: New file.
	* testsuite/gas/s12z/opr-indirect-expr.d: New file.
	* testsuite/gas/s12z/opr-indirect-expr.s: New file.
	* testsuite/gas/s12z/opr-symbol.d: New file.
	* testsuite/gas/s12z/opr-symbol.s: New file.
	* testsuite/gas/s12z/or-imm.d: New file.
	* testsuite/gas/s12z/or-imm.s: New file.
	* testsuite/gas/s12z/or-opr.d: New file.
	* testsuite/gas/s12z/or-opr.s: New file.
	* testsuite/gas/s12z/p2-mul.d: New file.
	* testsuite/gas/s12z/p2-mul.s: New file.
	* testsuite/gas/s12z/page2-inh.d: New file.
	* testsuite/gas/s12z/page2-inh.s: New file.
	* testsuite/gas/s12z/psh-pul.d: New file.
	* testsuite/gas/s12z/psh-pul.s: New file.
	* testsuite/gas/s12z/qmul.d: New file.
	* testsuite/gas/s12z/qmul.s: New file.
	* testsuite/gas/s12z/rotate.d: New file.
	* testsuite/gas/s12z/rotate.s: New file.
	* testsuite/gas/s12z/s12z.exp: New file.
	* testsuite/gas/s12z/sat.d: New file.
	* testsuite/gas/s12z/sat.s: New file.
	* testsuite/gas/s12z/sbc-imm.d: New file.
	* testsuite/gas/s12z/sbc-imm.s: New file.
	* testsuite/gas/s12z/sbc-opr.d: New file.
	* testsuite/gas/s12z/sbc-opr.s: New file.
	* testsuite/gas/s12z/shift.d: New file.
	* testsuite/gas/s12z/shift.s: New file.
	* testsuite/gas/s12z/simple-shift.d: New file.
	* testsuite/gas/s12z/simple-shift.s: New file.
	* testsuite/gas/s12z/single-ops.d: New file.
	* testsuite/gas/s12z/single-ops.s: New file.
	* testsuite/gas/s12z/specd6.d: New file.
	* testsuite/gas/s12z/specd6.s: New file.
	* testsuite/gas/s12z/st-large-direct.d: New file.
	* testsuite/gas/s12z/st-large-direct.s: New file.
	* testsuite/gas/s12z/st-opr.d: New file.
	* testsuite/gas/s12z/st-opr.s: New file.
	* testsuite/gas/s12z/st-s-opr.d: New file.
	* testsuite/gas/s12z/st-s-opr.s: New file.
	* testsuite/gas/s12z/st-small-direct.d: New file.
	* testsuite/gas/s12z/st-small-direct.s: New file.
	* testsuite/gas/s12z/st-xy.d: New file.
	* testsuite/gas/s12z/st-xy.s: New file.
	* testsuite/gas/s12z/sub-imm.d: New file.
	* testsuite/gas/s12z/sub-imm.s: New file.
	* testsuite/gas/s12z/sub-opr.d: New file.
	* testsuite/gas/s12z/sub-opr.s: New file.
	* testsuite/gas/s12z/tfr.d: New file.
	* testsuite/gas/s12z/tfr.s: New file.
	* testsuite/gas/s12z/trap.d: New file.
	* testsuite/gas/s12z/trap.s: New file.

binutils* readelf.c: Add support for s12z architecture.
	* testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z
	targets.
This commit is contained in:
John Darrington 2018-05-18 15:26:18 +01:00 committed by Nick Clifton
parent 011b32fd42
commit 7b4ae82428
259 changed files with 11812 additions and 5 deletions

View File

@ -1,3 +1,22 @@
2018-05-18 John Darrington <john@darrington.wattle.id.au>
* Makefile.am: Add s12z files.
* Makefile.in: Regenerate.
* archures.c: Add bfd_s12z_arch.
* bfd-in.h: Add exports of bfd_putb24 and bfd_putl24.
* bfd-in2.h: Regenerate.
* config.bfd: Add s12z target.
* configure.ac: Add s12z target.
* configure: Regenerate.
* cpu-s12z.c: New file.
* elf32-s12z.c: New file.
* libbfd.c (bfd_putb24): New function.
(bfd_putl24): New function.
* libbfd.h: Regenerate.
* reloc.c: Add s12z relocations.
(bfd_get_reloc_size): Handle size 5 relocs.
* targets.c: Add s12z_elf32_vec.
2018-05-18 H.J. Lu <hongjiu.lu@intel.com>
PR ld/23189

View File

@ -123,6 +123,7 @@ ALL_MACHINES = \
cpu-m68hc11.lo \
cpu-m68hc12.lo \
cpu-m9s12x.lo \
cpu-s12z.lo \
cpu-m9s12xg.lo \
cpu-m68k.lo \
cpu-mcore.lo \
@ -207,6 +208,7 @@ ALL_MACHINES_CFILES = \
cpu-m68hc11.c \
cpu-m68hc12.c \
cpu-m9s12x.c \
cpu-s12z.c \
cpu-m9s12xg.c \
cpu-m68k.c \
cpu-mcore.c \
@ -322,6 +324,7 @@ BFD32_BACKENDS = \
elf32-m68hc12.lo \
elf32-m68hc1x.lo \
elf32-m68k.lo \
elf32-s12z.lo \
elf32-mcore.lo \
elf32-mep.lo \
elf32-metag.lo \
@ -458,6 +461,7 @@ BFD32_BACKENDS_CFILES = \
elf32-m68hc12.c \
elf32-m68hc1x.c \
elf32-m68k.c \
elf32-s12z.c \
elf32-mcore.c \
elf32-mep.c \
elf32-metag.c \

View File

@ -456,6 +456,7 @@ ALL_MACHINES = \
cpu-m68hc11.lo \
cpu-m68hc12.lo \
cpu-m9s12x.lo \
cpu-s12z.lo \
cpu-m9s12xg.lo \
cpu-m68k.lo \
cpu-mcore.lo \
@ -540,6 +541,7 @@ ALL_MACHINES_CFILES = \
cpu-m68hc11.c \
cpu-m68hc12.c \
cpu-m9s12x.c \
cpu-s12z.c \
cpu-m9s12xg.c \
cpu-m68k.c \
cpu-mcore.c \
@ -656,6 +658,7 @@ BFD32_BACKENDS = \
elf32-m68hc12.lo \
elf32-m68hc1x.lo \
elf32-m68k.lo \
elf32-s12z.lo \
elf32-mcore.lo \
elf32-mep.lo \
elf32-metag.lo \
@ -792,6 +795,7 @@ BFD32_BACKENDS_CFILES = \
elf32-m68hc12.c \
elf32-m68hc1x.c \
elf32-m68k.c \
elf32-s12z.c \
elf32-mcore.c \
elf32-mep.c \
elf32-metag.c \
@ -1253,6 +1257,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-m68k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-m9s12x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-m9s12xg.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-s12z.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mcore.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-mep.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-metag.Plo@am__quote@
@ -1344,6 +1349,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-m68hc12.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-m68hc1x.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-m68k.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s12z.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mcore.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mep.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-metag.Plo@am__quote@

View File

@ -281,6 +281,8 @@ DESCRIPTION
.#define bfd_mach_m6812s 2
. bfd_arch_m9s12x, {* Freescale S12X. *}
. bfd_arch_m9s12xg, {* Freescale XGATE. *}
. bfd_arch_s12z, {* Freescale S12Z. *}
.#define bfd_mach_s12z_default 0
. bfd_arch_z8k, {* Zilog Z8000. *}
.#define bfd_mach_z8001 1
.#define bfd_mach_z8002 2
@ -590,6 +592,7 @@ extern const bfd_arch_info_type bfd_m68hc11_arch;
extern const bfd_arch_info_type bfd_m68hc12_arch;
extern const bfd_arch_info_type bfd_m9s12x_arch;
extern const bfd_arch_info_type bfd_m9s12xg_arch;
extern const bfd_arch_info_type bfd_s12z_arch;
extern const bfd_arch_info_type bfd_m68k_arch;
extern const bfd_arch_info_type bfd_mcore_arch;
extern const bfd_arch_info_type bfd_mep_arch;
@ -679,6 +682,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_m68hc12_arch,
&bfd_m9s12x_arch,
&bfd_m9s12xg_arch,
&bfd_s12z_arch,
&bfd_m68k_arch,
&bfd_mcore_arch,
&bfd_mep_arch,

View File

@ -581,6 +581,8 @@ void bfd_putb64 (bfd_uint64_t, void *);
void bfd_putl64 (bfd_uint64_t, void *);
void bfd_putb32 (bfd_vma, void *);
void bfd_putl32 (bfd_vma, void *);
void bfd_putb24 (bfd_vma, void *);
void bfd_putl24 (bfd_vma, void *);
void bfd_putb16 (bfd_vma, void *);
void bfd_putl16 (bfd_vma, void *);

View File

@ -588,6 +588,8 @@ void bfd_putb64 (bfd_uint64_t, void *);
void bfd_putl64 (bfd_uint64_t, void *);
void bfd_putb32 (bfd_vma, void *);
void bfd_putl32 (bfd_vma, void *);
void bfd_putb24 (bfd_vma, void *);
void bfd_putl24 (bfd_vma, void *);
void bfd_putb16 (bfd_vma, void *);
void bfd_putl16 (bfd_vma, void *);
@ -2149,6 +2151,8 @@ enum bfd_architecture
#define bfd_mach_m6812s 2
bfd_arch_m9s12x, /* Freescale S12X. */
bfd_arch_m9s12xg, /* Freescale XGATE. */
bfd_arch_s12z, /* Freescale S12Z. */
#define bfd_mach_s12z_default 0
bfd_arch_z8k, /* Zilog Z8000. */
#define bfd_mach_z8001 1
#define bfd_mach_z8002 2
@ -5253,6 +5257,11 @@ This is the 8 bit high part of an absolute address and immediately follows
a matching LO8XG part. */
BFD_RELOC_M68HC12_HI8XG,
/* Freescale S12Z reloc.
This is a 15 bit relative address. If the most significant bits are all zero
then it may be truncated to 8 bits. */
BFD_RELOC_S12Z_15_PCREL,
/* NS CR16C Relocations. */
BFD_RELOC_16C_NUM08,
BFD_RELOC_16C_NUM08_C,

View File

@ -179,6 +179,7 @@ lm32) targ_archs=bfd_lm32_arch ;;
m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;;
m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;;
m68*) targ_archs=bfd_m68k_arch ;;
s12z*) targ_archs=bfd_s12z_arch ;;
microblaze*) targ_archs=bfd_microblaze_arch ;;
mips*) targ_archs=bfd_mips_arch ;;
nds32*) targ_archs=bfd_nds32_arch ;;
@ -814,6 +815,9 @@ case "${targ}" in
targ_defvec=m68k_elf32_vec
;;
s12z-*-*)
targ_defvec=s12z_elf32_vec
;;
mcore-*-elf)
targ_defvec=mcore_elf32_be_vec
targ_selvecs="mcore_elf32_be_vec mcore_elf32_le_vec"

1
bfd/configure vendored
View File

@ -14465,6 +14465,7 @@ do
m68hc11_elf32_vec) tb="$tb elf32-m68hc11.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
m68hc12_elf32_vec) tb="$tb elf32-m68hc12.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
m68k_elf32_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;;
s12z_elf32_vec) tb="$tb elf32-s12z.lo elf32.lo $elf" ;;
mach_o_be_vec) tb="$tb mach-o.lo dwarf2.lo" ;;
mach_o_le_vec) tb="$tb mach-o.lo dwarf2.lo" ;;
mach_o_fat_vec) tb="$tb mach-o.lo dwarf2.lo" ;;

View File

@ -520,6 +520,7 @@ do
m68hc11_elf32_vec) tb="$tb elf32-m68hc11.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
m68hc12_elf32_vec) tb="$tb elf32-m68hc12.lo elf32-m68hc1x.lo elf32.lo $elf" ;;
m68k_elf32_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;;
s12z_elf32_vec) tb="$tb elf32-s12z.lo elf32.lo $elf" ;;
mach_o_be_vec) tb="$tb mach-o.lo dwarf2.lo" ;;
mach_o_le_vec) tb="$tb mach-o.lo dwarf2.lo" ;;
mach_o_fat_vec) tb="$tb mach-o.lo dwarf2.lo" ;;

41
bfd/cpu-s12z.c Normal file
View File

@ -0,0 +1,41 @@
/* BFD support for the Freescale 9S12Z processor
Copyright (C) 2008-2018 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_s12z_arch =
{
16, /* 16 bits in a word. */
24, /* 24 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_s12z,
0,
"s12z",
"s12z",
4, /* Section alignment power. */
TRUE,
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
0,
};

270
bfd/elf32-s12z.c Normal file
View File

@ -0,0 +1,270 @@
/* Freescale S12Z-specific support for 32-bit ELF
Copyright (C) 1999-2018 Free Software Foundation, Inc.
(Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com))
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "bfdlink.h"
#include "libbfd.h"
#include "elf-bfd.h"
#include "elf/s12z.h"
/* Relocation functions. */
static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
(bfd *, bfd_reloc_code_real_type);
static bfd_boolean s12z_info_to_howto_rel
(bfd *, arelent *, Elf_Internal_Rela *);
static bfd_reloc_status_type
shift_addend_reloc (bfd *abfd, arelent *reloc_entry, struct bfd_symbol *symbol ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED, asection *input_section ATTRIBUTE_UNUSED,
bfd *output ATTRIBUTE_UNUSED, char **msg ATTRIBUTE_UNUSED)
{
/* This is a really peculiar reloc, which is done for compatibility
with the Freescale toolchain.
That toolchain appears to (ab)use the lowest 15 bits of the addend for
the purpose of holding flags. The purpose of these flags are unknown.
So in this function, when writing the bfd we left shift the addend by
15, and when reading we right shift it by 15 (discarding the lower bits).
This allows the linker to work with object files generated by Freescale,
as well as by Gas. */
if (abfd->is_linker_input)
reloc_entry->addend >>= 15;
else
reloc_entry->addend <<= 15;
return bfd_reloc_continue;
}
#define USE_REL 0
static reloc_howto_type elf_s12z_howto_table[] =
{
/* This reloc does nothing. */
HOWTO (R_S12Z_NONE, /* type */
0, /* rightshift */
3, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_S12Z_NONE", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 24 bit absolute relocation emitted by the OPR mode operands */
HOWTO (R_S12Z_OPR, /* type */
0, /* rightshift */
5, /* size (0 = byte, 1 = short, 2 = long) */
24, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
shift_addend_reloc,
"R_S12Z_OPR", /* name */
FALSE, /* partial_inplace */
0x00ffffff, /* src_mask */
0x00ffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* The purpose of this reloc is not known */
HOWTO (R_S12Z_UKNWN_2, /* type */
0, /* rightshift */
3, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_S12Z_UKNWN_2", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 15 bit PC-rel relocation */
HOWTO (R_S12Z_PCREL_7_15, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
15, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
shift_addend_reloc,
"R_S12Z_PCREL_7_15", /* name */
FALSE, /* partial_inplace */
0x00, /* src_mask */
0x007fff, /* dst_mask */
TRUE), /* pcrel_offset */
/* A 24 bit absolute relocation emitted by EXT24 mode operands */
HOWTO (R_S12Z_EXT24, /* type */
0, /* rightshift */
5, /* size (0 = byte, 1 = short, 2 = long) */
24, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_S12Z_EXT24", /* name */
FALSE, /* partial_inplace */
0x00ffffff, /* src_mask */
0x00ffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* The purpose of this reloc is not known */
HOWTO (R_S12Z_UKNWN_3, /* type */
0, /* rightshift */
3, /* size (0 = byte, 1 = short, 2 = long) */
0, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_S12Z_UKNWN_3", /* name */
FALSE, /* partial_inplace */
0, /* src_mask */
0, /* dst_mask */
FALSE), /* pcrel_offset */
/* A 32 bit absolute relocation */
HOWTO (R_S12Z_EXT32, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_S12Z_EXT32", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* Map BFD reloc types to S12Z ELF reloc types. */
struct s12z_reloc_map
{
bfd_reloc_code_real_type bfd_reloc_val;
unsigned char elf_reloc_val;
};
static const struct s12z_reloc_map s12z_reloc_map[] =
{
/* bfd reloc val */ /* elf reloc val */
{BFD_RELOC_NONE, R_S12Z_NONE},
{BFD_RELOC_32, R_S12Z_EXT32},
{BFD_RELOC_24, R_S12Z_EXT24},
{BFD_RELOC_16_PCREL, R_S12Z_PCREL_7_15}
};
static reloc_howto_type *
bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
bfd_reloc_code_real_type code)
{
unsigned int i;
for (i = 0;
i < sizeof (s12z_reloc_map) / sizeof (struct s12z_reloc_map);
i++)
{
if (s12z_reloc_map[i].bfd_reloc_val == code)
{
return &elf_s12z_howto_table[s12z_reloc_map[i].elf_reloc_val];
}
}
printf ("%s:%d Not found type %d\n", __FILE__, __LINE__, code);
return NULL;
}
static reloc_howto_type *
bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
const char *r_name)
{
unsigned int i;
printf ("%s:%d Looking up %s\n", __FILE__, __LINE__, r_name);
for (i = 0;
i < (sizeof (elf_s12z_howto_table)
/ sizeof (elf_s12z_howto_table[0]));
i++)
if (elf_s12z_howto_table[i].name != NULL
&& strcasecmp (elf_s12z_howto_table[i].name, r_name) == 0)
return &elf_s12z_howto_table[i];
return NULL;
}
/* Set the howto pointer for an S12Z ELF reloc. */
static bfd_boolean
s12z_info_to_howto_rel (bfd *abfd,
arelent *cache_ptr, Elf_Internal_Rela *dst)
{
unsigned int r_type = ELF32_R_TYPE (dst->r_info);
if (r_type >= (unsigned int) R_S12Z_max)
{
/* xgettext:c-format */
_bfd_error_handler (_("%pB: unsupported relocation type %#x"),
abfd, r_type);
bfd_set_error (bfd_error_bad_value);
return FALSE;
}
cache_ptr->howto = &elf_s12z_howto_table[r_type];
return TRUE;
}
static bfd_boolean
s12z_elf_set_mach_from_flags (bfd *abfd)
{
bfd_default_set_arch_mach (abfd, bfd_arch_s12z, 0); // bfd_mach_s12z);
return TRUE;
}
#define ELF_ARCH bfd_arch_s12z
#define ELF_TARGET_ID 0
#define ELF_MACHINE_CODE EM_S12Z
#define ELF_MAXPAGESIZE 0x1000
#define TARGET_BIG_SYM s12z_elf32_vec
#define TARGET_BIG_NAME "elf32-s12z"
#define elf_info_to_howto NULL
#define elf_info_to_howto_rel s12z_info_to_howto_rel
#define elf_backend_object_p s12z_elf_set_mach_from_flags
#define elf_backend_final_write_processing NULL
#define elf_backend_can_gc_sections 1
#include "elf32-target.h"

View File

@ -613,6 +613,27 @@ bfd_putl16 (bfd_vma data, void *p)
addr[1] = (data >> 8) & 0xff;
}
void
bfd_putb24 (bfd_vma data, void *p)
{
bfd_byte *addr = (bfd_byte *) p;
addr[0] = (data >> 16) & 0xff;
addr[1] = (data >> 8) & 0xff;
addr[2] = data & 0xff;
}
void
bfd_putl24 (bfd_vma data, void *p)
{
bfd_byte *addr = (bfd_byte *) p;
addr[0] = data & 0xff;
addr[1] = (data >> 8) & 0xff;
addr[2] = (data >> 16) & 0xff;
}
bfd_vma
bfd_getb32 (const void *p)
{

View File

@ -2513,6 +2513,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_M68HC12_10_PCREL",
"BFD_RELOC_M68HC12_LO8XG",
"BFD_RELOC_M68HC12_HI8XG",
"BFD_RELOC_S12Z_15_PCREL",
"BFD_RELOC_16C_NUM08",
"BFD_RELOC_16C_NUM08_C",
"BFD_RELOC_16C_NUM16",

View File

@ -431,6 +431,7 @@ bfd_get_reloc_size (reloc_howto_type *howto)
{
switch (howto->size)
{
case 5: return 3;
case 0: return 1;
case 1: return 2;
case 2: return 4;
@ -917,6 +918,16 @@ space consuming. For each target:
switch (howto->size)
{
case 5:
{
long x = bfd_get_32 (abfd, (bfd_byte *) data + octets);
x >>= 8;
DOIT (x);
bfd_put_16 (abfd, (bfd_vma) (x >> 8), (bfd_byte *) data + octets);
bfd_put_8 (abfd, (x & 0xFF), (unsigned char *) data + 2 + octets);
}
break;
case 0:
{
char x = bfd_get_8 (abfd, (char *) data + octets);
@ -5948,6 +5959,12 @@ ENUMDOC
Motorola 68HC12/XGATE reloc.
This is the 8 bit high part of an absolute address and immediately follows
a matching LO8XG part.
ENUM
BFD_RELOC_S12Z_15_PCREL
ENUMDOC
Freescale S12Z reloc.
This is a 15 bit relative address. If the most significant bits are all zero
then it may be truncated to 8 bits.
ENUM
BFD_RELOC_16C_NUM08
ENUMX

View File

@ -684,6 +684,7 @@ extern const bfd_target m32r_elf32_linux_le_vec;
extern const bfd_target m68hc11_elf32_vec;
extern const bfd_target m68hc12_elf32_vec;
extern const bfd_target m68k_elf32_vec;
extern const bfd_target s12z_elf32_vec;
extern const bfd_target mach_o_be_vec;
extern const bfd_target mach_o_le_vec;
extern const bfd_target mach_o_fat_vec;
@ -1044,6 +1045,8 @@ static const bfd_target * const _bfd_target_vector[] =
&m68k_elf32_vec,
&s12z_elf32_vec,
&mach_o_be_vec,
&mach_o_le_vec,
&mach_o_fat_vec,

View File

@ -1,3 +1,9 @@
2018-05-18 John Darrington <john@darrington.wattle.id.au>
* readelf.c: Add support for s12z architecture.
* testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z
targets.
2018-05-15 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446

View File

@ -119,6 +119,7 @@
#include "elf/m32r.h"
#include "elf/m68k.h"
#include "elf/m68hc11.h"
#include "elf/s12z.h"
#include "elf/mcore.h"
#include "elf/mep.h"
#include "elf/metag.h"
@ -1274,6 +1275,10 @@ dump_relocations (Filedata * filedata,
rtype = elf_m68hc11_reloc_type (type);
break;
case EM_S12Z:
rtype = elf_s12z_reloc_type (type);
break;
case EM_68K:
rtype = elf_m68k_reloc_type (type);
break;
@ -12309,6 +12314,8 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_68HC11:
case EM_68HC12:
return reloc_type == 6; /* R_M68HC11_32. */
case EM_S12Z:
return reloc_type == 6; /* R_S12Z_EXT32. */
case EM_MCORE:
return reloc_type == 1; /* R_MCORE_ADDR32. */
case EM_CYGNUS_MEP:

View File

@ -27,6 +27,8 @@ _start:
func_cu1:
.Lbegin_func_cu1:
.4byte 0
.global func_cu1_end
func_cu1_end:
.Lend_func_cu1:
.size func_cu1, .-func_cu1
.Lend_text1:

View File

@ -23,7 +23,7 @@ proc is_elf_format {} {
# config.sub for these targets curiously transforms a target doublet
# ending in -elf to -none. eg. m68hc12-elf to m68hc12-unknown-none
# They are always elf.
if { [istarget m68hc1*-*] || [istarget xgate-*] } {
if { [istarget m68hc1*-*] || [istarget s12z*-*] || [istarget xgate-*] } {
return 1;
}
# vxworks (and windiss) excluded due to number of ELF tests that need

View File

@ -1,3 +1,219 @@
2018-05-18 John Darrington <john@darrington.wattle.id.au>
* Makefile.am: Add support for s12z target.
* Makefile.in: Regenerate.
* NEWS: Mention the new support.
* config/tc-s12z.c: New file.
* config/tc-s12z.h: New file.
* configure.tgt: Add s12z support.
* doc/Makefile.am: Likewise.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add s12z documentation.
* doc/as.textinfo: Likewise.
* doc/c-s12z.texi: New file.
* testsuite/gas/s12z: New directory.
* testsuite/gas/s12z/abs.d: New file.
* testsuite/gas/s12z/abs.s: New file.
* testsuite/gas/s12z/adc-imm.d: New file.
* testsuite/gas/s12z/adc-imm.s: New file.
* testsuite/gas/s12z/adc-opr.d: New file.
* testsuite/gas/s12z/adc-opr.s: New file.
* testsuite/gas/s12z/add-imm.d: New file.
* testsuite/gas/s12z/add-imm.s: New file.
* testsuite/gas/s12z/add-opr.d: New file.
* testsuite/gas/s12z/add-opr.s: New file.
* testsuite/gas/s12z/and-imm.d: New file.
* testsuite/gas/s12z/and-imm.s: New file.
* testsuite/gas/s12z/and-opr.d: New file.
* testsuite/gas/s12z/and-opr.s: New file.
* testsuite/gas/s12z/and-or-cc.d: New file.
* testsuite/gas/s12z/and-or-cc.s: New file.
* testsuite/gas/s12z/bfext-special.d: New file.
* testsuite/gas/s12z/bfext-special.s: New file.
* testsuite/gas/s12z/bfext.d: New file.
* testsuite/gas/s12z/bfext.s: New file.
* testsuite/gas/s12z/bit-manip.d: New file.
* testsuite/gas/s12z/bit-manip.s: New file.
* testsuite/gas/s12z/bit.d: New file.
* testsuite/gas/s12z/bit.s: New file.
* testsuite/gas/s12z/bra-expression-defined.d: New file.
* testsuite/gas/s12z/bra-expression-defined.s: New file.
* testsuite/gas/s12z/bra-expression-undef.d: New file.
* testsuite/gas/s12z/bra-expression-undef.s: New file.
* testsuite/gas/s12z/bra.d: New file.
* testsuite/gas/s12z/bra.s: New file.
* testsuite/gas/s12z/brclr-symbols.d: New file.
* testsuite/gas/s12z/brclr-symbols.s: New file.
* testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file.
* testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file.
* testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file.
* testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file.
* testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file.
* testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file.
* testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file.
* testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file.
* testsuite/gas/s12z/clb.d: New file.
* testsuite/gas/s12z/clb.s: New file.
* testsuite/gas/s12z/clr-opr.d: New file.
* testsuite/gas/s12z/clr-opr.s: New file.
* testsuite/gas/s12z/clr.d: New file.
* testsuite/gas/s12z/clr.s: New file.
* testsuite/gas/s12z/cmp-imm.d: New file.
* testsuite/gas/s12z/cmp-imm.s: New file.
* testsuite/gas/s12z/cmp-opr-inc.d: New file.
* testsuite/gas/s12z/cmp-opr-inc.s: New file.
* testsuite/gas/s12z/cmp-opr-rdirect.d: New file.
* testsuite/gas/s12z/cmp-opr-rdirect.s: New file.
* testsuite/gas/s12z/cmp-opr-reg.d: New file.
* testsuite/gas/s12z/cmp-opr-reg.s: New file.
* testsuite/gas/s12z/cmp-opr-rindirect.d: New file.
* testsuite/gas/s12z/cmp-opr-rindirect.s: New file.
* testsuite/gas/s12z/cmp-opr-sxe4.d: New file.
* testsuite/gas/s12z/cmp-opr-sxe4.s: New file.
* testsuite/gas/s12z/cmp-opr-xys.d: New file.
* testsuite/gas/s12z/cmp-opr-xys.s: New file.
* testsuite/gas/s12z/cmp-s-imm.d: New file.
* testsuite/gas/s12z/cmp-s-imm.s: New file.
* testsuite/gas/s12z/cmp-s-opr.d: New file.
* testsuite/gas/s12z/cmp-s-opr.s: New file.
* testsuite/gas/s12z/cmp-xy.d: New file.
* testsuite/gas/s12z/cmp-xy.s: New file.
* testsuite/gas/s12z/com-opr.d: New file.
* testsuite/gas/s12z/com-opr.s: New file.
* testsuite/gas/s12z/complex-shifts.d: New file.
* testsuite/gas/s12z/complex-shifts.s: New file.
* testsuite/gas/s12z/db-tb-cc-opr.d: New file.
* testsuite/gas/s12z/db-tb-cc-opr.s: New file.
* testsuite/gas/s12z/db-tb-cc-reg.d: New file.
* testsuite/gas/s12z/db-tb-cc-reg.s: New file.
* testsuite/gas/s12z/dbCC.d: New file.
* testsuite/gas/s12z/dbCC.s: New file.
* testsuite/gas/s12z/dec-opr.d: New file.
* testsuite/gas/s12z/dec-opr.s: New file.
* testsuite/gas/s12z/dec.d: New file.
* testsuite/gas/s12z/dec.s: New file.
* testsuite/gas/s12z/div.d: New file.
* testsuite/gas/s12z/div.s: New file.
* testsuite/gas/s12z/eor.d: New file.
* testsuite/gas/s12z/eor.s: New file.
* testsuite/gas/s12z/exg.d: New file.
* testsuite/gas/s12z/exg.s: New file.
* testsuite/gas/s12z/ext24-ld-xy.d: New file.
* testsuite/gas/s12z/ext24-ld-xy.s: New file.
* testsuite/gas/s12z/inc-opr.d: New file.
* testsuite/gas/s12z/inc-opr.s: New file.
* testsuite/gas/s12z/inc.d: New file.
* testsuite/gas/s12z/inc.s: New file.
* testsuite/gas/s12z/inh.d: New file.
* testsuite/gas/s12z/inh.s: New file.
* testsuite/gas/s12z/jmp.d: New file.
* testsuite/gas/s12z/jmp.s: New file.
* testsuite/gas/s12z/jsr.d: New file.
* testsuite/gas/s12z/jsr.s: New file.
* testsuite/gas/s12z/ld-imm-page2.d: New file.
* testsuite/gas/s12z/ld-imm-page2.s: New file.
* testsuite/gas/s12z/ld-imm.d: New file.
* testsuite/gas/s12z/ld-imm.s: New file.
* testsuite/gas/s12z/ld-immu18.d: New file.
* testsuite/gas/s12z/ld-immu18.s: New file.
* testsuite/gas/s12z/ld-large-direct.d: New file.
* testsuite/gas/s12z/ld-large-direct.s: New file.
* testsuite/gas/s12z/ld-opr.d: New file.
* testsuite/gas/s12z/ld-opr.s: New file.
* testsuite/gas/s12z/ld-s-opr.d: New file.
* testsuite/gas/s12z/ld-s-opr.s: New file.
* testsuite/gas/s12z/ld-small-direct.d: New file.
* testsuite/gas/s12z/ld-small-direct.s: New file.
* testsuite/gas/s12z/lea-immu18.d: New file.
* testsuite/gas/s12z/lea-immu18.s: New file.
* testsuite/gas/s12z/lea.d: New file.
* testsuite/gas/s12z/lea.s: New file.
* testsuite/gas/s12z/mac.d: New file.
* testsuite/gas/s12z/mac.s: New file.
* testsuite/gas/s12z/min-max.d: New file.
* testsuite/gas/s12z/min-max.s: New file.
* testsuite/gas/s12z/mod.d: New file.
* testsuite/gas/s12z/mod.s: New file.
* testsuite/gas/s12z/mov.d: New file.
* testsuite/gas/s12z/mov.s: New file.
* testsuite/gas/s12z/mul-imm.d: New file.
* testsuite/gas/s12z/mul-imm.s: New file.
* testsuite/gas/s12z/mul-opr-opr.d: New file.
* testsuite/gas/s12z/mul-opr-opr.s: New file.
* testsuite/gas/s12z/mul-opr.d: New file.
* testsuite/gas/s12z/mul-opr.s: New file.
* testsuite/gas/s12z/mul-reg.d: New file.
* testsuite/gas/s12z/mul-reg.s: New file.
* testsuite/gas/s12z/mul.d: New file.
* testsuite/gas/s12z/mul.s: New file.
* testsuite/gas/s12z/neg-opr.d: New file.
* testsuite/gas/s12z/neg-opr.s: New file.
* testsuite/gas/s12z/not-so-simple-shifts.d: New file.
* testsuite/gas/s12z/not-so-simple-shifts.s: New file.
* testsuite/gas/s12z/opr-18u.d: New file.
* testsuite/gas/s12z/opr-18u.s: New file.
* testsuite/gas/s12z/opr-expr.d: New file.
* testsuite/gas/s12z/opr-expr.s: New file.
* testsuite/gas/s12z/opr-ext-18.d: New file.
* testsuite/gas/s12z/opr-ext-18.s: New file.
* testsuite/gas/s12z/opr-idx-24-reg.d: New file.
* testsuite/gas/s12z/opr-idx-24-reg.s: New file.
* testsuite/gas/s12z/opr-idx3-reg.d: New file.
* testsuite/gas/s12z/opr-idx3-reg.s: New file.
* testsuite/gas/s12z/opr-idx3-xysp-24.d: New file.
* testsuite/gas/s12z/opr-idx3-xysp-24.s: New file.
* testsuite/gas/s12z/opr-indirect-expr.d: New file.
* testsuite/gas/s12z/opr-indirect-expr.s: New file.
* testsuite/gas/s12z/opr-symbol.d: New file.
* testsuite/gas/s12z/opr-symbol.s: New file.
* testsuite/gas/s12z/or-imm.d: New file.
* testsuite/gas/s12z/or-imm.s: New file.
* testsuite/gas/s12z/or-opr.d: New file.
* testsuite/gas/s12z/or-opr.s: New file.
* testsuite/gas/s12z/p2-mul.d: New file.
* testsuite/gas/s12z/p2-mul.s: New file.
* testsuite/gas/s12z/page2-inh.d: New file.
* testsuite/gas/s12z/page2-inh.s: New file.
* testsuite/gas/s12z/psh-pul.d: New file.
* testsuite/gas/s12z/psh-pul.s: New file.
* testsuite/gas/s12z/qmul.d: New file.
* testsuite/gas/s12z/qmul.s: New file.
* testsuite/gas/s12z/rotate.d: New file.
* testsuite/gas/s12z/rotate.s: New file.
* testsuite/gas/s12z/s12z.exp: New file.
* testsuite/gas/s12z/sat.d: New file.
* testsuite/gas/s12z/sat.s: New file.
* testsuite/gas/s12z/sbc-imm.d: New file.
* testsuite/gas/s12z/sbc-imm.s: New file.
* testsuite/gas/s12z/sbc-opr.d: New file.
* testsuite/gas/s12z/sbc-opr.s: New file.
* testsuite/gas/s12z/shift.d: New file.
* testsuite/gas/s12z/shift.s: New file.
* testsuite/gas/s12z/simple-shift.d: New file.
* testsuite/gas/s12z/simple-shift.s: New file.
* testsuite/gas/s12z/single-ops.d: New file.
* testsuite/gas/s12z/single-ops.s: New file.
* testsuite/gas/s12z/specd6.d: New file.
* testsuite/gas/s12z/specd6.s: New file.
* testsuite/gas/s12z/st-large-direct.d: New file.
* testsuite/gas/s12z/st-large-direct.s: New file.
* testsuite/gas/s12z/st-opr.d: New file.
* testsuite/gas/s12z/st-opr.s: New file.
* testsuite/gas/s12z/st-s-opr.d: New file.
* testsuite/gas/s12z/st-s-opr.s: New file.
* testsuite/gas/s12z/st-small-direct.d: New file.
* testsuite/gas/s12z/st-small-direct.s: New file.
* testsuite/gas/s12z/st-xy.d: New file.
* testsuite/gas/s12z/st-xy.s: New file.
* testsuite/gas/s12z/sub-imm.d: New file.
* testsuite/gas/s12z/sub-imm.s: New file.
* testsuite/gas/s12z/sub-opr.d: New file.
* testsuite/gas/s12z/sub-opr.s: New file.
* testsuite/gas/s12z/tfr.d: New file.
* testsuite/gas/s12z/tfr.s: New file.
* testsuite/gas/s12z/trap.d: New file.
* testsuite/gas/s12z/trap.s: New file.
2018-05-16 Maciej W. Rozycki <macro@mips.com>
* tc-nds32.c (md_assemble): Rename `expr' local variable to

View File

@ -156,6 +156,7 @@ TARGET_CPU_CFILES = \
config/tc-m32r.c \
config/tc-m68hc11.c \
config/tc-m68k.c \
config/tc-s12z.c \
config/tc-mcore.c \
config/tc-mep.c \
config/tc-metag.c \
@ -229,6 +230,7 @@ TARGET_CPU_HFILES = \
config/tc-m32r.h \
config/tc-m68hc11.h \
config/tc-m68k.h \
config/tc-s12z.h \
config/tc-mcore.h \
config/tc-mep.h \
config/tc-metag.h \

View File

@ -452,6 +452,7 @@ TARGET_CPU_CFILES = \
config/tc-m32r.c \
config/tc-m68hc11.c \
config/tc-m68k.c \
config/tc-s12z.c \
config/tc-mcore.c \
config/tc-mep.c \
config/tc-metag.c \
@ -525,6 +526,7 @@ TARGET_CPU_HFILES = \
config/tc-m32r.h \
config/tc-m68hc11.h \
config/tc-m68k.h \
config/tc-s12z.h \
config/tc-mcore.h \
config/tc-mep.h \
config/tc-metag.h \
@ -872,6 +874,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-m32r.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-m68hc11.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-m68k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-s12z.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mcore.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-mep.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-metag.Po@am__quote@
@ -1318,6 +1321,20 @@ tc-m68k.obj: config/tc-m68k.c
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-m68k.obj `if test -f 'config/tc-m68k.c'; then $(CYGPATH_W) 'config/tc-m68k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-m68k.c'; fi`
tc-s12z.o: config/tc-s12z.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-s12z.o -MD -MP -MF $(DEPDIR)/tc-s12z.Tpo -c -o tc-s12z.o `test -f 'config/tc-s12z.c' || echo '$(srcdir)/'`config/tc-s12z.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-s12z.Tpo $(DEPDIR)/tc-s12z.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-s12z.c' object='tc-s12z.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-s12z.o `test -f 'config/tc-s12z.c' || echo '$(srcdir)/'`config/tc-s12z.c
tc-s12z.obj: config/tc-s12z.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-s12z.obj -MD -MP -MF $(DEPDIR)/tc-s12z.Tpo -c -o tc-s12z.obj `if test -f 'config/tc-s12z.c'; then $(CYGPATH_W) 'config/tc-s12z.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-s12z.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-s12z.Tpo $(DEPDIR)/tc-s12z.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-s12z.c' object='tc-s12z.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-s12z.obj `if test -f 'config/tc-s12z.c'; then $(CYGPATH_W) 'config/tc-s12z.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-s12z.c'; fi`
tc-mcore.o: config/tc-mcore.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-mcore.o -MD -MP -MF $(DEPDIR)/tc-mcore.Tpo -c -o tc-mcore.o `test -f 'config/tc-mcore.c' || echo '$(srcdir)/'`config/tc-mcore.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-mcore.Tpo $(DEPDIR)/tc-mcore.Po

View File

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the Freescale S12Z architecture.
* Add --generate-missing-build-notes=[yes|no] option to create (or not) GNU
Build Attribute notes if none are present in the input sources. Add a
--enable-generate-build-notes=[yes|no] configure time option to set the

3840
gas/config/tc-s12z.c Normal file

File diff suppressed because it is too large Load Diff

105
gas/config/tc-s12z.h Normal file
View File

@ -0,0 +1,105 @@
/* tc-s12z.h -- Header file for tc-s12z.c.
Copyright (C) 1999-2018 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
struct fix;
/* Define TC_M68K so that we can use the MRI mode. */
#define TC_M68K
#define TARGET_BYTES_BIG_ENDIAN 1
/* Motorola assembler specs does not require '.' before pseudo-ops. */
#define NO_PSEUDO_DOT 1
/* The target BFD architecture. */
#define TARGET_ARCH (s12z_arch ())
extern enum bfd_architecture s12z_arch (void);
#define TARGET_MACH (s12z_mach ())
extern int s12z_mach (void);
#define TARGET_FORMAT (s12z_arch_format ())
extern const char *s12z_arch_format (void);
#define LISTING_WORD_SIZE 1 /* A word is 1 bytes */
#define LISTING_LHS_WIDTH 4 /* One word on the first line */
#define LISTING_LHS_WIDTH_SECOND 4 /* One word on the second line */
#define LISTING_LHS_CONT_LINES 4 /* And 4 lines max */
#define LISTING_HEADER s12z_listing_header ()
extern const char *s12z_listing_header (void);
/* Permit temporary numeric labels. */
#define LOCAL_LABELS_FB 1
#define tc_init_after_args s12z_init_after_args
extern void s12z_init_after_args (void);
#define md_parse_long_option s12z_parse_long_option
extern int s12z_parse_long_option (char *);
#define DWARF2_LINE_MIN_INSN_LENGTH 1
/* Use 32-bit address to represent a symbol address so that we can
represent them with their page number. */
#define DWARF2_ADDR_SIZE(bfd) 4
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
#define md_number_to_chars number_to_chars_bigendian
/* Relax table to translate short relative branches (-128..127) into
absolute branches. */
#define TC_GENERIC_RELAX_TABLE md_relax_table
extern struct relax_type md_relax_table[];
/* GAS only handles relaxations for pc-relative data targeting addresses
in the same segment, so we have to handle the rest on our own. */
#define md_relax_frag(SEG, FRAGP, STRETCH) \
((FRAGP)->fr_symbol != NULL \
&& S_GET_SEGMENT ((FRAGP)->fr_symbol) == (SEG) \
? relax_frag (SEG, FRAGP, STRETCH) \
: s12z_relax_frag (SEG, FRAGP, STRETCH))
extern long s12z_relax_frag (segT, fragS*, long);
#define TC_HANDLES_FX_DONE
#define DIFF_EXPR_OK /* .-foo gets turned into PC relative relocs */
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
/* No shared lib support, so we don't need to ensure externally
visible symbols can be overridden. */
#define EXTERN_FORCE_RELOC 0
#define TC_FORCE_RELOCATION(fix) tc_s12z_force_relocation (fix)
extern int tc_s12z_force_relocation (struct fix *);
#define tc_fix_adjustable(X) tc_s12z_fix_adjustable(X)
extern int tc_s12z_fix_adjustable (struct fix *);
#define md_operand(x)
#define elf_tc_final_processing s12z_elf_final_processing
extern void s12z_elf_final_processing (void);
#define tc_print_statistics(FILE) s12z_print_statistics (FILE)
extern void s12z_print_statistics (FILE *);

View File

@ -75,6 +75,7 @@ case ${cpu} in
m680[012346]0) cpu_type=m68k ;;
m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
m683??) cpu_type=m68k ;;
s12z) cpu_type=s12z ;;
mep) cpu_type=mep endian=little ;;
microblazeel*) cpu_type=microblaze endian=little;;
microblaze*) cpu_type=microblaze endian=big;;
@ -285,6 +286,8 @@ case ${generic_target} in
m68k-*-gnu*) fmt=elf ;;
m68k-*-netbsdelf*) fmt=elf em=nbsd ;;
s12z-*-*) fmt=elf ;;
mep-*-elf) fmt=elf ;;
metag-*-elf) fmt=elf ;;

View File

@ -65,6 +65,7 @@ CPU_DOCS = \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-s12z.texi \
c-metag.texi \
c-microblaze.texi \
c-mips.texi \

View File

@ -340,6 +340,7 @@ CPU_DOCS = \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-s12z.texi \
c-metag.texi \
c-microblaze.texi \
c-mips.texi \

View File

@ -46,6 +46,7 @@
@set M32R
@set xc16x
@set M68HC11
@set S12Z
@set M680X0
@set MCORE
@set METAG

View File

@ -7565,6 +7565,9 @@ subject, see the hardware manufacturer's manual.
@ifset M68HC11
* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
@end ifset
@ifset S12Z
* S12Z-Dependent:: S12Z Dependent Features
@end ifset
@ifset METAG
* Meta-Dependent :: Meta Dependent Features
@end ifset
@ -7776,6 +7779,10 @@ family.
@include c-m68hc11.texi
@end ifset
@ifset S12Z
@include c-s12z.texi
@end ifset
@ifset METAG
@include c-metag.texi
@end ifset

212
gas/doc/c-s12z.texi Normal file
View File

@ -0,0 +1,212 @@
@c Copyright (C) 2018 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node S12Z-Dependent
@chapter S12Z Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter S12Z Dependent Features
@end ifclear
The Freescale S12Z version of @code{@value{AS}} has a few machine
dependent features.
@cindex S12Z support
@menu
* S12Z-Opts:: S12Z Options
* S12Z-Syntax:: Syntax
* S12Z-Directives:: Assembler Directives
* S12Z-opcodes:: Opcodes
@end menu
@node S12Z-Opts
@section S12Z Options
@cindex options, S12Z
@cindex S12Z options
@node S12Z-Syntax
@section Syntax
@cindex S12Z syntax
@cindex syntax, S12Z
In the S12Z syntax, the instruction name comes first and it may
be followed by one or by several operands.
In most cases the maximum number of operands is three.
Some instructions accept and (in certain situations require) a suffix
indicating the size of the operand.
The suffix is separated from the instruction name by a period (@samp{.})
and may be one of @samp{b}, @samp{w}, @samp{p} or @samp{l} indicating
`byte' (a single byte), `word' (2 bytes), `pointer' (3 bytes) or `long' (4 bytes)
respectively.
Operands are separated by a comma (@samp{,}).
A comma however does not act as a separator if it appears within parentheses
(@samp{()}) or within square brackets (@samp{[]}).
@code{@value{AS}} will complain if too many, too few or inappropriate operands
are specified for a given instruction.
The MRI mode is not supported for this architecture.
Example:
@smallexample
bset.b 0xA98, #5
mov.b #6, 0x2409
ld d0, #4
mov.l (d0, x), 0x2409
inc d0
cmp d0, #12
blt *-4
lea x, 0x2409
st y, (1, x)
@end smallexample
@cindex line comment character, S12Z
@cindex S12Z line comment character
The presence of a @samp{;} character anywhere
on a line indicates the start of a comment that extends to the end of
that line.
A @samp{*} or a @samp{#} character at the start of a line also
introduces a line comment, but these characters do not work elsewhere
on the line. If the first character of the line is a @samp{#} then as
well as starting a comment, the line could also be logical line number
directive (@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
@cindex line separator, S12Z
@cindex statement separator, S12Z
@cindex S12Z line separator
The S12Z assembler does not currently support a line separator
character.
@cindex S12Z addressing modes
@cindex addressing modes, S12Z
The following addressing modes are understood for the S12Z.
@table @dfn
@item Immediate
@samp{#@var{number}}
@item Immediate Bit Field
@samp{#@var{width}:@var{offset}}
Bit field instructions in the immediate mode require the width and offset to
be specified.
The @var{width} pararmeter specifies the number of bits in the field.
It should be a number in the range [1,32].
@var{Offset} determines the position within the field where the operation
should start.
It should be a number in the range [0,31].
@item Relative
@samp{*@var{symbol}}, or @samp{*[+-]@var{digits}}
Program counter relative addresses have a width of 15 bits.
Thus, they must be within the range [-32768, 32767].
@item Register
@samp{@var{reg}}
Some instructions accept a register as an operand.
In general, @var{reg} may be a data register (@samp{D0}, @samp{D1} @dots{}
@samp{D7}), the @var{X} register or the @var{Y} register.
A few instructions accept as an argument the stack pointer
register (@samp{S}), and/or the program counter (@samp{P}).
Some very special instructions accept arguments which refer to the
condition code register. For these arguments the syntax is
@samp{CCR}, @samp{CCH} or @samp{CCL} which refer to the complete condition code register, the condition code register high byte and the condition code register low byte respectively.
@item Absolute Direct
@samp{@var{symbol}}, or @samp{@var{digits}}
@item Absolute Indirect
@samp{[@var{symbol}}, or @samp{@var{digits}]}
@item Constant Offset Indexed
@samp{(@var{number},@var{reg})}
@var{Reg} may be either @samp{X}, @samp{Y}, @samp{S} or
@samp{P} or one of the data registers @samp{D0}, @samp{D1} @dots{}
@samp{D7}.
If any of the registers @samp{D2} @dots{} @samp{D5} are specified, then the
register value is treated as a signed value.
Otherwise it is treated as unsigned.
@var{Number} may be any integer in the range [-8388608,8388607].
@item Offset Indexed Indirect
@samp{[@var{number},@var{reg}]}
@var{Reg} may be either @samp{X}, @samp{Y}, @samp{S} or
@samp{P}.
@var{Number} may be any integer in the range [-8388608,8388607].
@item Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement
@samp{-@var{reg}},
@samp{+@var{reg}},
@samp{@var{reg}-} or
@samp{@var{reg}+}
This addressing mode is typically used to access a value at an address,
and simultaneously to increment/decrement the register pointing to that
address.
Thus @var{reg} may be any of the 24 bit registers @samp{X}, @samp{Y}, or
@samp{S}.
Pre-increment and post-decrement are not available for
register @samp{S} (only post-increment and pre-decrement are available).
@item Register Offset Direct
@samp{(@var{data-reg},@var{reg})}
@var{Reg} can be either @samp{X}, @samp{Y}, or @samp{S}.
@var{Data-reg}
must be one of the data registers @samp{D0}, @samp{D1} @dots{} @samp{D7}.
If any of the registers @samp{D2} @dots{} @samp{D5} are specified, then
the register value is treated as a signed value.
Otherwise it is treated as unsigned.
@item Register Offset Indirect
@samp{[@var{data-reg},@var{reg}]}
@var{Reg} can be either @samp{X} or @samp{Y}.
@var{Data-reg}
must be one of the data registers @samp{D0}, @samp{D1} @dots{} @samp{D7}.
If any of the registers @samp{D2} @dots{} @samp{D5} are specified, then
the register value is treated as a signed value.
Otherwise it is treated as unsigned.
@end table
For example:
@smallexample
trap #197
bra *+49
bra .L0
jmp 0xFE0034
jmp [0xFD0012]
inc.b (4,x)
dec.w [4,y]
clr.p (-s)
neg.l (d0, s)
com.b [d1, x]
jsr (45, d0)
psh cch
@end smallexample
@node S12Z-Directives
@section Assembler Directives
@cindex assembler directives, S12Z
@node S12Z-opcodes
@section Opcodes
@cindex S12Z opcodes
@cindex opcodes, S12Z
@cindex instruction set, S12Z

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#objdump: -d
#name:
#source: abs.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 40 abs d2
2: 1b 41 abs d3
4: 1b 42 abs d4
6: 1b 43 abs d5
8: 1b 44 abs d0
a: 1b 45 abs d1
c: 1b 46 abs d6
e: 1b 47 abs d7

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@ -0,0 +1,8 @@
abs d2
abs d3
abs d4
abs d5
abs d0
abs d1
abs d6
abs d7

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#objdump: -d
#name:
#source: adc-imm.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 50 12 34 adc d2, #4660
4: 1b 51 12 34 adc d3, #4660
8: 1b 52 12 34 adc d4, #4660
c: 1b 53 12 34 adc d5, #4660
10: 1b 54 12 adc d0, #18
13: 1b 55 34 adc d1, #52
16: 1b 56 00 56 adc d6, #5666970
1a: 78 9a
1c: 1b 57 00 98 adc d7, #9991764
20: 76 54

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@ -0,0 +1,8 @@
adc d2, #0x1234
adc d3, #0x1234
adc d4, #0x1234
adc d5, #0x1234
adc d0, #0x12
adc d1, #0x34
adc d6, #0x56789A
adc d7, #0x987654

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#objdump: -d
#name:
#source: adc-opr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 64 c5 21 adc d0, \[-223,x\]
4: 1b 65 e2 ff adc d1, \(-2000,s\)
8: f8 30
a: 1b 60 c7 adc d2, \(x-\)
d: 1b 61 f3 adc d3, \(\+y\)
10: 1b 62 bb adc d4, d5
13: 1b 63 3e ce adc d5, 16078
17: 1b 66 fe 01 adc d6, \[73056\]
1b: 1d 60
1d: 1b 67 8a adc d7, \(d4,x\)

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@ -0,0 +1,9 @@
adc d0, [-223,x]
adc d1, (-2000, s)
adc d2, (x-)
adc d3, (+y)
adc d4, d5
adc d5, 16078
adc d6, [73056]
adc d7, (d4,x)

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: add-imm.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <start>:
0: 50 12 34 add d2, #4660
3: 51 12 34 add d3, #4660
6: 52 12 34 add d4, #4660
9: 53 12 34 add d5, #4660
c: 54 12 add d0, #18
e: 55 34 add d1, #52
10: 56 00 56 78 add d6, #5666970
14: 9a
15: 57 00 98 76 add d7, #9991764
19: 54

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@ -0,0 +1,8 @@
start: add d2, #0x1234
add d3, #0x1234
add d4, #0x1234
add d5, #0x1234
add d0, #0x12
add d1, #0x34
add d6, #0x56789A
add d7, #0x987654

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: add-opr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 64 c5 21 add d0, \[-223,x\]
3: 65 e2 00 75 add d1, \(30000,s\)
7: 30
8: 60 c7 add d2, \(x-\)
a: 61 f3 add d3, \(\+y\)
c: 62 bf add d4, d7
e: 63 17 be add d5, 6078
11: 66 fe 01 1d add d6, \[73056\]
15: 60
16: 67 8a add d7, \(d4,x\)

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@ -0,0 +1,9 @@
add d0, [-223,x]
add d1, (30000, s)
add d2, (x-)
add d3, (+y)
add d4, d7
add d5, 6078
add d6, [73056]
add d7, (d4,x)

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: and-imm.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <start>:
0: 58 12 34 and d2, #4660
3: 59 12 34 and d3, #4660
6: 5a 12 34 and d4, #4660
9: 5b 12 34 and d5, #4660
c: 5c 12 and d0, #18
e: 5d 34 and d1, #52
10: 5e 56 78 9a and d6, #1450744508
14: bc
15: 5f 98 76 54 and d7, #-1737075662
19: 32

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start: and d2, #0x1234
and d3, #0x1234
and d4, #0x1234
and d5, #0x1234
and d0, #0x12
and d1, #0x34
and d6, #0x56789ABC
and d7, #-1737075662

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@ -0,0 +1,22 @@
#objdump: -d
#name:
#source: and-opr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 6c c4 17 and d0, \[23,x\]
3: 6d d2 ff 8a and d1, \(-30000,y\)
7: d0
8: 68 c7 and d2, \(x-\)
a: 69 f3 and d3, \(\+y\)
c: 6a bb and d4, d5
e: 6b fa 23 ca and d5, 2345678
12: ce
13: 6e fe 01 e2 and d6, \[123456\]
17: 40
18: 6f ac and d7, \(d0,s\)

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@ -0,0 +1,9 @@
and d0, [23,x]
and d1, (-30000, y)
and d2, (x-)
and d3, (+y)
and d4, d5
and d5, 2345678
and d6, [123456]
and d7, (d0,s)

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@ -0,0 +1,13 @@
#objdump: -d
#name:
#source: and-or-cc.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <xx>:
0: ce 7b andcc #123
2: de 20 orcc #32

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@ -0,0 +1,2 @@
xx: andcc #123
orcc #32

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@ -0,0 +1,13 @@
#objdump: -d
#name:
#source: bfext-special.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 0f 75 a3 bfext.w \(45,d1\), d7, #13:3
4: 85 00 2d

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@ -0,0 +1,2 @@
bfext.w (45,d1), d7, #13:3

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@ -0,0 +1,47 @@
#objdump: -d
#name:
#source: bfext.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 0c 14 bfext d0, d1, d2
3: 1b 0d 21 17 bfext d1, d2, #8:23
7: 1b 08 41 e3 bfext.b d2, \(\+x\), d3
b: 1b 09 46 c4 bfext.w d3, \[123,x\], d4
f: 7b
10: 1b 0a 4b ac bfext.p d4, \(d0,s\), d5
14: 1b 0b 4c 84 bfext.l d5, \(45,d0\), d2
18: 00 2d
1a: 1b 0e 51 84 bfext.b \(45,d0\), d6, d3
1e: 00 2d
20: 1b 0f 54 c4 bfext.w \[45,x\], d7, d2
24: 2d
25: 1b 0c 61 a2 bfext.b d0, \(45,d1\), #13:2
29: 85 00 2d
2c: 1b 0f 75 a3 bfext.w \(45,d1\), d7, #13:3
30: 85 00 2d
33: 1b 0f 58 c6 bfext.p \[451,x\], d7, d2
37: 00 01 c3
3a: 1b 0c 94 bfins d0, d1, d2
3d: 1b 0d a1 17 bfins d1, d2, #8:23
41: 1b 08 c1 e3 bfins.b d2, \(\+x\), d3
45: 1b 09 c6 c4 bfins.w d3, \[123,x\], d4
49: 7b
4a: 1b 0a cb ac bfins.p d4, \(d0,s\), d5
4e: 1b 0b cc 84 bfins.l d5, \(45,d0\), d2
52: 00 2d
54: 1b 0e d1 84 bfins.b \(45,d0\), d6, d3
58: 00 2d
5a: 1b 0f d4 c4 bfins.w \[45,x\], d7, d2
5e: 2d
5f: 1b 0c e1 a2 bfins.b d0, \(45,d1\), #13:2
63: 85 00 2d
66: 1b 0f f5 a3 bfins.w \(45,d1\), d7, #13:3
6a: 85 00 2d
6d: 1b 0f d8 c6 bfins.p \[451,x\], d7, d2
71: 00 01 c3

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@ -0,0 +1,23 @@
bfext d0, d1, d2
bfext d1, d2, #8:23
bfext.b d2, (+x), d3
bfext.w d3, [123,x], d4
bfext.p d4, (d0, s), d5
bfext.l d5, (45,d0), d2
bfext.b (45,d0), d6, d3
bfext.w [45,x], d7, d2
bfext.b d0, (45,d1), #13:2
bfext.w (45,d1), d7, #13:3
bfext.p [451,x], d7, d2
bfins d0, d1, d2
bfins d1, d2, #8:23
bfins.b d2, (+x), d3
bfins.w d3, [123,x], d4
bfins.p d4, (d0, s), d5
bfins.l d5, (45,d0), d2
bfins.b (45,d0), d6, d3
bfins.w [45,x], d7, d2
bfins.b d0, (45,d1), #13:2
bfins.w (45,d1), d7, #13:3
bfins.p [451,x], d7, d2

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@ -0,0 +1,26 @@
#objdump: -d
#name:
#source: bit-manip.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: ec 1c bclr d0, #3
2: ed 25 bset d1, #4
4: ee 28 btgl d2, #5
6: ec b1 b9 bclr d3, d5
9: ed e1 ba bset d4, d6
c: ee f1 bb btgl d5, d7
f: ec a0 c0 22 bclr.b \(34,x\), #2
13: ec c3 ff bclr.w \(s\+\), #12
16: ec fd e0 38 bclr.l \(56,s\), d7
1a: ed d0 c4 22 bset.b \[34,x\], #5
1e: ed db fb bset.l \(-s\), #29
21: ed f5 c0 9c bset.w \(156,x\), d7
25: ee d0 c4 22 btgl.b \[34,x\], #5
29: ee f3 fb btgl.w \(-s\), #15
2c: ee fd f0 0f btgl.l \(15,p\), d7

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@ -0,0 +1,16 @@
bclr d0, #3
bset d1, #4
btgl d2, #5
bclr d3, d5
bset d4, d6
btgl d5, d7
bclr.b (34,x), #2
bclr.w (s+), #12
bclr.l (56,s), d7
bset.b [34,x], #5
bset.l (-s), #29
bset.w (156,x), d7
btgl.b [34,x], #5
btgl.w (-s), #15
btgl.l (15,p), d7

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@ -0,0 +1,33 @@
#objdump: -d
#name:
#source: bit.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 58 fc 84 bit d2, #-892
4: 1b 59 ef 32 bit d3, #-4302
8: 1b 5f 00 01 bit d7, #123456
c: e2 40
e: 1b 5b 04 d2 bit d5, #1234
12: 1b 5c 7b bit d0, #123
15: 1b 5d 22 bit d1, #34
18: 1b 5e ff ff bit d6, #-56789
1c: 22 2b
1e: 1b 5a 22 3d bit d4, #8765
22: 1b 6c d5 21 bit d0, \[-223,y\]
26: 1b 6d f2 00 bit d1, \(34000,p\)
2a: 84 d0
2c: 1b 68 fb bit d2, \(-s\)
2f: 1b 59 00 04 bit d3, #4
33: 1b 6a bc bit d4, d0
36: 1b 6b f9 4c bit d5, 85178
3a: ba
3b: 1b 6e fe 00 bit d6, \[15256\]
3f: 3b 98
41: 1b 6f 8b bit d7, \(d5,x\)
44: 1b 69 f3 bit d3, \(\+y\)

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@ -0,0 +1,17 @@
bit d2, #-892
bit d3, #-4302
bit d7, #123456
bit d5, #1234
bit d0, #123
bit d1, #34
bit d6, #-56789
bit d4, #8765
bit d0, [-223,y]
bit d1, (34000, p)
bit d2, (-s)
bit d3, #4
bit d4, d0
bit d5, 85178
bit d6, [15256]
bit d7, (d5, x)
bit d3, (+y)

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@ -0,0 +1,23 @@
#objdump: -d
#name: pc_relative expressions defined at assembly time
#source: bra-expression-defined.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <loop-0x11>:
0: 01 nop
1: 01 nop
2: 20 80 19 bra \*\+25
5: 01 nop
6: 02 c0 bc 80 brclr.b d0, #4, \*\+31
a: 1f
b: 01 nop
c: 0b 06 80 23 tbne d6, \*\+35
10: 01 nop
00000011 <loop>:
11: 01 nop

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@ -0,0 +1,11 @@
nop
nop
bra loop+10
nop
brclr.b d0, #4, loop+20
nop
tbne d6, loop+30
nop
loop:
nop

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@ -0,0 +1,24 @@
#objdump: -dr
#name: pc_relative expressions without a definition
#source: bra-expression-undef.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 01 nop
1: 01 nop
2: 20 80 0b bra \*\+11
3: R_S12Z_PCREL_7_15 loop\+0x8000
5: 01 nop
6: 02 c0 bc 80 brclr.b d0, #4, \*\+23
a: 17
9: R_S12Z_PCREL_7_15 loop\+0x18000
b: 01 nop
c: 0b 06 80 20 tbne d6, \*\+32
e: R_S12Z_PCREL_7_15 loop\+0x10000
10: 01 nop

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@ -0,0 +1,9 @@
nop
nop
bra loop+10
nop
brclr.b d0, #4, loop+20
nop
tbne d6, loop+30
nop

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@ -0,0 +1,34 @@
#objdump: -d
#name:
#source: bra.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <L1>:
0: 20 80 0f bra L4
00000003 <L2>:
3: 21 ff fd bsr L1
6: 22 ff fa bhi L1
00000009 <L3>:
9: 23 80 00 bls L3
c: 24 ff f4 bcc L1
0000000f <L4>:
f: 25 ff f4 bcs L2
12: 26 ff f7 bne L3
15: 27 ff fa beq L4
18: 28 ff f7 bvc L4
1b: 29 ff e8 bvs L2
1e: 2a ff e2 bpl L1
21: 2b ff e2 bmi L2
24: 2c ff dc bge L1
27: 2d ff e8 blt L4
2a: 2e ff df bgt L3
2d: 2f ff d3 ble L1
30: 20 02 bra \*\+2
32: 20 7c bra \*-4

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@ -0,0 +1,20 @@
L1: bra L4
L2: bsr L1
bhi L1
L3: bls L3
bcc L1
L4: bcs L2
bne L3
beq L4
bvc L4
bvs L2
bpl L1
bmi L2
bge L1
blt L4
bgt L3
ble L1
bra *+2
bra *-4

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#objdump: -dt
#name:
#source: brclr-symbols.s
dump.o: file format elf32-s12z
SYMBOL TABLE:
00000000 l d .text 00000000 .text
00000000 l d .data 00000000 .data
00000000 l d .bss 00000000 .bss
00000001 l .text 00000000 foo
Disassembly of section .text:
00000000 <foo-0x1>:
0: 01 nop
00000001 <foo>:
1: 01 nop
2: 01 nop
3: 02 0c ff fe brclr d0, #1, foo
7: 03 81 bd ff brset d1, d2, foo
b: fa
c: 02 a0 e7 ff brclr.b \(x\+\), #2, foo
10: f5
11: 03 c1 84 00 brset.b \(23,d0\), d0, foo
15: 17 ff f0
18: 02 a0 03 86 brclr.b 902, #2, foo
1c: ff e9

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@ -0,0 +1,9 @@
nop
foo:
nop
nop
brclr d0, #1, foo
brset d1, d2, foo
brclr.b (x+), #2, foo
brset.b (23,d0), d0, foo
brclr.b 902, #2, foo

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@ -0,0 +1,23 @@
#objdump: -d
#name:
#source: brset-clr-opr-imm-rel.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 03 c0 e4 2d brset.b \[45,s\], #4, \*\+3
4: 03
5: 03 e3 e6 00 brset.w \[345,s\], #14, \*\+32
9: 01 59 20
c: 03 99 e2 00 brset.l \(345,s\), #9, \*\+309
10: 01 59 81 35
14: 02 c0 e6 00 brclr.b \[345,s\], #4, \*\+3
18: 01 59 03
1b: 02 f3 e6 00 brclr.w \[345,s\], #15, \*\+3087
1f: 01 59 8c 0f
23: 02 fb e6 00 brclr.l \[345,s\], #31, \*\+3
27: 01 59 03

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@ -0,0 +1,7 @@
brset.b [45,s], #4, *+3
brset.w [345,s], #14, *+32
brset.l (345,s), #9, *+309
brclr.b [345,s], #4, *+3
brclr.w [345,s], #15, *+3087
brclr.l [345,s], #31, *+3

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: brset-clr-opr-reg-rel.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <L1-0x6>:
0: 02 85 d0 22 brclr.w \(34,y\), d2, \*\+3034
4: 8b da
00000006 <L1>:
6: 03 c1 d3 81 brset.b \(-y\), d0, \*\+434
a: b2
b: 03 9d e3 88 brset.l \(\+x\), d3, \*\+2134
f: 56
10: 02 ad c4 22 brclr.l \[34,x\], d4, L1
14: ff f6

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@ -0,0 +1,5 @@
brclr.w (34,y), d2, *+3034
L1: brset.b (-y), d0, *+434
brset.l (+x), d3, *+2134
brclr.l [34,x], d4, L1

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@ -0,0 +1,24 @@
#objdump: -d
#name:
#source: brset-clr-reg-imm-rel.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <L1>:
0: 03 10 05 brset d2, #2, \*\+5
3: 03 19 17 brset d3, #3, \*\+23
6: 03 11 71 brset d3, #2, \*-15
9: 03 40 43 brset d2, #8, \*-61
c: 03 40 fd 01 brset d2, #8, \*-767
10: 03 6e fd 01 brset d6, #13, \*-767
00000014 <L2>:
14: 02 10 05 brclr d2, #2, \*\+5
17: 02 19 17 brclr d3, #3, \*\+23
1a: 02 11 fc c0 brclr d3, #2, \*-832
1e: 02 40 43 brclr d2, #8, \*-61
21: 02 40 fd 01 brclr d2, #8, \*-767

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@ -0,0 +1,12 @@
L1: brset d2, #2, *+5
brset d3, #3, *+23
brset d3, #2, *-15
brset d2, #8, *-61
brset d2, #8, *-767
brset d6, #13, *-767
L2: brclr d2, #2, *+5
brclr d3, #3, *+23
brclr d3, #2, *-832
brclr d2, #8, *-61
brclr d2, #8, *-767

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@ -0,0 +1,19 @@
#objdump: -d
#name:
#source: brset-clr-reg-reg-rel.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 03 e1 bb 2d brset d5, d6, \*\+45
4: 02 d1 b8 6f brclr d2, d1, \*-17
8: 03 91 be ff brset d6, d3, \*-90
c: a6
d: 02 f1 bc ff brclr d0, d7, \*-90
11: a6
12: 02 81 bd ff brclr d1, d2, \*-190
16: 42

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@ -0,0 +1,6 @@
brset d5, d6, *+45
brclr d2, d1, *-17
brset d6, d3, *-90
brclr d0, d7, *-90
brclr d1, d2, *-190

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@ -0,0 +1,19 @@
#objdump: -d
#name:
#source: clb.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 91 47 clb d0, d7
3: 1b 91 56 clb d1, d6
6: 1b 91 03 clb d2, d5
9: 1b 91 12 clb d3, d4
c: 1b 91 21 clb d4, d3
f: 1b 91 30 clb d5, d2
12: 1b 91 65 clb d6, d1
15: 1b 91 74 clb d7, d0

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@ -0,0 +1,8 @@
clb d0, d7
clb d1, d6
clb d2, d5
clb d3, d4
clb d4, d3
clb d5, d2
clb d6, d1
clb d7, d0

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@ -0,0 +1,15 @@
#objdump: -d
#name:
#source: clr-opr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: bc ff clr.b \(s\+\)
2: bd c0 2d clr.w \(45,x\)
5: be f9 e2 32 clr.p 123442
9: bf d4 03 clr.l \[3,y\]

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@ -0,0 +1,5 @@
clr.b (s+)
clr.w (45,x)
clr.p 123442
clr.l [3,y]

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: clr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <L1>:
0: 38 clr d2
1: 39 clr d3
2: 3a clr d4
3: 3b clr d5
4: 3c clr d0
5: 3d clr d1
6: 3e clr d6
7: 3f clr d7
8: 9a clr x
9: 9b clr y

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@ -0,0 +1,10 @@
L1: clr d2
clr d3
clr d4
clr d5
clr d0
clr d1
clr d6
clr d7
clr x
clr y

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@ -0,0 +1,23 @@
#objdump: -d
#name:
#source: cmp-imm.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <here>:
0: e4 12 cmp d0, #18
2: e5 34 cmp d1, #52
4: e0 34 56 cmp d2, #13398
7: e1 34 56 cmp d3, #13398
a: e2 34 56 cmp d4, #13398
d: e3 34 56 cmp d5, #13398
10: e6 00 34 56 cmp d6, #3430008
14: 78
15: e7 00 34 56 cmp d7, #3430008
19: 78
1a: e8 aa bb cc cmp x, #-5588020
1e: e9 dd ee ff cmp y, #-2232577

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@ -0,0 +1,12 @@
here: cmp d0, #0x12
cmp d1, #0x34
cmp d2, #0x3456
cmp d3, #0x3456
cmp d4, #0x3456
cmp d5, #0x3456
cmp d6, #0x345678
cmp d7, #0x345678
cmp x, #-5588020
cmp y, #-2232577

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: cmp-opr-inc.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: f0 e3 cmp d2, \(\+x\)
2: f1 f3 cmp d3, \(\+y\)
4: f2 c3 cmp d4, \(-x\)
6: f3 d3 cmp d5, \(-y\)
8: f4 fb cmp d0, \(-s\)
a: f6 ff cmp d6, \(s\+\)
c: f8 d7 cmp x, \(y-\)
e: f8 c7 cmp x, \(x-\)
10: f9 f7 cmp y, \(y\+\)
12: f9 e7 cmp y, \(x\+\)

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@ -0,0 +1,11 @@
;; Pre/Post increment/decrement xys
cmp d2, (+x)
cmp d3, (+y)
cmp d4, (-x)
cmp d5, (-y)
cmp d0, (-s)
cmp d6, (s+)
cmp x, (y-)
cmp x, (x-)
cmp y, (y+)
cmp y, (x+)

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@ -0,0 +1,19 @@
#objdump: -d
#name:
#source: cmp-opr-rdirect.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: f0 ad cmp d2, \(d1,s\)
2: f1 88 cmp d3, \(d2,x\)
4: f2 89 cmp d4, \(d3,x\)
6: f3 99 cmp d5, \(d3,y\)
8: f4 8a cmp d0, \(d4,x\)
a: f5 8b cmp d1, \(d5,x\)
c: f6 8e cmp d6, \(d6,x\)
e: f7 8f cmp d7, \(d7,x\)

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@ -0,0 +1,9 @@
;;; Direct register offset
cmp d2, (d1,s)
cmp d3, (d2,x)
cmp d4, (d3,x)
cmp d5, (d3,y)
cmp d0, (d4,x)
cmp d1, (d5,x)
cmp d6, (d6,x)
cmp d7, (d7,x)

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@ -0,0 +1,19 @@
#objdump: -d
#name:
#source: cmp-opr-reg.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: f0 b8 cmp d2, d2
2: f1 b9 cmp d3, d3
4: f2 ba cmp d4, d4
6: f3 bb cmp d5, d5
8: f4 bc cmp d0, d0
a: f5 bd cmp d1, d1
c: f6 be cmp d6, d6
e: f7 bf cmp d7, d7

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@ -0,0 +1,9 @@
;; Register as operand
cmp d2, d2
cmp d3, d3
cmp d4, d4
cmp d5, d5
cmp d0, d0
cmp d1, d1
cmp d6, d6
cmp d7, d7

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@ -0,0 +1,19 @@
#objdump: -d
#name:
#source: cmp-opr-rindirect.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: f0 dd cmp d2, \[d1,y\]
2: f1 dd cmp d3, \[d1,y\]
4: f2 dc cmp d4, \[d0,y\]
6: f3 dc cmp d5, \[d0,y\]
8: f4 ce cmp d0, \[d6,x\]
a: f5 ce cmp d1, \[d6,x\]
c: f6 ce cmp d6, \[d6,x\]
e: f7 cf cmp d7, \[d7,x\]

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@ -0,0 +1,9 @@
;;; Indirect register offset
cmp d2, [d1,y]
cmp d3, [d1,y]
cmp d4, [d0,y]
cmp d5, [d0,y]
cmp d0, [d6,x]
cmp d1, [d6,x]
cmp d6, [d6,x]
cmp d7, [d7,x]

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@ -0,0 +1,21 @@
#objdump: -d
#name:
#source: cmp-opr-sxe4.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: e0 ff ff cmp d2, #-1
3: e1 00 01 cmp d3, #1
6: e2 00 02 cmp d4, #2
9: e3 00 03 cmp d5, #3
c: e4 0e cmp d0, #14
e: e5 0f cmp d1, #15
10: e6 00 00 00 cmp d6, #4
14: 04
15: e7 00 00 00 cmp d7, #10
19: 0a

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@ -0,0 +1,10 @@
;; Short immediate forms
cmp d2, #-1
cmp d3, #1
cmp d4, #2
cmp d5, #3
cmp d0, #14
cmp d1, #15
cmp d6, #4
cmp d7, #10

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@ -0,0 +1,19 @@
#objdump: -d
#name:
#source: cmp-opr-xys.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: f0 61 cmp d2, \(1,s\)
2: f1 42 cmp d3, \(2,x\)
4: f2 43 cmp d4, \(3,x\)
6: f3 53 cmp d5, \(3,y\)
8: f4 44 cmp d0, \(4,x\)
a: f5 45 cmp d1, \(5,x\)
c: f6 46 cmp d6, \(6,x\)
e: f7 47 cmp d7, \(7,x\)

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@ -0,0 +1,9 @@
;; Constant offset from xys
cmp d2, (1,s)
cmp d3, (2,x)
cmp d4, (3,x)
cmp d5, (3,y)
cmp d0, (4,x)
cmp d1, (5,x)
cmp d6, (6,x)
cmp d7, (7,x)

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@ -0,0 +1,27 @@
#objdump: -d
#name:
#source: cmp-s-imm.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 04 00 00 cmp s, #0
4: 00
5: 1b 02 71 cmp s, #1
8: 1b 02 70 cmp s, #-1
b: 1b 04 00 00 cmp s, #255
f: ff
10: 1b 04 ff ff cmp s, #-256
14: 00
15: 1b 04 00 7f cmp s, #32767
19: ff
1a: 1b 04 ff 80 cmp s, #-32768
1e: 00
1f: 1b 04 07 ff cmp s, #524287
23: ff
24: 1b 04 f8 00 cmp s, #-524288
28: 00

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@ -0,0 +1,10 @@
cmp s, #0
cmp s, #1
cmp s, #-1
cmp s, #255
cmp s, #-256
cmp s, #32767
cmp s, #-32768
cmp s, #524287
cmp s, #-524288

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@ -0,0 +1,25 @@
#objdump: -d
#name:
#source: cmp-s-opr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 1b 02 e0 43 cmp s, \(67,s\)
4: 1b 02 e3 cmp s, \(\+x\)
7: 1b 02 8c cmp s, \(d0,x\)
a: 1b 02 dd cmp s, \[d1,y\]
d: 1b 02 f2 00 cmp s, \(2134,p\)
11: 08 56
13: 1b 02 f6 00 cmp s, \[2134,p\]
17: 08 56
19: 1b 02 fa 0f cmp s, 987654
1d: 12 06
1f: 1b 02 e6 08 cmp s, \[565543,s\]
23: a1 27
25: 1b 02 80 04 cmp s, \(1233,d2\)
29: d1

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@ -0,0 +1,10 @@
cmp s, (67,s)
cmp s, (+x)
cmp s, (d0,x)
cmp s, [d1,y]
cmp s, (2134,p)
cmp s, [2134,p]
cmp s, 987654
cmp s, [565543,s]
cmp s, (1233, d2)

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@ -0,0 +1,12 @@
#objdump: -d
#name:
#source: cmp-xy.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: fc cmp x, y

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@ -0,0 +1 @@
cmp x, y

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@ -0,0 +1,15 @@
#objdump: -d
#name:
#source: com-opr.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: cc df com.b \[d7,y\]
2: cd fe 00 1f com.w \[8134\]
6: c6
7: cf ae com.l \(d6,s\)

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@ -0,0 +1,3 @@
com.b [d7, y]
com.w [8134]
com.l (d6, s)

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@ -0,0 +1,18 @@
#objdump: -d
#name:
#source: complex-shifts.s
dump.o: file format elf32-s12z
Disassembly of section .text:
00000000 <.text>:
0: 14 73 e3 e6 lsl.l d0, \(\+x\), \[345,s\]
4: 00 01 59
7: 13 32 8e fb lsr.p d5, \(d6,x\), \(-s\)
b: 17 f1 f4 2d asl.w d7, \[45,p\], \(278,y\)
f: d2 00 01 16
13: 12 b0 84 00 asr.b d4, \(145,d0\), \(d0,s\)
17: 91 ac

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