OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add support for Xilinx MicroBlaze processor.

Browse Source 
* bfd/Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}.
        * bfd/Makefile.in: Same.
        * bfd/archures.c: Add bfd_arch_microblaze.
        * bfd/bfd-in2.h: Regenerate.
        * bfd/config.bfd: Add microblaze target.
        * bfd/configure: Add bfd_elf32_microblaze_vec target.
        * bfd/configure.in: Same.
        * bfd/cpu-microblaze.c: New.
        * bfd/elf32-microblaze.c: New.
        * bfd/libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc().
        * bfd/libbfd.h: Regenerate.
        * bfd/reloc.c: Add MICROBLAZE relocations.
        * bfd/section.c: Add struct relax_table and relax_count to section.
        * bfd/targets.c: Add bfd_elf32_microblaze_vec.
        * binutils/MAINTAINERS: Add self as maintainer.
        * binutils/readelf.c: Include elf/microblaze.h, add EM_MICROBLAZE &
        EM_MICROBLAZE_OLD to guess_is_rela(), dump_relocations(),
        get_machine_name().
        * config.sub: Add microblaze target.
        * configure: Same.
        * configure.ac: Same.
        * gas/Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to
        TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add
        DEP_microblaze_elf target.
        * gas/Makefile.in: Same.
        * gas/config/tc-microblaze.c: Add MicroBlaze assembler.
        * gas/config/tc-microblaze.h: Add header for tc-microblaze.c.
        * gas/configure: Add microblaze target.
        * gas/configure.in: Same.
        * gas/configure.tgt: Same.
        * gas/doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS.
        * gas/doc/Makefile.in: Same.
        * gas/doc/all.texi: Set MICROBLAZE.
        * gas/doc/as.texinfo: Add MicroBlaze doc links.
        * gas/doc/c-microblaze.texi: New MicroBlaze docs.
        * include/dis-asm.h: Decl print_insn_microblaze().
        * include/elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD.
        * include/elf/microblaze.h: New reloc definitions.
        * ld/Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to
        ALL_EMULATIONS, targets.
        * ld/Makefile.in: Same.
        * ld/configure.tgt: Add microblaze*-linux*, microblaze* targets.
        * ld/emulparams/elf32mb_linux.sh: New.
        * ld/emulparams/elf32microblaze.sh. New.
        * ld/scripttempl/elfmicroblaze.sc: New.
        * opcodes/Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to
        CFILES, microblaze-dis.lo to ALL_MACHINES, targets.
        * opcodes/Makefile.in: Same.
        * opcodes/configure: Add bfd_microblaze_arch target.
        * opcodes/configure.in: Same.
        * opcodes/disassemble.c: Define ARCH_microblaze, return
        print_insn_microblaze().
        * opcodes/microblaze-dis.c: New MicroBlaze disassembler.
        * opcodes/microblaze-opc.h: New MicroBlaze opcode definitions.
        * opcodes/microblaze-opcm.h: New MicroBlaze opcode types.
This commit is contained in:
Nick Clifton 2009-08-06 17:38:04 +00:00
parent 9961db38d4
commit 7ba29e2a41
55 changed files with 7428 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
bfd/ChangeLog
View File

@ -1,3 +1,20 @@
2009-08-06 Michael Eager <eager@eagercon.com>
* Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}.
* Makefile.in: Regenerate.
* archures.c: Add bfd_arch_microblaze.
* bfd-in2.h: Regenerate.
* config.bfd: Add microblaze target.
* configure.in: Add bfd_elf32_microblaze_vec target.
* configure: Regenerate.
* cpu-microblaze.c: New.
* elf32-microblaze.c: New.
* libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc().
* libbfd.h: Regenerate.
* reloc.c: Add MICROBLAZE relocations.
* section.c: Add struct relax_table and relax_count to section.
* targets.c: Add bfd_elf32_microblaze_vec.
2009-08-06 Jakub Jelinek <jakub@redhat.com>
Alan Modra <amodra@bigpond.net.au>

19
bfd/Makefile.am
View File

@ -101,6 +101,7 @@ ALL_MACHINES = \
cpu-maxq.lo \
cpu-mcore.lo \
cpu-mep.lo \
cpu-microblaze.lo \
cpu-mips.lo \
cpu-mmix.lo \
cpu-moxie.lo \
@ -171,6 +172,7 @@ ALL_MACHINES_CFILES = \
cpu-maxq.c \
cpu-mcore.c \
cpu-mep.c \
cpu-microblaze.c \
cpu-mips.c \
cpu-mmix.c \
cpu-moxie.c \
@ -291,6 +293,7 @@ BFD32_BACKENDS = \
elf32-m88k.lo \
elf32-mcore.lo \
elf32-mep.lo \
elf32-microblaze.lo \
elf32-mips.lo \
elf32-moxie.lo \
elf32-msp430.lo \
@ -474,6 +477,7 @@ BFD32_BACKENDS_CFILES = \
elf32-m88k.c \
elf32-mcore.c \
elf32-mep.c \
elf32-microblaze.c \
elf32-mips.c \
elf32-moxie.c \
elf32-msp430.c \
@ -1387,6 +1391,10 @@ cpu-mep.lo: \
cpu-mep.c \
$(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h
cpu-microblaze.lo: \
cpu-microblaze.c $\
$(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h
cpu-mips.lo: \
cpu-mips.c \
$(INCDIR)/filenames.h \
@ -2844,6 +2852,17 @@ elflink.lo: \
$(INCDIR)/objalloc.h \
$(INCDIR)/safe-ctype.h \
elf-bfd.h
elf32-microblaze.lo: \
elf32-microblaze.c \
$(INCDIR)/filenames.h \
$(INCDIR)/bfdlink.h \
genlink.h \
elf-bfd.h \
$(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h \
$(INCDIR)/elf/reloc-macros.h \
elf32-target.h
elfxx-mips.lo: \
elfxx-mips.c \
$(INCDIR)/bfdlink.h \

19
bfd/Makefile.in
View File

@ -371,6 +371,7 @@ ALL_MACHINES = \
cpu-maxq.lo \
cpu-mcore.lo \
cpu-mep.lo \
cpu-microblaze.lo \
cpu-mips.lo \
cpu-mmix.lo \
cpu-moxie.lo \
@ -441,6 +442,7 @@ ALL_MACHINES_CFILES = \
cpu-maxq.c \
cpu-mcore.c \
cpu-mep.c \
cpu-microblaze.c \
cpu-mips.c \
cpu-mmix.c \
cpu-moxie.c \
@ -562,6 +564,7 @@ BFD32_BACKENDS = \
elf32-m88k.lo \
elf32-mcore.lo \
elf32-mep.lo \
elf32-microblaze.lo \
elf32-mips.lo \
elf32-moxie.lo \
elf32-msp430.lo \
@ -745,6 +748,7 @@ BFD32_BACKENDS_CFILES = \
elf32-m88k.c \
elf32-mcore.c \
elf32-mep.c \
elf32-microblaze.c \
elf32-mips.c \
elf32-moxie.c \
elf32-msp430.c \
@ -1988,6 +1992,10 @@ cpu-mep.lo: \
cpu-mep.c \
$(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h
cpu-microblaze.lo: \
cpu-microblaze.c $\
$(INCDIR)/filenames.h \
$(INCDIR)/hashtab.h
cpu-mips.lo: \
cpu-mips.c \
$(INCDIR)/filenames.h \
@ -3445,6 +3453,17 @@ elflink.lo: \
$(INCDIR)/objalloc.h \
$(INCDIR)/safe-ctype.h \
elf-bfd.h
elf32-microblaze.lo: \
elf32-microblaze.c \
$(INCDIR)/filenames.h \
$(INCDIR)/bfdlink.h \
genlink.h \
elf-bfd.h \
$(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h \
$(INCDIR)/elf/reloc-macros.h \
elf32-target.h
elfxx-mips.lo: \
elfxx-mips.c \
$(INCDIR)/bfdlink.h \

3
bfd/archures.c
View File

@ -422,6 +422,7 @@ DESCRIPTION
.#define bfd_mach_r800 11 {* R800: successor with multiplication. *}
. bfd_arch_lm32, {* Lattice Mico32 *}
.#define bfd_mach_lm32 1
. bfd_arch_microblaze,{* Xilinx MicroBlaze. *}
. bfd_arch_last
. };
*/
@ -496,6 +497,7 @@ extern const bfd_arch_info_type bfd_maxq_arch;
extern const bfd_arch_info_type bfd_mcore_arch;
extern const bfd_arch_info_type bfd_mep_arch;
extern const bfd_arch_info_type bfd_mips_arch;
extern const bfd_arch_info_type bfd_microblaze_arch;
extern const bfd_arch_info_type bfd_mmix_arch;
extern const bfd_arch_info_type bfd_mn10200_arch;
extern const bfd_arch_info_type bfd_mn10300_arch;
@ -570,6 +572,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_maxq_arch,
&bfd_mcore_arch,
&bfd_mep_arch,
&bfd_microblaze_arch,
&bfd_mips_arch,
&bfd_mmix_arch,
&bfd_mn10200_arch,

76
bfd/bfd-in2.h
View File

@ -1405,6 +1405,13 @@ typedef struct bfd_section
section size calculated on a previous linker relaxation pass. */
bfd_size_type rawsize;
/* Relaxation table. */
struct relax_table *relax;
/* Count of used relaxation table entries. */
int relax_count;
/* If this section is going to be output, then this value is the
offset in *bytes* into the output section of the first byte in the
input section (byte ==> smallest addressable unit on the
@ -1494,6 +1501,17 @@ typedef struct bfd_section
} map_head, map_tail;
} asection;
/* Relax table contains information about instructions which can
be removed by relaxation -- replacing a long address with a
short address. */
struct relax_table {
/* Address where bytes may be deleted. */
bfd_vma addr;
/* Number of bytes to be deleted. */
int size;
};
/* These sections are global, and are managed by BFD. The application
and target back end are not permitted to change the values in
these sections. New code should use the section_ptr macros rather
@ -1629,8 +1647,8 @@ extern asection bfd_ind_section;
/* has_tls_get_addr_call, has_gp_reloc, need_finalize_relax, */ \
0, 0, 0, \
\
/* reloc_done, vma, lma, size, rawsize */ \
0, 0, 0, 0, 0, \
/* reloc_done, vma, lma, size, rawsize, relax, relax_count, */ \
0, 0, 0, 0, 0, 0, 0, \
\
/* output_offset, output_section, alignment_power, */ \
0, (struct bfd_section *) &SEC, 0, \
@ -2071,6 +2089,7 @@ enum bfd_architecture
#define bfd_mach_r800 11 /* R800: successor with multiplication. */
bfd_arch_lm32, /* Lattice Mico32 */
#define bfd_mach_lm32 1
bfd_arch_microblaze,/* Xilinx MicroBlaze. */
bfd_arch_last
};
@ -4513,6 +4532,59 @@ BFD_RELOC_MACH_O_PAIR. */
/* Mach-O generic relocations. */
BFD_RELOC_MACH_O_PAIR,
/* This is a 32 bit reloc for the microblaze that stores the
low 16 bits of a value */
BFD_RELOC_MICROBLAZE_32_LO,
/* This is a 32 bit pc-relative reloc for the microblaze that
stores the low 16 bits of a value */
BFD_RELOC_MICROBLAZE_32_LO_PCREL,
/* This is a 32 bit reloc for the microblaze that stores a
value relative to the read-only small data area anchor */
BFD_RELOC_MICROBLAZE_32_ROSDA,
/* This is a 32 bit reloc for the microblaze that stores a
value relative to the read-write small data area anchor */
BFD_RELOC_MICROBLAZE_32_RWSDA,
/* This is a 32 bit reloc for the microblaze to handle
expressions of the form "Symbol Op Symbol" */
BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). No relocation is
done here - only used for relaxing */
BFD_RELOC_MICROBLAZE_64_NONE,
/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative GOT offset */
BFD_RELOC_MICROBLAZE_64_GOTPC,
/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
GOT offset */
BFD_RELOC_MICROBLAZE_64_GOT,
/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative offset into PLT */
BFD_RELOC_MICROBLAZE_64_PLT,
/* This is a 64 bit reloc that stores the 32 bit GOT relative
value in two words (with an imm instruction). The relocation is
relative offset from _GLOBAL_OFFSET_TABLE_ */
BFD_RELOC_MICROBLAZE_64_GOTOFF,
/* This is a 32 bit reloc that stores the 32 bit GOT relative
value in a word. The relocation is relative offset from */
BFD_RELOC_MICROBLAZE_32_GOTOFF,
/* This is used to tell the dynamic linker to copy the value out of
the dynamic object into the runtime process image. */
BFD_RELOC_MICROBLAZE_COPY,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *bfd_reloc_type_lookup

5
bfd/config.bfd
View File

@ -91,6 +91,7 @@ m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;;
m68*) targ_archs=bfd_m68k_arch ;;
m88*) targ_archs=bfd_m88k_arch ;;
maxq*) targ_archs=bfd_maxq_arch ;;
microblaze*) targ_archs=bfd_microblaze_arch ;;
mips*) targ_archs=bfd_mips_arch ;;
or32*) targ_archs=bfd_or32_arch ;;
pdp11*) targ_archs=bfd_pdp11_arch ;;
@ -899,6 +900,10 @@ case "${targ}" in
targ_selvecs=bfd_elf32_mep_little_vec
;;
microblaze*-*)
targ_defvec=bfd_elf32_microblaze_vec
;;
mips*-big-*)
targ_defvec=ecoff_big_vec
targ_selvecs=ecoff_little_vec

1
bfd/configure vendored
View File

@ -21247,6 +21247,7 @@ do
bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
bfd_elf32_mep_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
bfd_elf32_mep_little_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
bfd_elf32_microblaze_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;;
bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;;
bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;;

1
bfd/configure.in
View File

@ -751,6 +751,7 @@ do
bfd_elf32_mcore_little_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;;
bfd_elf32_mep_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
bfd_elf32_mep_little_vec) tb="$tb elf32-mep.lo elf32.lo $elf" ;;
bfd_elf32_microblaze_vec) tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
bfd_elf32_mn10200_vec) tb="$tb elf-m10200.lo elf32.lo $elf" ;;
bfd_elf32_mn10300_vec) tb="$tb elf-m10300.lo elf32.lo $elf" ;;
bfd_elf32_mt_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;;

40
bfd/cpu-microblaze.c Normal file
View File

@ -0,0 +1,40 @@
/* BFD Xilinx MicroBlaze architecture definition
Copyright 2009 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_microblaze_arch =
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_microblaze, /* Architecture. */
0, /* Machine number - 0 for now. */
"microblaze", /* Architecture name. */
"MicroBlaze", /* Printable name. */
3, /* Section align power. */
TRUE, /* Is this the default architecture ? */
bfd_default_compatible, /* Architecture comparison function. */
bfd_default_scan, /* String to architecture conversion. */
NULL /* Next in list. */
};

4
bfd/ecoff.c
View File

@ -62,8 +62,8 @@ static asection bfd_debug_section =
0, 0, 0, 0,
/* has_tls_get_addr_call, has_gp_reloc, need_finalize_relax, */
0, 0, 0,
/* reloc_done, vma, lma, size, rawsize, */
0, 0, 0, 0, 0,
/* reloc_done, vma, lma, size, rawsize, relax, relax_count, */
0, 0, 0, 0, 0, 0, 0,
/* output_offset, output_section, alignment_power, */
0, NULL, 0,
/* relocation, orelocation, reloc_count, filepos, rel_filepos, */

3058
bfd/elf32-microblaze.c Normal file
View File

File diff suppressed because it is too large Load Diff

12
bfd/libbfd.h
View File

@ -2072,6 +2072,18 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_LM32_RELATIVE",
"BFD_RELOC_MACH_O_SECTDIFF",
"BFD_RELOC_MACH_O_PAIR",
"BFD_RELOC_MICROBLAZE_32_LO",
"BFD_RELOC_MICROBLAZE_32_LO_PCREL",
"BFD_RELOC_MICROBLAZE_32_ROSDA",
"BFD_RELOC_MICROBLAZE_32_RWSDA",
"BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
"BFD_RELOC_MICROBLAZE_64_NONE",
"BFD_RELOC_MICROBLAZE_64_GOTPC",
"BFD_RELOC_MICROBLAZE_64_GOT",
"BFD_RELOC_MICROBLAZE_64_PLT",
"BFD_RELOC_MICROBLAZE_64_GOTOFF",
"BFD_RELOC_MICROBLAZE_32_GOTOFF",
"BFD_RELOC_MICROBLAZE_COPY",
"@@overflow: BFD_RELOC_UNUSED@@",
};
#endif

68
bfd/reloc.c
View File

@ -5193,6 +5193,74 @@ ENUM
ENUMDOC
Mach-O generic relocations.
ENUM
BFD_RELOC_MICROBLAZE_32_LO
ENUMDOC
This is a 32 bit reloc for the microblaze that stores the
low 16 bits of a value
ENUM
BFD_RELOC_MICROBLAZE_32_LO_PCREL
ENUMDOC
This is a 32 bit pc-relative reloc for the microblaze that
stores the low 16 bits of a value
ENUM
BFD_RELOC_MICROBLAZE_32_ROSDA
ENUMDOC
This is a 32 bit reloc for the microblaze that stores a
value relative to the read-only small data area anchor
ENUM
BFD_RELOC_MICROBLAZE_32_RWSDA
ENUMDOC
This is a 32 bit reloc for the microblaze that stores a
value relative to the read-write small data area anchor
ENUM
BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
ENUMDOC
This is a 32 bit reloc for the microblaze to handle
expressions of the form "Symbol Op Symbol"
ENUM
BFD_RELOC_MICROBLAZE_64_NONE
ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). No relocation is
done here - only used for relaxing
ENUM
BFD_RELOC_MICROBLAZE_64_GOTPC
ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative GOT offset
ENUM
BFD_RELOC_MICROBLAZE_64_GOT
ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
GOT offset
ENUM
BFD_RELOC_MICROBLAZE_64_PLT
ENUMDOC
This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative offset into PLT
ENUM
BFD_RELOC_MICROBLAZE_64_GOTOFF
ENUMDOC
This is a 64 bit reloc that stores the 32 bit GOT relative
value in two words (with an imm instruction). The relocation is
relative offset from _GLOBAL_OFFSET_TABLE_
ENUM
BFD_RELOC_MICROBLAZE_32_GOTOFF
ENUMDOC
This is a 32 bit reloc that stores the 32 bit GOT relative
value in a word. The relocation is relative offset from
_GLOBAL_OFFSET_TABLE_
ENUM
BFD_RELOC_MICROBLAZE_COPY
ENUMDOC
This is used to tell the dynamic linker to copy the value out of
the dynamic object into the runtime process image.
ENDSENUM
BFD_RELOC_UNUSED
CODE_FRAGMENT

22
bfd/section.c
View File

@ -428,6 +428,13 @@ CODE_FRAGMENT
. section size calculated on a previous linker relaxation pass. *}
. bfd_size_type rawsize;
.
. {* Relaxation table. *}
. struct relax_table *relax;
.
. {* Count of used relaxation table entries. *}
. int relax_count;
.
.
. {* If this section is going to be output, then this value is the
. offset in *bytes* into the output section of the first byte in the
. input section (byte ==> smallest addressable unit on the
@ -517,6 +524,17 @@ CODE_FRAGMENT
. } map_head, map_tail;
.} asection;
.
.{* Relax table contains information about instructions which can
. be removed by relaxation -- replacing a long address with a
. short address. *}
.struct relax_table {
. {* Address where bytes may be deleted. *}
. bfd_vma addr;
.
. {* Number of bytes to be deleted. *}
. int size;
.};
.
.{* These sections are global, and are managed by BFD. The application
. and target back end are not permitted to change the values in
. these sections. New code should use the section_ptr macros rather
@ -652,8 +670,8 @@ CODE_FRAGMENT
. {* has_tls_get_addr_call, has_gp_reloc, need_finalize_relax, *} \
. 0, 0, 0, \
. \
. {* reloc_done, vma, lma, size, rawsize *} \
. 0, 0, 0, 0, 0, \
. {* reloc_done, vma, lma, size, rawsize, relax, relax_count, *} \
. 0, 0, 0, 0, 0, 0, 0, \
. \
. {* output_offset, output_section, alignment_power, *} \
. 0, (struct bfd_section *) &SEC, 0, \

2
bfd/targets.c
View File

@ -625,6 +625,7 @@ extern const bfd_target bfd_elf32_mcore_big_vec;
extern const bfd_target bfd_elf32_mcore_little_vec;
extern const bfd_target bfd_elf32_mep_vec;
extern const bfd_target bfd_elf32_mep_little_vec;
extern const bfd_target bfd_elf32_microblaze_vec;
extern const bfd_target bfd_elf32_mn10200_vec;
extern const bfd_target bfd_elf32_mn10300_vec;
extern const bfd_target bfd_elf32_mt_vec;
@ -959,6 +960,7 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf32_mcore_big_vec,
&bfd_elf32_mcore_little_vec,
&bfd_elf32_mep_vec,
&bfd_elf32_microblaze_vec,
&bfd_elf32_mn10200_vec,
&bfd_elf32_mn10300_vec,
&bfd_elf32_mt_vec,

1
binutils/MAINTAINERS
View File

@ -93,6 +93,7 @@ responsibility among the other maintainers.
MACH-O Tristan Gingold <gingold@adacore.com>
MAXQ Inderpreet Singh <inderpreetb@noida.hcltech.com>
MEP Dave Brolley <brolley@redhat.com>
MICROBLAZE Michael Eager <eager@eagercon.com>
MIPS Eric Christopher <echristo@apple.com>
MMIX Hans-Peter Nilsson <hp@bitrange.com>
MN10300 Eric Christopher <echristo@apple.com>

10
binutils/readelf.c
View File

@ -119,6 +119,7 @@
#include "elf/m68hc11.h"
#include "elf/mcore.h"
#include "elf/mep.h"
#include "elf/microblaze.h"
#include "elf/mips.h"
#include "elf/mmix.h"
#include "elf/mn10200.h"
@ -614,6 +615,8 @@ guess_is_rela (unsigned int e_machine)
case EM_XSTORMY16:
case EM_XTENSA:
case EM_XTENSA_OLD:
case EM_MICROBLAZE:
case EM_MICROBLAZE_OLD:
return TRUE;
case EM_68HC05:
@ -1197,6 +1200,11 @@ dump_relocations (FILE * file,
case EM_CR16_OLD:
rtype = elf_cr16_reloc_type (type);
break;
case EM_MICROBLAZE:
case EM_MICROBLAZE_OLD:
rtype = elf_microblaze_reloc_type (type);
break;
}
if (rtype == NULL)
@ -1865,6 +1873,8 @@ get_machine_name (unsigned e_machine)
case EM_CYGNUS_MEP: return "Toshiba MeP Media Engine";
case EM_CR16:
case EM_CR16_OLD: return "National Semiconductor's CR16";
case EM_MICROBLAZE: return "Xilinx MicroBlaze";
case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze";
default:
snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine);
return buff;

17
gas/ChangeLog
View File

@ -1,3 +1,20 @@
2009-08-06 Michael Eager <eager@eagercon.com>
* Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to
TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add
DEP_microblaze_elf target.
* Makefile.in: Regenerate.
* config/tc-microblaze.c: Add MicroBlaze assembler.
* config/tc-microblaze.h: Add header for tc-microblaze.c.
* configure.in: Add microblaze target.
* configure: Regenerate.
* configure.tgt: Same.
* doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS.
* doc/Makefile.in: Same.
* doc/all.texi: Set MICROBLAZE.
* doc/as.texinfo: Add MicroBlaze doc links.
* doc/c-microblaze.texi: New MicroBlaze docs.
2009-08-06 Nick Clifton <nickc@redhat.com>
* config/tc-arm.c (md_assemble): Call mapping_state from inside a

24
gas/Makefile.am
View File

@ -72,6 +72,7 @@ CPU_TYPES = \
maxq \
mcore \
mep \
microblaze \
mips \
mmix \
mn10200 \
@ -273,6 +274,7 @@ TARGET_CPU_CFILES = \
config/tc-maxq.c \
config/tc-mcore.c \
config/tc-mep.c \
config/tc-microblaze.c \
config/tc-mips.c \
config/tc-mmix.c \
config/tc-mn10200.c \
@ -334,6 +336,7 @@ TARGET_CPU_HFILES = \
config/tc-maxq.h \
config/tc-mcore.h \
config/tc-mep.h \
config/tc-microblaze.h \
config/tc-mips.h \
config/tc-mmix.h \
config/tc-mn10200.h \
@ -1788,6 +1791,19 @@ DEPTC_mep_elf = \
cgen.h \
dwarf2dbg.h \
subsegs.h
DEPTC_microblaze_elf = \
$(srcdir)/config/obj-elf.h \
$(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h \
$(srcdir)/config/tc-microblaze.h \
$(INCDIR)/obstack.h \
$(srcdir)/../opcodes/microblaze-opc.h \
$(INCDIR)/elf/reloc-macros.h \
emul.h \
subsegs.h
DEPTC_mips_coff = \
$(BFDDIR)/elf-bfd.h \
$(BFDDIR)/libcoff.h \
@ -3921,6 +3937,14 @@ DEP_mep_elf = \
$(srcdir)/config/obj-elf.h \
$(srcdir)/config/tc-mep.h \
dwarf2dbg.h
DEP_microblaze_elf = \
$(srcdir)/config/obj-elf.h \
$(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h \
$(srcdir)/config/tc-microblaze.h
DEP_mips_coff = \
$(BFDDIR)/libcoff.h \
$(INCDIR)/bfdlink.h \

26
gas/Makefile.in
View File

@ -335,6 +335,7 @@ CPU_TYPES = \
maxq \
mcore \
mep \
microblaze \
mips \
mmix \
mn10200 \
@ -534,6 +535,7 @@ TARGET_CPU_CFILES = \
config/tc-maxq.c \
config/tc-mcore.c \
config/tc-mep.c \
config/tc-microblaze.c \
config/tc-mips.c \
config/tc-mmix.c \
config/tc-mn10200.c \
@ -595,6 +597,7 @@ TARGET_CPU_HFILES = \
config/tc-maxq.h \
config/tc-mcore.h \
config/tc-mep.h \
config/tc-microblaze.h \
config/tc-mips.h \
config/tc-mmix.h \
config/tc-mn10200.h \
@ -1555,6 +1558,20 @@ DEPTC_mep_elf = \
dwarf2dbg.h \
subsegs.h
DEPTC_microblaze_elf = \
$(srcdir)/config/obj-elf.h \
$(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h \
$(srcdir)/config/tc-microblaze.h \
$(INCDIR)/obstack.h \
$(srcdir)/../opcodes/microblaze-opc.h \
$(INCDIR)/elf/reloc-macros.h \
emul.h \
subsegs.h
DEPTC_mips_coff = \
$(BFDDIR)/elf-bfd.h \
$(BFDDIR)/libcoff.h \
@ -3850,6 +3867,15 @@ DEP_mep_elf = \
$(srcdir)/config/tc-mep.h \
dwarf2dbg.h
DEP_microblaze_elf = \
$(srcdir)/config/obj-elf.h \
$(BFDDIR)/elf-bfd.h \
$(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h \
$(INCDIR)/bfdlink.h \
$(srcdir)/config/tc-microblaze.h
DEP_mips_coff = \
$(BFDDIR)/libcoff.h \
$(INCDIR)/bfdlink.h \

2370
gas/config/tc-microblaze.c Normal file
View File

File diff suppressed because it is too large Load Diff

114
gas/config/tc-microblaze.h Normal file
View File

@ -0,0 +1,114 @@
/* tc-microblaze.h -- Header file for tc-microblaze.c.
Copyright 2009 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef TC_MICROBLAZE
#define TC_MICROBLAZE 1
#define TARGET_ARCH bfd_arch_microblaze
/* Used to initialise target_big_endian. */
#define TARGET_BYTES_BIG_ENDIAN 1
#define IGNORE_NONSTANDARD_ESCAPES
#define TC_RELOC_MANGLE(a,b,c) tc_reloc_mangle (a, b, c)
/* We need to handle expressions of type "symbol op symbol" and create
relocs for such expressions as -relax in linker can change the value
of such expressions */
#define TC_CONS_FIX_NEW cons_fix_new_microblaze
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) parse_cons_expression_microblaze (EXP, NBYTES)
extern void parse_cons_expression_microblaze PARAMS ((expressionS *, int));
#define TC_FORCE_RELOCATION_SECTION(FIXP,SEG) 1
#define UNDEFINED_DIFFERENCE_OK 1
#define TC_FORCE_RELOCATION_LOCAL(FIX) \
(!(FIX)->fx_pcrel \
|| (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_64_GOT \
|| (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_64_PLT \
|| (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_64_GOTOFF \
|| (FIX)->fx_r_type == BFD_RELOC_MICROBLAZE_32_GOTOFF \
|| TC_FORCE_RELOCATION (FIX))
#define tc_fix_adjustable(X) tc_microblaze_fix_adjustable(X)
extern int tc_microblaze_fix_adjustable (struct fix *);
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
#define LISTING_HEADER "Xilinx MicroBlaze GAS Listing"
#define LISTING_LHS_CONT_LINES 4
#define NEED_FX_R_TYPE 1
/* We want local label support. */
#define LOCAL_LABELS_FB 1
/* Want the section information too... */
#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
#define MD_APPLY_FIX3 /* We want the segment as well. */
/* We set the fx_done field appropriately in md_apply_fix. */
#define TC_HANDLES_FX_DONE
#ifdef OBJ_ELF
#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblaze-little")
#define ELF_TC_SPECIAL_SECTIONS \
{ ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \
{ ".sbss", SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, \
{ ".sdata2", SHT_PROGBITS, SHF_ALLOC }, \
{ ".sbss2", SHT_PROGBITS, SHF_ALLOC }, \
/* Other special sections not generated by the assembler: .reginfo,
.liblist, .conflict, .gptab, .got, .dynamic, .rel.dyn. */
#endif /* OBJ_ELF */
#ifndef TARGET_FORMAT
# error No target format specified.
#endif
#include "write.h" /* For definition of fixS */
extern void md_begin (void);
extern void md_assemble (char *);
extern symbolS * md_undefined_symbol (char *);
extern char * md_atof (int, char *, int *);
extern int md_parse_option (int, char *);
extern void md_show_usage (FILE *);
extern void md_convert_frag (bfd *, segT, fragS *);
extern void md_operand (expressionS *);
extern int md_estimate_size_before_relax (fragS *, segT);
extern void md_number_to_chars (char *, valueT, int);
extern valueT md_section_align (segT, valueT);
extern long md_pcrel_from_section (fixS *, segT);
extern arelent * tc_gen_reloc (asection *, fixS *);
extern void cons_fix_new_microblaze (fragS *, int, int, expressionS *);
extern void md_apply_fix3 (fixS *, valueT *, segT);
#define EXTERN_FORCE_RELOC -1
#endif /* TC_MICROBLAZE */

4
gas/config/tc-tic4x.c
View File

@ -1285,8 +1285,8 @@ tic4x_inst_add (const tic4x_inst_t *insts)
d = name;
/* We do not care about INSNs that is not a part of our
oplevel setting */
if (!insts->oplevel & tic4x_oplevel)
oplevel setting. */
if ((insts->oplevel & tic4x_oplevel) == 0)
return ok;
while (1)

3
gas/configure vendored
View File

@ -12042,6 +12042,9 @@ _ACEOF
echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;}
;;
microblaze*)
;;
mips-sony-bsd*)
;;
mips-*-bsd*)

3
gas/configure.in
View File

@ -137,6 +137,9 @@ for this_target in $target $canon_targets ; do
AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress)
;;
microblaze*)
;;
mips-sony-bsd*)
;;
mips-*-bsd*)

5
gas/configure.tgt
View File

@ -55,6 +55,7 @@ case ${cpu} in
m683??) cpu_type=m68k ;;
maxq) cpu_type=maxq ;;
mep-*-elf) cpu_type=mep endian=big ;;
microblaze*) cpu_type=microblaze ;;
mips*el) cpu_type=mips endian=little ;;
mips*) cpu_type=mips endian=big ;;
mt) cpu_type=mt endian=big ;;
@ -279,6 +280,8 @@ case ${generic_target} in
mcore-*-elf) fmt=elf ;;
mcore-*-pe) fmt=coff em=pe bfd_gas=yes ;;
microblaze-*-*) fmt=elf ;;
# don't change em like *-*-bsd does
mips-sony-bsd*) fmt=ecoff ;;
mips-*-ultrix*) fmt=ecoff endian=little ;;
@ -425,7 +428,7 @@ case ${generic_target} in
esac
case ${cpu_type} in
alpha | arm | i386 | ia64 | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
bfd_gas=yes
;;
esac

1
gas/doc/Makefile.am
View File

@ -49,6 +49,7 @@ CPU_DOCS = \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-microblaze.texi \
c-mips.texi \
c-mmix.texi \
c-mt.texi \

1
gas/doc/Makefile.in
View File

@ -270,6 +270,7 @@ CPU_DOCS = \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-microblaze.texi \
c-mips.texi \
c-mmix.texi \
c-mt.texi \

1
gas/doc/all.texi
View File

@ -50,6 +50,7 @@
@set M68HC11
@set M680X0
@set MCORE
@set MICROBLAZE
@set MIPS
@set MMIX
@set MS1

11
gas/doc/as.texinfo
View File

@ -363,6 +363,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-jsri2bsr}] [@b{-sifilter}] [@b{-relax}]
[@b{-mcpu=[210|340]}]
@end ifset
@ifset MICROBLAZE
@emph{Target MICROBLAZE options:}
@c MicroBlaze has no machine-dependent assembler options.
@end ifset
@ifset MIPS
@emph{Target MIPS options:}
@ -6766,6 +6770,9 @@ subject, see the hardware manufacturer's manual.
@ifset M68HC11
* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
@end ifset
@ifset MICROBLAZE
* MicroBlaze-Dependent:: MICROBLAZE Dependent Features
@end ifset
@ifset MIPS
* MIPS-Dependent:: MIPS Dependent Features
@end ifset
@ -6934,6 +6941,10 @@ family.
@include c-m68hc11.texi
@end ifset
@ifset MICROBLAZE
@include c-microblaze.texi
@end ifset
@ifset MIPS
@include c-mips.texi
@end ifset

1
gas/testsuite/gas/arm/align.d
View File

@ -1,6 +1,7 @@
# name: ARM V6t2 Alignment
# as: -march=armv6kt2
# objdump: -dr --prefix-addresses --show-raw-insn
#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*arm.*

4
include/ChangeLog
View File

@ -1,3 +1,7 @@
2009-08-06 Michael Eager <eager@eagercon.com>
* dis-asm.h: Decl print_insn_microblaze().
2009-07-24 Ian Lance Taylor <iant@google.com>
* libiberty.h (crc32): Declare.

1
include/dis-asm.h
View File

@ -265,6 +265,7 @@ extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
extern int print_insn_mcore (bfd_vma, disassemble_info *);
extern int print_insn_mep (bfd_vma, disassemble_info *);
extern int print_insn_microblaze (bfd_vma, disassemble_info *);
extern int print_insn_mmix (bfd_vma, disassemble_info *);
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
extern int print_insn_mn10300 (bfd_vma, disassemble_info *);

5
include/elf/ChangeLog
View File

@ -1,3 +1,8 @@
2009-08-06 Michael Eager <eager@eagercon.com>
* elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD.
* elf/microblaze.h: New reloc definitions.
2009-07-30 Alan Modra <amodra@bigpond.net.au>
* ppc64.h: Add R_PPC64_JMP_IREL, R_PPC64_REL16, R_PPC64_REL16_LO,

4
include/elf/common.h
View File

@ -241,6 +241,8 @@
#define EM_L1OM 180 /* Intel L1OM */
#define EM_INTEL181 181 /* Reserved by Intel */
#define EM_INTEL182 182 /* Reserved by Intel */
#define EM_MICROBLAZE 183 /* Xilinx MicroBlaze */
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
@ -344,6 +346,8 @@
/* Old Sunplus S+core7 backend magic number. Written in the absence of an ABI. */
#define EM_SCORE_OLD 95
#define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */
/* See the above comment before you add a new EM_* value here. */
/* Values for e_version. */

63
include/elf/microblaze.h Normal file
View File

@ -0,0 +1,63 @@
/* Xilinx MicroBlaze support for BFD.
Copyright 2009 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* This file holds definitions specific to the MICROBLAZE ELF ABI. */
#ifndef _ELF_MICROBLAZE_H
#define _ELF_MICROBLAZE_H
#include "elf/reloc-macros.h"
/* Relocations. */
START_RELOC_NUMBERS (elf_microblaze_reloc_type)
RELOC_NUMBER (R_MICROBLAZE_NONE, 0)
RELOC_NUMBER (R_MICROBLAZE_32, 1)
RELOC_NUMBER (R_MICROBLAZE_32_PCREL, 2)
RELOC_NUMBER (R_MICROBLAZE_64_PCREL, 3)
RELOC_NUMBER (R_MICROBLAZE_32_PCREL_LO, 4)
RELOC_NUMBER (R_MICROBLAZE_64, 5)
RELOC_NUMBER (R_MICROBLAZE_32_LO, 6)
RELOC_NUMBER (R_MICROBLAZE_SRO32, 7)
RELOC_NUMBER (R_MICROBLAZE_SRW32, 8)
RELOC_NUMBER (R_MICROBLAZE_64_NONE, 9)
RELOC_NUMBER (R_MICROBLAZE_32_SYM_OP_SYM, 10)
RELOC_NUMBER (R_MICROBLAZE_GNU_VTINHERIT, 11)
RELOC_NUMBER (R_MICROBLAZE_GNU_VTENTRY, 12)
RELOC_NUMBER (R_MICROBLAZE_GOTPC_64, 13) /* PC-relative GOT offset. */
RELOC_NUMBER (R_MICROBLAZE_GOT_64, 14) /* GOT entry offset. */
RELOC_NUMBER (R_MICROBLAZE_PLT_64, 15) /* PLT offset (PC-relative). */
RELOC_NUMBER (R_MICROBLAZE_REL, 16) /* Adjust by program base. */
RELOC_NUMBER (R_MICROBLAZE_JUMP_SLOT, 17) /* Create PLT entry. */
RELOC_NUMBER (R_MICROBLAZE_GLOB_DAT, 18) /* Create GOT entry. */
RELOC_NUMBER (R_MICROBLAZE_GOTOFF_64, 19) /* Offset relative to GOT. */
RELOC_NUMBER (R_MICROBLAZE_GOTOFF_32, 20) /* Offset relative to GOT. */
RELOC_NUMBER (R_MICROBLAZE_COPY, 21) /* Runtime copy. */
END_RELOC_NUMBERS (R_MICROBLAZE_max)
/* Global base address names. */
#define RO_SDA_ANCHOR_NAME "_SDA2_BASE_"
#define RW_SDA_ANCHOR_NAME "_SDA_BASE_"
/* Section Attributes. */
#define SHF_MICROBLAZE_NOREAD 0x80000000
#endif /* _ELF_MICROBLAZE_H */

10
ld/ChangeLog
View File

@ -1,3 +1,13 @@
2009-08-06 Michael Eager <eager@eagercon.com>
* Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to
ALL_EMULATIONS, targets.
* Makefile.in: Regenerate.
* configure.tgt: Add microblaze*-linux*, microblaze* targets.
* emulparams/elf32mb_linux.sh: New.
* emulparams/elf32microblaze.sh. New.
* scripttempl/elfmicroblaze.sc: New.
2009-08-05 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
* emulparams/elf32_spu.sh (OTHER_READONLY_SECTIONS): Add .fixup

8
ld/Makefile.am
View File

@ -191,6 +191,8 @@ ALL_EMULATIONS = \
eelf32m32c.o \
eelf32mcore.o \
eelf32mep.o \
eelf32mb_linux.o \
eelf32microblaze.o \
eelf32mipswindiss.o \
eelf32mt.o \
eelf32openrisc.o \
@ -858,6 +860,12 @@ eelf32lmip.c: $(srcdir)/emulparams/elf32lmip.sh \
$(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \
$(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32lmip "$(tdir_elf32lmip)"
eelf32mb_linux.c: $(srcdir)/emulparams/elf32mb_linux.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mb_linux "$(tdir_microblaze)"
eelf32microblaze.c: $(srcdir)/emulparams/elf32microblaze.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32microblaze "$(tdir_microblaze)"
eelf32mipswindiss.c: $(srcdir)/emulparams/elf32mipswindiss.sh $(ELF_DEPS) \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mipswindiss "$(tdir_elf32mipswindiss)"

8
ld/Makefile.in
View File

@ -456,6 +456,8 @@ ALL_EMULATIONS = \
eelf32m32c.o \
eelf32mcore.o \
eelf32mep.o \
eelf32mb_linux.o \
eelf32microblaze.o \
eelf32mipswindiss.o \
eelf32mt.o \
eelf32openrisc.o \
@ -1705,6 +1707,12 @@ eelf32lmip.c: $(srcdir)/emulparams/elf32lmip.sh \
$(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \
$(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32lmip "$(tdir_elf32lmip)"
eelf32mb_linux.c: $(srcdir)/emulparams/elf32mb_linux.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mb_linux "$(tdir_microblaze)"
eelf32microblaze.c: $(srcdir)/emulparams/elf32microblaze.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32microblaze "$(tdir_microblaze)"
eelf32mipswindiss.c: $(srcdir)/emulparams/elf32mipswindiss.sh $(ELF_DEPS) \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32mipswindiss "$(tdir_elf32mipswindiss)"

3
ld/configure.tgt
View File

@ -361,6 +361,9 @@ mcore-*-pe) targ_emul=mcorepe ;
mcore-*-elf) targ_emul=elf32mcore
;;
mep-*-elf) targ_emul=elf32mep ;;
microblaze*-linux*)
targ_emul="elf32mb_linux" ;;
microblaze*) targ_emul=elf32microblaze ;;
mips*-*-pe) targ_emul=mipspe ;
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
mips*-dec-ultrix*) targ_emul=mipslit ;;

17
ld/emulparams/elf32mb_linux.sh Normal file
View File

@ -0,0 +1,17 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-microblaze"
TEXT_START_ADDR=0x10000000
NONPAGED_TEXT_START_ADDR=0x28
ALIGNMENT=4
MAXPAGESIZE=0x1000
COMMONPAGESIZE=0x1000
ARCH=microblaze
NOP=0x80000000
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
GENERATE_PIE_SCRIPT=yes
NO_SMALL_DATA=yes
SEPARATE_GOTPLT=12

23
ld/emulparams/elf32microblaze.sh Normal file
View File

@ -0,0 +1,23 @@
SCRIPT_NAME=elfmicroblaze
OUTPUT_FORMAT="elf32-microblaze"
#TEXT_START_ADDR=0
NONPAGED_TEXT_START_ADDR=0x28
ALIGNMENT=4
MAXPAGESIZE=4
ARCH=microblaze
EMBEDDED=yes
NOP=0x80000000
# Hmmm, there's got to be a better way. This sets the stack to the
# top of the simulator memory (2^19 bytes).
#PAGE_SIZE=0x1000
#DATA_ADDR=0x10000
#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
TEMPLATE_NAME=elf32
#GENERATE_SHLIB_SCRIPT=yes

6
ld/scripttempl/elf32cr16.sc
View File

@ -133,21 +133,21 @@ SECTIONS
The heap and stack are aligned to the bus width, as a speed optimization
for accessing data located there. */
.heap :
.heap (NOLOAD) :
{
. = ALIGN(4);
__HEAP_START = .;
. += 0x2000; __HEAP_MAX = .;
} > ram
.stack :
.stack (NOLOAD) :
{
. = ALIGN(4);
. += 0x6000;
__STACK_START = .;
} > ram
.istack :
.istack (NOLOAD) :
{
. = ALIGN(4);
. += 0x100;

24
ld/scripttempl/elf32cr16c.sc
View File

@ -31,18 +31,18 @@ SECTIONS
there. The alignment to 4 bytes is compatible for both the CR16C
bus width (2 bytes) and CR16CPlus bus width (4 bytes). */
.text : { __TEXT_START = .; *(.text) __TEXT_END = .; } > rom
.rdata : { __RDATA_START = .; *(.rdata_4) *(.rdata_2) *(.rdata_1) __RDATA_END = .; } > near_rom
.ctor ALIGN(4) : { __CTOR_LIST = .; *(.ctors) __CTOR_END = .; } > near_rom
.dtor ALIGN(4) : { __DTOR_LIST = .; *(.dtors) __DTOR_END = .; } > near_rom
.data : { __DATA_START = .; *(.data_4) *(.data_2) *(.data_1) *(.data) __DATA_END = .; } > ram AT > rom
.bss (NOLOAD) : { __BSS_START = .; *(.bss_4) *(.bss_2) *(.bss_1) *(.bss) *(COMMON) __BSS_END = .; } > ram
.nrdata : { __NRDATA_START = .; *(.nrdat_4) *(.nrdat_2) *(.nrdat_1) __NRDATA_END = .; } > near_rom
.ndata : { __NDATA_START = .; *(.ndata_4) *(.ndata_2) *(.ndata_1) __NDATA_END = .; } > near_ram AT > rom
.nbss (NOLOAD) : { __NBSS_START = .; *(.nbss_4) *(.nbss_2) *(.nbss_1) *(.ncommon) __NBSS_END = .; } > near_ram
.heap : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > near_ram
.stack : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram
.istack : { . = ALIGN(2); . += 0x100; __ISTACK_START = .; } > ram
.text : { __TEXT_START = .; *(.text) __TEXT_END = .; } > rom
.rdata : { __RDATA_START = .; *(.rdata_4) *(.rdata_2) *(.rdata_1) __RDATA_END = .; } > near_rom
.ctor ALIGN(4) : { __CTOR_LIST = .; *(.ctors) __CTOR_END = .; } > near_rom
.dtor ALIGN(4) : { __DTOR_LIST = .; *(.dtors) __DTOR_END = .; } > near_rom
.data : { __DATA_START = .; *(.data_4) *(.data_2) *(.data_1) *(.data) __DATA_END = .; } > ram AT > rom
.bss (NOLOAD) : { __BSS_START = .; *(.bss_4) *(.bss_2) *(.bss_1) *(.bss) *(COMMON) __BSS_END = .; } > ram
.nrdata : { __NRDATA_START = .; *(.nrdat_4) *(.nrdat_2) *(.nrdat_1) __NRDATA_END = .; } > near_rom
.ndata : { __NDATA_START = .; *(.ndata_4) *(.ndata_2) *(.ndata_1) __NDATA_END = .; } > near_ram AT > rom
.nbss (NOLOAD) : { __NBSS_START = .; *(.nbss_4) *(.nbss_2) *(.nbss_1) *(.ncommon) __NBSS_END = .; } > near_ram
.heap (NOLOAD) : { . = ALIGN(4); __HEAP_START = .; . += 0x2000; __HEAP_MAX = .; } > near_ram
.stack (NOLOAD) : { . = ALIGN(4); . += 0x6000; __STACK_START = .; } > ram
.istack (NOLOAD) : { . = ALIGN(2); . += 0x100; __ISTACK_START = .; } > ram
}
__DATA_IMAGE_START = LOADADDR(.data);

6
ld/scripttempl/elf32crx.sc
View File

@ -135,21 +135,21 @@ SECTIONS
The heap and stack are aligned to the bus width, as a speed optimization
for accessing data located there. */
.heap :
.heap (NOLOAD) :
{
. = ALIGN(4);
__HEAP_START = .;
. += 0x2000; __HEAP_MAX = .;
} > ram
.stack :
.stack (NOLOAD) :
{
. = ALIGN(4);
. += 0x6000;
__STACK_START = .;
} > ram
.istack :
.istack (NOLOAD) :
{
. = ALIGN(4);
. += 0x100;

222
ld/scripttempl/elfmicroblaze.sc Normal file
View File

@ -0,0 +1,222 @@
# Adapted from mips.sc
# These variables may be overridden by the emulation file. The
# defaults are appropriate for a DECstation running Ultrix.
test -z "$ENTRY" && ENTRY=_start
#test -z "$TEXT_START_ADDR" && TEXT_START_ADDR="0x0"
CTOR=".ctors ${CONSTRUCTING-0} :
{
${CONSTRUCTING+${CTOR_START}}
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
${CONSTRUCTING+${CTOR_END}}
}"
DTOR=" .dtors ${CONSTRUCTING-0} :
{
${CONSTRUCTING+${DTOR_START}}
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
${CONSTRUCTING+${DTOR_END}}
}"
cat <<EOF
OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
"${LITTLE_OUTPUT_FORMAT}")
/*${LIB_SEARCH_DIRS}*/
${RELOCATING+${LIB_SEARCH_DIRS}}
ENTRY(${ENTRY})
_TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0;
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
SECTIONS
{
.vectors.reset 0x0 : { KEEP (*(.vectors.reset)) } = 0
.vectors.sw_exception 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0
.vectors.interrupt 0x10 : { KEEP (*(.vectors.interrupt)) } = 0
.vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0
.vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0
${RELOCATING+. = _TEXT_START_ADDR;}
${RELOCATING+ _ftext = .;}
.text : {
${RELOCATING+*(.text)}
${RELOCATING+*(.text.*)}
${RELOCATING+*(.gnu.linkonce.t.*)}
}
${RELOCATING+ _etext = .;}
.init : { KEEP (*(.init)) } =0
.fini : { KEEP (*(.fini)) } =0
${RELOCATING+PROVIDE (__CTOR_LIST__ = .);}
${RELOCATING+PROVIDE (___CTOR_LIST__ = .);}
${RELOCATING+${CTOR}}
${RELOCATING+PROVIDE (__CTOR_END__ = .);}
${RELOCATING+PROVIDE (___CTOR_END__ = .);}
${RELOCATING+PROVIDE (__DTOR_LIST__ = .);}
${RELOCATING+PROVIDE (___DTOR_LIST__ = .);}
${RELOCATING+${DTOR}}
${RELOCATING+PROVIDE (__DTOR_END__ = .);}
${RELOCATING+PROVIDE (___DTOR_END__ = .);}
${RELOCATING+ . = ALIGN(4);}
${RELOCATING+ _frodata = . ;}
.rodata : {
${RELOCATING+*(.rodata)}
${RELOCATING+*(.rodata.*)}
${RELOCATING+*(.gnu.linkonce.r.*)}
${CONSTRUCTING+CONSTRUCTORS}; /* Is this needed? */
}
${RELOCATING+ _erodata = .;}
/* Alignments by 8 to ensure that _SDA2_BASE_ on a word boundary */
/* Note that .sdata2 and .sbss2 must be contiguous */
${RELOCATING+. = ALIGN(8);}
${RELOCATING+ _ssrw = .;}
.sdata2 : {
${RELOCATING+*(.sdata2)}
${RELOCATING+*(.sdata2.*)}
${RELOCATING+*(.gnu.linkonce.s2.*)}
}
${RELOCATING+. = ALIGN(4);}
.sbss2 : {
${RELOCATING+PROVIDE (__sbss2_start = .);}
${RELOCATING+*(.sbss2)}
${RELOCATING+*(.sbss2.*)}
${RELOCATING+*(.gnu.linkonce.sb2.*)}
${RELOCATING+PROVIDE (__sbss2_end = .);}
}
${RELOCATING+. = ALIGN(8);}
${RELOCATING+ _essrw = .;}
${RELOCATING+ _ssrw_size = _essrw - _ssrw;}
${RELOCATING+ PROVIDE (_SDA2_BASE_ = _ssrw + (_ssrw_size / 2 ));}
${RELOCATING+ . = ALIGN(4);}
${RELOCATING+ _fdata = .;}
.data : {
${RELOCATING+*(.data)}
${RELOCATING+*(.gnu.linkonce.d.*)}
${CONSTRUCTING+CONSTRUCTORS}; /* Is this needed? */
}
${RELOCATING+ _edata = . ;}
/* Added to handle pic code */
.got : {
${RELOCATING+*(.got)}
}
.got1 : {
${RELOCATING+*(.got1)}
}
.got2 : {
${RELOCATING+*(.got2)}
}
/* Added by Sathya to handle C++ exceptions */
.eh_frame : {
${RELOCATING+*(.eh_frame)}
}
.jcr : {
${RELOCATING+*(.jcr)}
}
.gcc_except_table : {
${RELOCATING+*(.gcc_except_table)}
}
/* Alignments by 8 to ensure that _SDA_BASE_ on a word boundary */
/* Note that .sdata and .sbss must be contiguous */
${RELOCATING+. = ALIGN(8);}
${RELOCATING+ _ssro = .;}
.sdata : {
${RELOCATING+*(.sdata)}
${RELOCATING+*(.sdata.*)}
${RELOCATING+*(.gnu.linkonce.s.*)}
}
${RELOCATING+. = ALIGN(4);}
.sbss : {
${RELOCATING+PROVIDE (__sbss_start = .);}
${RELOCATING+*(.sbss)}
${RELOCATING+*(.sbss.*)}
${RELOCATING+*(.gnu.linkonce.sb.*)}
${RELOCATING+PROVIDE (__sbss_end = .);}
}
${RELOCATING+. = ALIGN(8);}
${RELOCATING+ _essro = .;}
${RELOCATING+ _ssro_size = _essro - _ssro;}
${RELOCATING+PROVIDE (_SDA_BASE_ = _ssro + (_ssro_size / 2 ));}
${RELOCATING+ . = ALIGN(4);}
${RELOCATING+ _fbss = .;}
.bss : {
${RELOCATING+PROVIDE (__bss_start = .);}
${RELOCATING+*(.bss)}
${RELOCATING+*(.bss.*)}
${RELOCATING+*(.gnu.linkonce.b.*)}
${RELOCATING+*(COMMON)}
${RELOCATING+. = ALIGN(4);}
${RELOCATING+PROVIDE (__bss_end = .);}
}
${RELOCATING+ . = ALIGN(4);}
.heap : {
${RELOCATING+ _heap = .;}
${RELOCATING+ _heap_start = .;}
${RELOCATING+ . += _HEAP_SIZE;}
${RELOCATING+ _heap_end = .;}
}
${RELOCATING+ . = ALIGN(4);}
.stack : {
${RELOCATING+ _stack_end = .;}
${RELOCATING+ . += _STACK_SIZE;}
${RELOCATING+ . = ALIGN(8);}
${RELOCATING+ _stack = .;}
${RELOCATING+ _end = .;}
}
.tdata : {
${RELOCATING+*(.tdata)}
${RELOCATING+*(.tdata.*)}
${RELOCATING+*(.gnu.linkonce.td.*)}
}
.tbss : {
${RELOCATING+*(.tbss)}
${RELOCATING+*(.tbss.*)}
${RELOCATING+*(.gnu.linkonce.tb.*)}
}
}
EOF

13
opcodes/ChangeLog
View File

@ -1,3 +1,16 @@
2009-08-06 Michael Eager <eager@eagercon.com>
* Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to
CFILES, microblaze-dis.lo to ALL_MACHINES, targets.
* Makefile.in: Regenerate.
* configure.in: Add bfd_microblaze_arch target.
* configure: Regenerate.
* disassemble.c: Define ARCH_microblaze, return
print_insn_microblaze().
* microblaze-dis.c: New MicroBlaze disassembler.
* microblaze-opc.h: New MicroBlaze opcode definitions.
* microblaze-opcm.h: New MicroBlaze opcode types.
2009-07-25 H.J. Lu <hongjiu.lu@intel.com>
* configure.in: Handle bfd_l1om_arch.

8
opcodes/Makefile.am
View File

@ -49,6 +49,7 @@ HFILES = \
m32r-desc.h m32r-opc.h \
mcore-opc.h \
mep-desc.h mep-opc.h \
microblaze-opc.h \
mt-desc.h mt-opc.h \
openrisc-desc.h openrisc-opc.h \
score-opc.h \
@ -160,6 +161,7 @@ CFILES = \
mep-ibld.c \
mep-opc.c \
mips-dis.c \
microblaze-dis.c \
mips-opc.c \
mips16-opc.c \
m10200-dis.c \
@ -315,6 +317,7 @@ ALL_MACHINES = \
mep-ibld.lo \
mep-opc.lo \
mips-dis.lo \
microblaze-dis.lo \
mips-opc.lo \
mips16-opc.lo \
mmix-dis.lo \
@ -1798,6 +1801,11 @@ mep-opc.lo: \
mep-desc.h \
mep-opc.h \
sysdep.h
microblaze-dis.lo: \
microblaze-dis.c \
microblaze-opc.h \
$(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h
mips-dis.lo: \
mips-dis.c \
$(BFDDIR)/elf-bfd.h \

8
opcodes/Makefile.in
View File

@ -287,6 +287,7 @@ HFILES = \
m32r-desc.h m32r-opc.h \
mcore-opc.h \
mep-desc.h mep-opc.h \
microblaze-opc.h \
mt-desc.h mt-opc.h \
openrisc-desc.h openrisc-opc.h \
score-opc.h \
@ -399,6 +400,7 @@ CFILES = \
mep-ibld.c \
mep-opc.c \
mips-dis.c \
microblaze-dis.c \
mips-opc.c \
mips16-opc.c \
m10200-dis.c \
@ -554,6 +556,7 @@ ALL_MACHINES = \
mep-ibld.lo \
mep-opc.lo \
mips-dis.lo \
microblaze-dis.lo \
mips-opc.lo \
mips16-opc.lo \
mmix-dis.lo \
@ -2363,6 +2366,11 @@ mep-opc.lo: \
mep-desc.h \
mep-opc.h \
sysdep.h
microblaze-dis.lo: \
microblaze-dis.c \
microblaze-opc.h \
$(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h
mips-dis.lo: \
mips-dis.c \
$(BFDDIR)/elf-bfd.h \

1
opcodes/configure vendored
View File

@ -12787,6 +12787,7 @@ if test x${all_targets} = xfalse ; then
bfd_maxq_arch) ta="$ta maxq-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;

1
opcodes/configure.in
View File

@ -238,6 +238,7 @@ if test x${all_targets} = xfalse ; then
bfd_maxq_arch) ta="$ta maxq-dis.lo" ;;
bfd_mcore_arch) ta="$ta mcore-dis.lo" ;;
bfd_mep_arch) ta="$ta mep-asm.lo mep-desc.lo mep-dis.lo mep-ibld.lo mep-opc.lo" using_cgen=yes ;;
bfd_microblaze_arch) ta="$ta microblaze-dis.lo" ;;
bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;

6
opcodes/disassemble.c
View File

@ -56,6 +56,7 @@
#define ARCH_maxq
#define ARCH_mcore
#define ARCH_mep
#define ARCH_microblaze
#define ARCH_mips
#define ARCH_mmix
#define ARCH_mn10200
@ -264,6 +265,11 @@ disassembler (abfd)
disassemble = print_insn_mt;
break;
#endif
#ifdef ARCH_microblaze
case bfd_arch_microblaze:
disassemble = print_insn_microblaze;
break;
#endif
#ifdef ARCH_msp430
case bfd_arch_msp430:
disassemble = print_insn_msp430;

527
opcodes/microblaze-dis.c Normal file
View File

@ -0,0 +1,527 @@
/* Disassemble Xilinx microblaze instructions.
Copyright 2009 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#define STATIC_TABLE
#define DEFINE_TABLE
#include "microblaze-opc.h"
#include "dis-asm.h"
#include <strings.h>
#define get_field_rd(instr) get_field (instr, RD_MASK, RD_LOW)
#define get_field_r1(instr) get_field (instr, RA_MASK, RA_LOW)
#define get_field_r2(instr) get_field (instr, RB_MASK, RB_LOW)
#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
static char *
get_field (long instr, long mask, unsigned short low)
{
char tmpstr[25];
sprintf (tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low));
return (strdup (tmpstr));
}
static char *
get_field_imm (long instr)
{
char tmpstr[25];
sprintf (tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
return (strdup (tmpstr));
}
static char *
get_field_imm5 (long instr)
{
char tmpstr[25];
sprintf (tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
return (strdup (tmpstr));
}
static char *
get_field_rfsl (long instr)
{
char tmpstr[25];
sprintf (tmpstr, "%s%d", fsl_register_prefix,
(short)((instr & RFSL_MASK) >> IMM_LOW));
return (strdup (tmpstr));
}
static char *
get_field_imm15 (long instr)
{
char tmpstr[25];
sprintf (tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
return (strdup (tmpstr));
}
static char *
get_field_special (long instr, struct op_code_struct * op)
{
char tmpstr[25];
char spr[6];
switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
{
case REG_MSR_MASK :
strcpy (spr, "msr");
break;
case REG_PC_MASK :
strcpy (spr, "pc");
break;
case REG_EAR_MASK :
strcpy (spr, "ear");
break;
case REG_ESR_MASK :
strcpy (spr, "esr");
break;
case REG_FSR_MASK :
strcpy (spr, "fsr");
break;
case REG_BTR_MASK :
strcpy (spr, "btr");
break;
case REG_EDR_MASK :
strcpy (spr, "edr");
break;
case REG_PID_MASK :
strcpy (spr, "pid");
break;
case REG_ZPR_MASK :
strcpy (spr, "zpr");
break;
case REG_TLBX_MASK :
strcpy (spr, "tlbx");
break;
case REG_TLBLO_MASK :
strcpy (spr, "tlblo");
break;
case REG_TLBHI_MASK :
strcpy (spr, "tlbhi");
break;
case REG_TLBSX_MASK :
strcpy (spr, "tlbsx");
break;
default :
if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
== REG_PVR_MASK)
{
sprintf (tmpstr, "%spvr%d", register_prefix,
(unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
^ op->immval_mask) ^ REG_PVR_MASK);
return (strdup (tmpstr));
}
else
strcpy (spr, "pc");
break;
}
sprintf (tmpstr, "%s%s", register_prefix, spr);
return (strdup (tmpstr));
}
static unsigned long
read_insn_microblaze (bfd_vma memaddr,
struct disassemble_info *info,
struct op_code_struct **opr)
{
unsigned char ibytes[4];
int status;
struct op_code_struct * op;
unsigned long inst;
status = info->read_memory_func (memaddr, ibytes, 4, info);
if (status != 0)
{
info->memory_error_func (status, memaddr, info);
return 0;
}
if (info->endian == BFD_ENDIAN_BIG)
inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3];
else if (info->endian == BFD_ENDIAN_LITTLE)
inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0];
else
abort ();
/* Just a linear search of the table. */
for (op = opcodes; op->name != 0; op ++)
if (op->bit_sequence == (inst & op->opcode_mask))
break;
*opr = op;
return inst;
}
int
print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
{
fprintf_ftype fprintf = info->fprintf_func;
void * stream = info->stream;
unsigned long inst, prev_inst;
struct op_code_struct * op, *pop;
int immval = 0;
bfd_boolean immfound = FALSE;
static bfd_vma prev_insn_addr = -1; /* Init the prev insn addr. */
static int prev_insn_vma = -1; /* Init the prev insn vma. */
int curr_insn_vma = info->buffer_vma;
info->bytes_per_chunk = 4;
inst = read_insn_microblaze (memaddr, info, &op);
if (inst == 0)
return -1;
if (prev_insn_vma == curr_insn_vma)
{
if (memaddr-(info->bytes_per_chunk) == prev_insn_addr)
{
prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
if (prev_inst == 0)
return -1;
if (pop->instr == imm)
{
immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
immfound = TRUE;
}
else
{
immval = 0;
immfound = FALSE;
}
}
}
/* Make curr insn as prev insn. */
prev_insn_addr = memaddr;
prev_insn_vma = curr_insn_vma;
if (op->name == NULL)
fprintf (stream, ".short 0x%04x", inst);
else
{
fprintf (stream, "%s", op->name);
switch (op->inst_type)
{
case INST_TYPE_RD_R1_R2:
fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
get_field_r1(inst), get_field_r2 (inst));
break;
case INST_TYPE_RD_R1_IMM:
fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
get_field_r1(inst), get_field_imm (inst));
if (info->print_address_func && get_int_field_r1 (inst) == 0
&& info->symbol_at_address_func)
{
if (immfound)
immval |= (get_int_field_imm (inst) & 0x0000ffff);
else
{
immval = get_int_field_imm (inst);
if (immval & 0x8000)
immval |= 0xFFFF0000;
}
if (immval > 0 && info->symbol_at_address_func (immval, info))
{
fprintf (stream, "\t// ");
info->print_address_func (immval, info);
}
}
break;
case INST_TYPE_RD_R1_IMM5:
fprintf (stream, "\t%s, %s, %s", get_field_rd (inst),
get_field_r1(inst), get_field_imm5 (inst));
break;
case INST_TYPE_RD_RFSL:
fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst));
break;
case INST_TYPE_R1_RFSL:
fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst));
break;
case INST_TYPE_RD_SPECIAL:
fprintf (stream, "\t%s, %s", get_field_rd (inst),
get_field_special (inst, op));
break;
case INST_TYPE_SPECIAL_R1:
fprintf (stream, "\t%s, %s", get_field_special (inst, op),
get_field_r1(inst));
break;
case INST_TYPE_RD_R1:
fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r1 (inst));
break;
case INST_TYPE_R1_R2:
fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst));
break;
case INST_TYPE_R1_IMM:
fprintf (stream, "\t%s, %s", get_field_r1 (inst), get_field_imm (inst));
/* The non-pc relative instructions are returns, which shouldn't
have a label printed. */
if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET
&& info->symbol_at_address_func)
{
if (immfound)
immval |= (get_int_field_imm (inst) & 0x0000ffff);
else
{
immval = get_int_field_imm (inst);
if (immval & 0x8000)
immval |= 0xFFFF0000;
}
immval += memaddr;
if (immval > 0 && info->symbol_at_address_func (immval, info))
{
fprintf (stream, "\t// ");
info->print_address_func (immval, info);
}
else
{
fprintf (stream, "\t\t// ");
fprintf (stream, "%x", immval);
}
}
break;
case INST_TYPE_RD_IMM:
fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm (inst));
if (info->print_address_func && info->symbol_at_address_func)
{
if (immfound)
immval |= (get_int_field_imm (inst) & 0x0000ffff);
else
{
immval = get_int_field_imm (inst);
if (immval & 0x8000)
immval |= 0xFFFF0000;
}
if (op->inst_offset_type == INST_PC_OFFSET)
immval += (int) memaddr;
if (info->symbol_at_address_func (immval, info))
{
fprintf (stream, "\t// ");
info->print_address_func (immval, info);
}
}
break;
case INST_TYPE_IMM:
fprintf (stream, "\t%s", get_field_imm (inst));
if (info->print_address_func && info->symbol_at_address_func
&& op->instr != imm)
{
if (immfound)
immval |= (get_int_field_imm (inst) & 0x0000ffff);
else
{
immval = get_int_field_imm (inst);
if (immval & 0x8000)
immval |= 0xFFFF0000;
}
if (op->inst_offset_type == INST_PC_OFFSET)
immval += (int) memaddr;
if (immval > 0 && info->symbol_at_address_func (immval, info))
{
fprintf (stream, "\t// ");
info->print_address_func (immval, info);
}
else if (op->inst_offset_type == INST_PC_OFFSET)
{
fprintf (stream, "\t\t// ");
fprintf (stream, "%x", immval);
}
}
break;
case INST_TYPE_RD_R2:
fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
break;
case INST_TYPE_R2:
fprintf (stream, "\t%s", get_field_r2 (inst));
break;
case INST_TYPE_R1:
fprintf (stream, "\t%s", get_field_r1 (inst));
break;
case INST_TYPE_RD_R1_SPECIAL:
fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
break;
case INST_TYPE_RD_IMM15:
fprintf (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
break;
/* For tuqula instruction */
case INST_TYPE_RD:
fprintf (stream, "\t%s", get_field_rd (inst));
break;
case INST_TYPE_RFSL:
fprintf (stream, "\t%s", get_field_rfsl (inst));
break;
default:
/* If the disassembler lags the instruction set. */
fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
break;
}
}
/* Say how many bytes we consumed. */
return 4;
}
#if 0
static enum microblaze_instr
get_insn_microblaze (long inst,
bfd_boolean *isunsignedimm,
enum microblaze_instr_type *insn_type,
short *delay_slots)
{
struct op_code_struct * op;
*isunsignedimm = FALSE;
/* Just a linear search of the table. */
for (op = opcodes; op->name != 0; op ++)
if (op->bit_sequence == (inst & op->opcode_mask))
break;
if (op->name == 0)
return invalid_inst;
else
{
*isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
*insn_type = op->instr_type;
*delay_slots = op->delay_slots;
return op->instr;
}
}
short
get_delay_slots_microblaze (long inst)
{
bfd_boolean isunsignedimm;
enum microblaze_instr_type insn_type;
enum microblaze_instr op;
short delay_slots;
op = get_insn_microblaze (inst, &isunsignedimm, &insn_type, &delay_slots);
if (op == invalid_inst)
return 0;
else
return delay_slots;
}
enum microblaze_instr
microblaze_decode_insn (long insn, int *rd, int *ra, int *rb, int *imm)
{
enum microblaze_instr op;
bfd_boolean t1;
enum microblaze_instr_type t2;
short t3;
op = get_insn_microblaze (insn, &t1, &t2, &t3);
*rd = (insn & RD_MASK) >> RD_LOW;
*ra = (insn & RA_MASK) >> RA_LOW;
*rb = (insn & RB_MASK) >> RB_LOW;
t3 = (insn & IMM_MASK) >> IMM_LOW;
*imm = (int) t3;
return (op);
}
unsigned long
microblaze_get_target_address (long inst, bfd_boolean immfound, int immval,
long pcval, long r1val, long r2val,
bfd_boolean *targetvalid,
bfd_boolean *unconditionalbranch)
{
struct op_code_struct * op;
long targetaddr = 0;
*unconditionalbranch = FALSE;
/* Just a linear search of the table. */
for (op = opcodes; op->name != 0; op ++)
if (op->bit_sequence == (inst & op->opcode_mask))
break;
if (op->name == 0)
{
*targetvalid = FALSE;
}
else if (op->instr_type == branch_inst)
{
switch (op->inst_type)
{
case INST_TYPE_R2:
*unconditionalbranch = TRUE;
/* Fall through. */
case INST_TYPE_RD_R2:
case INST_TYPE_R1_R2:
targetaddr = r2val;
*targetvalid = TRUE;
if (op->inst_offset_type == INST_PC_OFFSET)
targetaddr += pcval;
break;
case INST_TYPE_IMM:
*unconditionalbranch = TRUE;
/* Fall through. */
case INST_TYPE_RD_IMM:
case INST_TYPE_R1_IMM:
if (immfound)
{
targetaddr = (immval << 16) & 0xffff0000;
targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
}
else
{
targetaddr = get_int_field_imm (inst);
if (targetaddr & 0x8000)
targetaddr |= 0xFFFF0000;
}
if (op->inst_offset_type == INST_PC_OFFSET)
targetaddr += pcval;
*targetvalid = TRUE;
break;
default:
*targetvalid = FALSE;
break;
}
}
else if (op->instr_type == return_inst)
{
if (immfound)
{
targetaddr = (immval << 16) & 0xffff0000;
targetaddr |= (get_int_field_imm (inst) & 0x0000ffff);
}
else
{
targetaddr = get_int_field_imm (inst);
if (targetaddr & 0x8000)
targetaddr |= 0xFFFF0000;
}
targetaddr += r1val;
*targetvalid = TRUE;
}
else
*targetvalid = FALSE;
return targetaddr;
}
#endif

409
opcodes/microblaze-opc.h Normal file
View File

@ -0,0 +1,409 @@
/* microblaze-opc.h -- MicroBlaze Opcodes
Copyright 2009 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef MICROBLAZE_OPC
#define MICROBLAZE_OPC
#include "microblaze-opcm.h"
#define INST_TYPE_RD_R1_R2 0
#define INST_TYPE_RD_R1_IMM 1
#define INST_TYPE_RD_R1_UNSIGNED_IMM 2
#define INST_TYPE_RD_R1 3
#define INST_TYPE_RD_R2 4
#define INST_TYPE_RD_IMM 5
#define INST_TYPE_R2 6
#define INST_TYPE_R1_R2 7
#define INST_TYPE_R1_IMM 8
#define INST_TYPE_IMM 9
#define INST_TYPE_SPECIAL_R1 10
#define INST_TYPE_RD_SPECIAL 11
#define INST_TYPE_R1 12
/* New instn type for barrel shift imms. */
#define INST_TYPE_RD_R1_IMM5 13
#define INST_TYPE_RD_RFSL 14
#define INST_TYPE_R1_RFSL 15
/* New insn type for insn cache. */
#define INST_TYPE_RD_R1_SPECIAL 16
/* New insn type for msrclr, msrset insns. */
#define INST_TYPE_RD_IMM15 17
/* New insn type for tuqula rd - addik rd, r0, 42. */
#define INST_TYPE_RD 18
/* New insn type for t*put. */
#define INST_TYPE_RFSL 19
#define INST_TYPE_NONE 25
/* Instructions where the label address is resolved as a PC offset
(for branch label). */
#define INST_PC_OFFSET 1
/* Instructions where the label address is resolved as an absolute
value (for data mem or abs address). */
#define INST_NO_OFFSET 0
#define IMMVAL_MASK_NON_SPECIAL 0x0000
#define IMMVAL_MASK_MTS 0x4000
#define IMMVAL_MASK_MFS 0x0000
#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
#define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits. */
#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last
nibble of last byte for spr. */
#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
nibble of last byte for spr. */
#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits. */
#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits. */
#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */
#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
/* New Mask for msrset, msrclr insns. */
#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
#define MAX_OPCODES 280
struct op_code_struct
{
char * name;
short inst_type; /* Registers and immediate values involved. */
short inst_offset_type; /* Immediate vals offset from PC? (= 1 for branches). */
short delay_slots; /* Info about delay slots needed after this instr. */
short immval_mask;
unsigned long bit_sequence; /* All the fixed bits for the op are set and
all the variable bits (reg names, imm vals)
are set to 0. */
unsigned long opcode_mask; /* Which bits define the opcode. */
enum microblaze_instr instr;
enum microblaze_instr_type instr_type;
/* More info about output format here. */
} opcodes[MAX_OPCODES] =
{
{"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
{"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
{"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
{"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
{"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
{"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
{"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
{"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
{"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
{"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
{"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst },
{"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst },
{"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst },
{"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst },
{"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst },
{"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst },
{"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
{"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
{"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
{"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
{"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
{"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
{"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
{"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
{"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
{"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
{"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
{"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
{"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
{"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
{"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
{"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
{"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
{"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
{"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
{"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
{"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
{"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
{"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
{"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
{"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
{"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
{"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
{"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
{"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
{"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
{"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
{"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
{"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
{"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
{"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
{"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
{"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
{"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
{"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
{"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
{"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
{"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
{"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
{"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
{"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
{"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
{"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
{"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
{"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
{"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
{"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
{"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
{"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
{"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
{"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
{"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst },
{"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst },
{"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst },
{"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst },
{"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst },
{"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst },
{"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst },
{"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst },
{"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst },
{"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst },
{"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst },
{"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst },
{"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst },
{"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst },
{"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst },
{"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst },
{"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst },
{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
{"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
{"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
{"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
{"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0. */
{"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */
{"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */
{"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */
{"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */
{"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */
{"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */
{"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
{"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
{"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
{"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
{"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
{"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
{"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
{"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
{"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
{"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
{"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
{"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
{"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
{"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst },
{"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst },
{"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
{"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst },
{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
{"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
{"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst },
{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
{"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
{"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst },
{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
{"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
{"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst },
{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
{"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
{"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst },
{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
{"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
{"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst },
{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
{"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
{"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst },
{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
{"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst },
{"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst },
{"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst },
{"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst },
{"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
{"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst },
{"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst },
{"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst },
{"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst },
{"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst },
{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
{"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst },
{"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst },
{"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst },
{"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst },
{"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
{"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst },
{"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst },
{"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst },
{"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst },
{"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst },
{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
{"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst },
{"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst },
{"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst },
{"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst },
{"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
{"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst },
{"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst },
{"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst },
{"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst },
{"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst },
{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
{"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst },
{"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst },
{"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst },
{"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst },
{"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
{"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst },
{"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst },
{"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst },
{"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst },
{"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst },
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
};
/* Prefix for register names. */
char register_prefix[] = "r";
char special_register_prefix[] = "spr";
char fsl_register_prefix[] = "rfsl";
char pvr_register_prefix[] = "rpvr";
/* #defines for valid immediate range. */
#define MIN_IMM ((int) 0x80000000)
#define MAX_IMM ((int) 0x7fffffff)
#define MIN_IMM15 ((int) 0x0000)
#define MAX_IMM15 ((int) 0x7fff)
#endif /* MICROBLAZE_OPC */

139
opcodes/microblaze-opcm.h Normal file
View File

@ -0,0 +1,139 @@
/* microblaze-opcm.h -- Header used in microblaze-opc.h
Copyright 2009 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef MICROBLAZE_OPCM
#define MICROBLAZE_OPCM
enum microblaze_instr
{
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,
tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
eget, ecget, neget, necget, eput, ecput, neput, necput,
teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
aget, caget, naget, ncaget, aput, caput, naput, ncaput,
taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
invalid_inst
};
enum microblaze_instr_type
{
arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
return_inst, immediate_inst, special_inst, memory_load_inst,
memory_store_inst, barrel_shift_inst, anyware_inst
};
#define INST_WORD_SIZE 4
/* Gen purpose regs go from 0 to 31. */
/* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */
#define REG_PC_MASK 0x8000
#define REG_MSR_MASK 0x8001
#define REG_EAR_MASK 0x8003
#define REG_ESR_MASK 0x8005
#define REG_FSR_MASK 0x8007
#define REG_BTR_MASK 0x800b
#define REG_EDR_MASK 0x800d
#define REG_PVR_MASK 0xa000
#define REG_PID_MASK 0x9000
#define REG_ZPR_MASK 0x9001
#define REG_TLBX_MASK 0x9002
#define REG_TLBLO_MASK 0x9003
#define REG_TLBHI_MASK 0x9004
#define REG_TLBSX_MASK 0x9005
#define MIN_REGNUM 0
#define MAX_REGNUM 31
#define MIN_PVR_REGNUM 0
#define MAX_PVR_REGNUM 15
#define REG_PC 32 /* PC. */
#define REG_MSR 33 /* Machine status reg. */
#define REG_EAR 35 /* Exception reg. */
#define REG_ESR 37 /* Exception reg. */
#define REG_FSR 39 /* FPU Status reg. */
#define REG_BTR 43 /* Branch Target reg. */
#define REG_EDR 45 /* Exception reg. */
#define REG_PVR 40960 /* Program Verification reg. */
#define REG_PID 36864 /* MMU: Process ID reg. */
#define REG_ZPR 36865 /* MMU: Zone Protect reg. */
#define REG_TLBX 36866 /* MMU: TLB Index reg. */
#define REG_TLBLO 36867 /* MMU: TLB Low reg. */
#define REG_TLBHI 36868 /* MMU: TLB High reg. */
#define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */
/* Alternate names for gen purpose regs. */
#define REG_SP 1 /* stack pointer. */
#define REG_ROSDP 2 /* read-only small data pointer. */
#define REG_RWSDP 13 /* read-write small data pointer. */
/* Assembler Register - Used in Delay Slot Optimization. */
#define REG_AS 18
#define REG_ZERO 0
#define RD_LOW 21 /* Low bit for RD. */
#define RA_LOW 16 /* Low bit for RA. */
#define RB_LOW 11 /* Low bit for RB. */
#define IMM_LOW 0 /* Low bit for immediate. */
#define RD_MASK 0x03E00000
#define RA_MASK 0x001F0000
#define RB_MASK 0x0000F800
#define IMM_MASK 0x0000FFFF
/* Imm mask for barrel shifts. */
#define IMM5_MASK 0x0000001F
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F
/* Imm mask for msrset, msrclr instructions. */
#define IMM15_MASK 0x00007FFF
#endif /* MICROBLAZE-OPCM */