* cgen-opc.c (cgen_set_cpu): Initialize hardware table.
* m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Update.
This commit is contained in:
Doug Evans
parent
a4f6f75ff9
commit
7c26196f5a
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@ -1,3 +1,18 @@
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Tue Feb 3 17:19:40 1998 Doug Evans <devans@seba.cygnus.com>
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* cgen-opc.c (cgen_set_cpu): Initialize hardware table.
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* m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate.
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Mon Feb 2 19:22:15 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU>
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* tic30-dis.c: New file.
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* disassemble.c (disassembler): Add bfd_arch_tic30 case.
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* configure.in: Handle bfd_tic30_arch.
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* Makefile.am: Rebuild dependencies.
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(CFILES): Add tic30-dis.c
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(ALL_MACHINES): Add tic30-dis.lo.
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* configure, Makefile.in: Rebuild.
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start-sanitize-m32rx
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Mon Feb 2 11:04:08 1998 Nick Clifton <nickc@cygnus.com>
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1147
opcodes/m32r-opc.c
1147
opcodes/m32r-opc.c
File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,7 @@
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/* Instruction description for m32r.
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This file is machine generated with CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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@ -30,6 +32,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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/* Selected cpu families. */
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#define HAVE_CPU_M32R
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/* start-sanitize-m32rx */
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#define HAVE_CPU_M32RX
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/* end-sanitize-m32rx */
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#define CGEN_WORD_BITSIZE 32
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#define CGEN_DEFAULT_INSN_BITSIZE 32
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@ -40,14 +45,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
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#define CGEN_INT_INSN
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/* +1 because the first entry is reserved (null) */
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#define CGEN_NUM_INSNS (127 + 1)
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#define CGEN_NUM_OPERANDS (21)
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/* Number of non-boolean attributes. */
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#define CGEN_MAX_INSN_ATTRS 0
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#define CGEN_MAX_OPERAND_ATTRS 0
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/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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@ -55,102 +52,250 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Number of architecture variants. */
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#define MAX_MACHS 1
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/* Enums. */
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/* Enum declaration for insn format enums. */
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typedef enum insn_op1 {
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OP1_0 = 0, OP1_1 = 1, OP1_2 = 2, OP1_3 = 3,
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OP1_4 = 4, OP1_5 = 5, OP1_6 = 6, OP1_7 = 7,
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OP1_8 = 8, OP1_9 = 9, OP1_10 = 10, OP1_11 = 11,
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OP1_12 = 12, OP1_13 = 13, OP1_14 = 14, OP1_15 = 15
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OP1_0, OP1_1, OP1_2, OP1_3
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, OP1_4, OP1_5, OP1_6, OP1_7
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, OP1_8, OP1_9, OP1_10, OP1_11
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, OP1_12, OP1_13, OP1_14, OP1_15
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} INSN_OP1;
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/* Enum declaration for op2 enums. */
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typedef enum insn_op2 {
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OP2_0 = 0, OP2_1 = 1, OP2_2 = 2, OP2_3 = 3,
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OP2_4 = 4, OP2_5 = 5, OP2_6 = 6, OP2_7 = 7,
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OP2_8 = 8, OP2_9 = 9, OP2_10 = 10, OP2_11 = 11,
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OP2_12 = 12, OP2_13 = 13, OP2_14 = 14, OP2_15 = 15
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OP2_0, OP2_1, OP2_2, OP2_3
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, OP2_4, OP2_5, OP2_6, OP2_7
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, OP2_8, OP2_9, OP2_10, OP2_11
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, OP2_12, OP2_13, OP2_14, OP2_15
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} INSN_OP2;
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/* Enum declaration for m32r operand types. */
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typedef enum cgen_operand_type {
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M32R_OPERAND_PC = 0, M32R_OPERAND_SR = 1, M32R_OPERAND_DR = 2, M32R_OPERAND_SRC1 = 3,
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M32R_OPERAND_SRC2 = 4, M32R_OPERAND_SCR = 5, M32R_OPERAND_DCR = 6, M32R_OPERAND_SIMM8 = 7,
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M32R_OPERAND_SIMM16 = 8, M32R_OPERAND_UIMM4 = 9, M32R_OPERAND_UIMM5 = 10, M32R_OPERAND_UIMM16 = 11,
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M32R_OPERAND_HI16 = 12, M32R_OPERAND_SLO16 = 13, M32R_OPERAND_ULO16 = 14, M32R_OPERAND_UIMM24 = 15,
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M32R_OPERAND_DISP8 = 16, M32R_OPERAND_DISP16 = 17, M32R_OPERAND_DISP24 = 18, M32R_OPERAND_CONDBIT = 19,
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M32R_OPERAND_ACCUM = 20
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M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
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, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
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, M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ACCS
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/* end-sanitize-m32rx */
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ACC
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/* end-sanitize-m32rx */
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, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24
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, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT
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, M32R_OPERAND_ACCUM
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/* start-sanitize-m32rx */
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, M32R_OPERAND_ABORT_PARALLEL_EXECUTION
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/* end-sanitize-m32rx */
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, M32R_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Non-boolean attributes. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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MACH_M32R = 0
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MACH_M32R
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/* start-sanitize-m32rx */
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, MACH_M32RX
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/* end-sanitize-m32rx */
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, MACH_MAX
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} MACH_ATTR;
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/* start-sanitize-m32rx */
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/* Enum declaration for parallel execution pipeline selection. */
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typedef enum pipe_attr {
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PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
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} PIPE_ATTR;
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/* end-sanitize-m32rx */
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/* Number of architecture variants. */
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#define MAX_MACHS ((int) MACH_MAX)
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/* Number of operands. */
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#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
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/* Operand and instruction attribute indices. */
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC,
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CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT,
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CGEN_OPERAND_UNSIGNED
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CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PC
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, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_UNSIGNED
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand. */
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#define CGEN_OPERAND_MAX_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
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/* Enum declaration for cgen_insn attrs. */
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typedef enum cgen_insn_attr {
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CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_RELAX,
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CGEN_INSN_RELAX_BC, CGEN_INSN_RELAX_BL, CGEN_INSN_RELAX_BNC, CGEN_INSN_RELAX_BRA,
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CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
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CGEN_INSN_MACH
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/* start-sanitize-m32rx */
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, CGEN_INSN_PIPE
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/* end-sanitize-m32rx */
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, CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_PARALLEL
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, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_UNCOND_CTI
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn. */
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#define CGEN_INSN_MAX_ATTRS ((int) CGEN_INSN_ALIAS)
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/* Insn types are used by the simulator. */
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/* Enum declaration for m32r instruction types. */
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typedef enum cgen_insn_type {
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M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND,
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M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR,
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M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3,
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M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC8_S, M32R_INSN_BC24,
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M32R_INSN_BC24_L, M32R_INSN_BEQ, M32R_INSN_BEQZ, M32R_INSN_BGEZ,
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M32R_INSN_BGTZ, M32R_INSN_BLEZ, M32R_INSN_BLTZ, M32R_INSN_BNEZ,
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M32R_INSN_BL8, M32R_INSN_BL8_S, M32R_INSN_BL24, M32R_INSN_BL24_L,
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M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L,
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M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24,
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M32R_INSN_BRA24_L, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU,
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M32R_INSN_CMPUI, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM,
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M32R_INSN_REMU, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD,
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M32R_INSN_LD_2, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB,
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M32R_INSN_LDB_2, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH,
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M32R_INSN_LDH_2, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB,
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M32R_INSN_LDUB_2, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH,
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M32R_INSN_LDUH_2, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS,
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M32R_INSN_LD24, M32R_INSN_LDI8, M32R_INSN_LDI8A, M32R_INSN_LDI16,
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M32R_INSN_LDI16A, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACLO,
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M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI,
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M32R_INSN_MULLO, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV,
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M32R_INSN_MVFACHI, M32R_INSN_MVFACLO, M32R_INSN_MVFACMI, M32R_INSN_MVFC,
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M32R_INSN_MVTACHI, M32R_INSN_MVTACLO, M32R_INSN_MVTC, M32R_INSN_NEG,
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M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC, M32R_INSN_RACH,
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M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3,
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M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI,
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M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST,
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M32R_INSN_ST_2, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB,
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M32R_INSN_STB_2, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH,
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M32R_INSN_STH_2, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS,
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M32R_INSN_ST_MINUS, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX,
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M32R_INSN_TRAP, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP,
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M32R_INSN_MAX
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M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_ADD3_A
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, M32R_INSN_AND, M32R_INSN_AND3, M32R_INSN_AND3_A, M32R_INSN_OR
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, M32R_INSN_OR3, M32R_INSN_OR3_A, M32R_INSN_XOR, M32R_INSN_XOR3
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, M32R_INSN_XOR3_A, M32R_INSN_ADDI, M32R_INSN_ADDI_A, M32R_INSN_ADDV
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, M32R_INSN_ADDV3, M32R_INSN_ADDV3_A, M32R_INSN_ADDX, M32R_INSN_BC8
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, M32R_INSN_BC8_S, M32R_INSN_BC24, M32R_INSN_BC24_L, M32R_INSN_BEQ
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, M32R_INSN_BEQZ, M32R_INSN_BGEZ, M32R_INSN_BGTZ, M32R_INSN_BLEZ
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, M32R_INSN_BLTZ, M32R_INSN_BNEZ, M32R_INSN_BL8, M32R_INSN_BL8_S
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, M32R_INSN_BL24, M32R_INSN_BL24_L
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/* start-sanitize-m32rx */
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, M32R_INSN_BCL8
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/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
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, M32R_INSN_BCL8_S
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/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
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, M32R_INSN_BCL24
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
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||||
, M32R_INSN_BCL24_L
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/* end-sanitize-m32rx */
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, M32R_INSN_BNC8, M32R_INSN_BNC8_S, M32R_INSN_BNC24, M32R_INSN_BNC24_L
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, M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA8_S, M32R_INSN_BRA24
|
||||
, M32R_INSN_BRA24_L
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL8
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL8_S
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL24
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_BNCL24_L
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPI_A, M32R_INSN_CMPU
|
||||
, M32R_INSN_CMPUI, M32R_INSN_CMPUI_A
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_CMPEQ
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_CMPZ
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_DIV, M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_JC
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_JNC
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD, M32R_INSN_LD_2
|
||||
, M32R_INSN_LD_D, M32R_INSN_LD_D2, M32R_INSN_LDB, M32R_INSN_LDB_2
|
||||
, M32R_INSN_LDB_D, M32R_INSN_LDB_D2, M32R_INSN_LDH, M32R_INSN_LDH_2
|
||||
, M32R_INSN_LDH_D, M32R_INSN_LDH_D2, M32R_INSN_LDUB, M32R_INSN_LDUB_2
|
||||
, M32R_INSN_LDUB_D, M32R_INSN_LDUB_D2, M32R_INSN_LDUH, M32R_INSN_LDUH_2
|
||||
, M32R_INSN_LDUH_D, M32R_INSN_LDUH_D2, M32R_INSN_LD_PLUS, M32R_INSN_LD24
|
||||
, M32R_INSN_LD24_A, M32R_INSN_LDI8, M32R_INSN_LDI8_A, M32R_INSN_LDI8A
|
||||
, M32R_INSN_LDI8A_A, M32R_INSN_LDI16, M32R_INSN_LDI16A, M32R_INSN_LOCK
|
||||
, M32R_INSN_MACHI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MACHI_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MACLO
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MACLO_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MACWHI, M32R_INSN_MACWLO, M32R_INSN_MUL, M32R_INSN_MULHI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MULHI_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MULLO
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MULLO_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MULWHI, M32R_INSN_MULWLO, M32R_INSN_MV, M32R_INSN_MVFACHI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MVFACHI_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MVFACLO
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MVFACLO_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MVFACMI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MVFACMI_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MVFC, M32R_INSN_MVTACHI
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MVTACHI_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MVTACLO
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MVTACLO_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
|
||||
, M32R_INSN_RAC
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RAC_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_RACH
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_RACH_A
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SETH_A, M32R_INSN_SLL
|
||||
, M32R_INSN_SLL3, M32R_INSN_SLL3_A, M32R_INSN_SLLI, M32R_INSN_SLLI_A
|
||||
, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRA3_A, M32R_INSN_SRAI
|
||||
, M32R_INSN_SRAI_A, M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRL3_A
|
||||
, M32R_INSN_SRLI, M32R_INSN_SRLI_A, M32R_INSN_ST, M32R_INSN_ST_2
|
||||
, M32R_INSN_ST_D, M32R_INSN_ST_D2, M32R_INSN_STB, M32R_INSN_STB_2
|
||||
, M32R_INSN_STB_D, M32R_INSN_STB_D2, M32R_INSN_STH, M32R_INSN_STH_2
|
||||
, M32R_INSN_STH_D, M32R_INSN_STH_D2, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS
|
||||
, M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
|
||||
, M32R_INSN_TRAP_A, M32R_INSN_UNLOCK, M32R_INSN_PUSH, M32R_INSN_POP
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SATB
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SATH
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SAT
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_PCMPBZ
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SADD
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MACWU1
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MSBLO
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MULWU1
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_MACHL1
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SC
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
, M32R_INSN_SNC
|
||||
/* end-sanitize-m32rx */
|
||||
, M32R_INSN_MAX
|
||||
} CGEN_INSN_TYPE;
|
||||
|
||||
/* Index of `illegal' insn place holder. */
|
||||
#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
|
||||
/* Total number of insns in table. */
|
||||
#define CGEN_MAX_INSNS ((int) M32R_INSN_MAX)
|
||||
#define MAX_INSNS ((int) M32R_INSN_MAX)
|
||||
|
||||
/* cgen.h uses things we just defined. */
|
||||
#include "opcode/cgen.h"
|
||||
|
|
@ -175,6 +320,18 @@ typedef struct cgen_fields
|
|||
long f_disp8;
|
||||
long f_disp16;
|
||||
long f_disp24;
|
||||
/* start-sanitize-m32rx */
|
||||
long f_op23;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_op3;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_acc;
|
||||
/* end-sanitize-m32rx */
|
||||
/* start-sanitize-m32rx */
|
||||
long f_accs;
|
||||
/* end-sanitize-m32rx */
|
||||
int length;
|
||||
} CGEN_FIELDS;
|
||||
|
||||
|
|
@ -182,9 +339,11 @@ typedef struct cgen_fields
|
|||
extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
|
||||
extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
|
||||
|
||||
extern CGEN_KEYWORD m32r_cgen_opval_mach;
|
||||
extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
|
||||
extern CGEN_KEYWORD m32r_cgen_opval_h_cr;
|
||||
/* start-sanitize-m32rx */
|
||||
extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
|
||||
/* end-sanitize-m32rx */
|
||||
|
||||
#define CGEN_INIT_PARSE() \
|
||||
{\
|
||||
|
|
|
|||
Loading…
Reference in New Issue