Fix typos in error and option messages in OPCODES library.
PR 21739 opcodes * arc-opc.c (insert_rhv2): Use lower case first letter in error message. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_r13el): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pclel): Likewise. (insert_nps_bitop_size_2b): Likewise. (insert_nps_imm_offset): Likewise. (insert_nps_imm_entry): Likewise. (insert_nps_size_16bit): Likewise. (insert_nps_##NAME##_pos): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_bitop_ins_ext): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_min_hofs): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_rbdouble_64): Likewise. (insert_nps_misc_imm_offset): Likewise. * riscv-dis.c (print_riscv_disassembler_options): Fix typo in option description. gas * testsuite/gas/arc/add_s-err.s: Update expected error message.
This commit is contained in:
Nick Clifton
parent
46a62268b8
commit
7cbc739c71
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@ -1,3 +1,8 @@
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2017-07-25 Nick Clifton <nickc@redhat.com>
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PR 21739
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* testsuite/gas/arc/add_s-err.s: Update expected error message.
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2017-07-24 Nick Clifton <nickc@redhat.com>
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PR 21809
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@ -4,7 +4,7 @@
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; { dg-do assemble { target arc*-*-* } }
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; { dg-options "--mcpu=arc700" }
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;; The following insns are accepted by ARCv2 only
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add_s r4,r4,-1 ; { dg-error "Error: Register must be either r0-r3 or r12-r15 for instruction." }
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add_s r4,r4,-1 ; { dg-error "Error: register must be either r0-r3 or r12-r15 for instruction" }
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add_s 0,0xAAAA5555,-1 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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add_s r0,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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add_s r1,r15,0x20 ; { dg-error "Error: inappropriate arguments for opcode 'add_s'" }
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@ -1,3 +1,42 @@
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2017-07-25 Nick Clifton <nickc@redhat.com>
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PR 21739
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* arc-opc.c (insert_rhv2): Use lower case first letter in error
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message.
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(insert_r0): Likewise.
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(insert_r1): Likewise.
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(insert_r2): Likewise.
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(insert_r3): Likewise.
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(insert_sp): Likewise.
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(insert_gp): Likewise.
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(insert_pcl): Likewise.
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(insert_blink): Likewise.
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(insert_ilink1): Likewise.
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(insert_ilink2): Likewise.
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(insert_ras): Likewise.
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(insert_rbs): Likewise.
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(insert_rcs): Likewise.
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(insert_simm3s): Likewise.
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(insert_rrange): Likewise.
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(insert_r13el): Likewise.
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(insert_fpel): Likewise.
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(insert_blinkel): Likewise.
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(insert_pclel): Likewise.
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(insert_nps_bitop_size_2b): Likewise.
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(insert_nps_imm_offset): Likewise.
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(insert_nps_imm_entry): Likewise.
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(insert_nps_size_16bit): Likewise.
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(insert_nps_##NAME##_pos): Likewise.
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(insert_nps_##NAME): Likewise.
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(insert_nps_bitop_ins_ext): Likewise.
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(insert_nps_##NAME): Likewise.
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(insert_nps_min_hofs): Likewise.
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(insert_nps_##NAME): Likewise.
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(insert_nps_rbdouble_64): Likewise.
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(insert_nps_misc_imm_offset): Likewise.
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* riscv-dis.c (print_riscv_disassembler_options): Fix typo in
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option description.
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2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
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Jiong Wang <jiong.wang@arm.com>
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@ -170,7 +170,7 @@ insert_rhv2 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value == 0x1E)
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*errmsg = _("Register R30 is a limm indicator");
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*errmsg = _("register R30 is a limm indicator");
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return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
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}
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@ -189,7 +189,7 @@ insert_r0 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 0)
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*errmsg = _("Register must be R0");
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*errmsg = _("register must be R0");
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return insn;
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}
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@ -207,7 +207,7 @@ insert_r1 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 1)
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*errmsg = _("Register must be R1");
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*errmsg = _("register must be R1");
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return insn;
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}
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@ -224,7 +224,7 @@ insert_r2 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 2)
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*errmsg = _("Register must be R2");
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*errmsg = _("register must be R2");
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return insn;
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}
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@ -241,7 +241,7 @@ insert_r3 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 3)
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*errmsg = _("Register must be R3");
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*errmsg = _("register must be R3");
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return insn;
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}
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@ -258,7 +258,7 @@ insert_sp (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 28)
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*errmsg = _("Register must be SP");
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*errmsg = _("register must be SP");
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return insn;
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}
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@ -275,7 +275,7 @@ insert_gp (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 26)
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*errmsg = _("Register must be GP");
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*errmsg = _("register must be GP");
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return insn;
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}
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@ -292,7 +292,7 @@ insert_pcl (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 63)
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*errmsg = _("Register must be PCL");
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*errmsg = _("register must be PCL");
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return insn;
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}
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@ -309,7 +309,7 @@ insert_blink (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 31)
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*errmsg = _("Register must be BLINK");
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*errmsg = _("register must be BLINK");
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return insn;
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}
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@ -326,7 +326,7 @@ insert_ilink1 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 29)
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*errmsg = _("Register must be ILINK1");
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*errmsg = _("register must be ILINK1");
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return insn;
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}
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@ -343,7 +343,7 @@ insert_ilink2 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value != 30)
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*errmsg = _("Register must be ILINK2");
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*errmsg = _("register must be ILINK2");
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return insn;
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}
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@ -374,7 +374,7 @@ insert_ras (unsigned long long insn,
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insn |= (value - 8);
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break;
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default:
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*errmsg = _("Register must be either r0-r3 or r12-r15");
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*errmsg = _("register must be either r0-r3 or r12-r15");
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break;
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}
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return insn;
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@ -412,7 +412,7 @@ insert_rbs (unsigned long long insn,
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insn |= ((value - 8)) << 8;
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break;
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default:
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*errmsg = _("Register must be either r0-r3 or r12-r15");
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*errmsg = _("register must be either r0-r3 or r12-r15");
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break;
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}
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return insn;
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@ -450,7 +450,7 @@ insert_rcs (unsigned long long insn,
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insn |= ((value - 8)) << 5;
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break;
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default:
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*errmsg = _("Register must be either r0-r3 or r12-r15");
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*errmsg = _("register must be either r0-r3 or r12-r15");
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break;
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}
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return insn;
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@ -501,7 +501,7 @@ insert_simm3s (unsigned long long insn,
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tmp = 0x06;
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break;
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default:
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*errmsg = _("Accepted values are from -1 to 6");
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*errmsg = _("accepted values are from -1 to 6");
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break;
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}
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@ -530,9 +530,9 @@ insert_rrange (unsigned long long insn,
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int reg2 = value & 0xFFFF;
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if (reg1 != 13)
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*errmsg = _("First register of the range should be r13");
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*errmsg = _("first register of the range should be r13");
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else if (reg2 < 13 || reg2 > 26)
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*errmsg = _("Last register of the range doesn't fit");
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*errmsg = _("last register of the range doesn't fit");
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else
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insn |= ((reg2 - 12) & 0x0F) << 1;
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return insn;
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@ -552,7 +552,7 @@ insert_r13el (unsigned long long insn,
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{
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if (value != 13)
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{
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*errmsg = _("Invalid register number, should be fp");
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*errmsg = _("invalid register number, should be fp");
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return insn;
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}
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@ -567,7 +567,7 @@ insert_fpel (unsigned long long insn,
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{
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if (value != 27)
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{
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*errmsg = _("Invalid register number, should be fp");
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*errmsg = _("invalid register number, should be fp");
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return insn;
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}
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@ -589,7 +589,7 @@ insert_blinkel (unsigned long long insn,
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{
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if (value != 31)
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{
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*errmsg = _("Invalid register number, should be blink");
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*errmsg = _("invalid register number, should be blink");
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return insn;
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}
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@ -611,7 +611,7 @@ insert_pclel (unsigned long long insn,
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{
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if (value != 63)
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{
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*errmsg = _("Invalid register number, should be pcl");
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*errmsg = _("invalid register number, should be pcl");
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return insn;
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}
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@ -715,7 +715,7 @@ insert_nps_3bit_reg_at_##OFFSET##_##NAME \
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insn |= (value - 8) << (OFFSET); \
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break; \
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default: \
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*errmsg = _("Register must be either r0-r3 or r12-r15"); \
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*errmsg = _("register must be either r0-r3 or r12-r15"); \
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break; \
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} \
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return insn; \
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@ -763,7 +763,7 @@ insert_nps_bitop_size_2b (unsigned long long insn,
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break;
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default:
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value = 0;
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*errmsg = _("Invalid size, should be 1, 2, 4, or 8");
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*errmsg = _("invalid size, should be 1, 2, 4, or 8");
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break;
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}
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@ -874,7 +874,7 @@ insert_nps_imm_offset (unsigned long long insn,
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value = value >> 4;
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break;
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default:
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*errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64.");
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*errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
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value = 0;
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}
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insn |= (value << 10);
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@ -908,7 +908,7 @@ insert_nps_imm_entry (unsigned long long insn,
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value = 3;
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break;
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default:
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*errmsg = _("Invalid position, should be 16, 32, 64 or 128.");
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*errmsg = _("invalid position, should be 16, 32, 64 or 128.");
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value = 0;
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}
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insn |= (value << 2);
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@ -930,7 +930,7 @@ insert_nps_size_16bit (unsigned long long insn,
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{
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if ((value < 1) || (value > 64))
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{
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*errmsg = _("Invalid size value must be on range 1-64.");
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*errmsg = _("invalid size value must be on range 1-64.");
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value = 0;
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}
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value = value & 0x3f;
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@ -961,7 +961,7 @@ insert_nps_##NAME##_pos (unsigned long long insn, \
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value = value / 8; \
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break; \
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default: \
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*errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
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*errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
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value = 0; \
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} \
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insn |= (value << SHIFT); \
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@ -986,7 +986,7 @@ insert_nps_##NAME (unsigned long long insn, \
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{ \
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if (value < LOWER || value > UPPER) \
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{ \
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*errmsg = _("Invalid size, value must be " \
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*errmsg = _("invalid size, value must be " \
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#LOWER " to " #UPPER "."); \
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return insn; \
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} \
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@ -1122,7 +1122,7 @@ insert_nps_bitop_ins_ext (unsigned long long insn,
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const char ** errmsg)
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{
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if (value < 0 || value > 28)
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*errmsg = _("Value must be in the range 0 to 28");
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*errmsg = _("value must be in the range 0 to 28");
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return insn | (value << 20);
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}
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@ -1144,7 +1144,7 @@ insert_nps_##NAME (unsigned long long insn, \
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const char ** errmsg) \
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{ \
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if (value < 1 || value > UPPER) \
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*errmsg = _("Value must be in the range 1 to " #UPPER); \
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*errmsg = _("value must be in the range 1 to " #UPPER); \
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if (value == UPPER) \
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value = 0; \
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return insn | (value << SHIFT); \
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@ -1174,9 +1174,9 @@ insert_nps_min_hofs (unsigned long long insn,
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const char ** errmsg)
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{
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if (value < 0 || value > 240)
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*errmsg = _("Value must be in the range 0 to 240");
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*errmsg = _("value must be in the range 0 to 240");
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if ((value % 16) != 0)
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*errmsg = _("Value must be a multiple of 16");
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*errmsg = _("value must be a multiple of 16");
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value = value / 16;
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return insn | (value << 6);
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}
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@ -1196,7 +1196,7 @@ insert_nps_##NAME (unsigned long long insn, \
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const char ** errmsg) \
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{ \
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if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
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*errmsg = _("Invalid address type for operand"); \
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*errmsg = _("invalid address type for operand"); \
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return insn; \
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} \
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\
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@ -1230,7 +1230,7 @@ insert_nps_rbdouble_64 (unsigned long long insn,
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const char ** errmsg)
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{
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if (value < 0 || value > 31)
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*errmsg = _("Value must be in the range 0 to 31");
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*errmsg = _("value must be in the range 0 to 31");
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return insn | (value << 43) | (value << 48);
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}
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@ -1255,7 +1255,7 @@ insert_nps_misc_imm_offset (unsigned long long insn,
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{
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if (value & 0x3)
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{
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*errmsg = _("Invalid position, should be 0,4, 8,...124.");
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*errmsg = _("invalid position, should be one of: 0,4,8,...124.");
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value = 0;
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}
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insn |= (value << 6);
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@ -498,7 +498,7 @@ The following RISC-V-specific disassembler options are supported for use\n\
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with the -M switch (multiple options should be separated by commas):\n"));
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fprintf (stream, _("\n\
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numeric Print numeric reigster names, rather than ABI names.\n"));
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numeric Print numeric register names, rather than ABI names.\n"));
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fprintf (stream, _("\n\
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no-aliases Disassemble only into canonical instructions, rather\n\
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