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* NEWS: Document target described register support for PowerPC. 

* ppc-tdep.h: Remove ppc_spr constants.
	(struct gdbarch_tdep): Remove regs, ppc_sr0_regnum, and
	ppc_builtin_type_vec128 members.
	(PPC_R0_REGNUM, PPC_F0_REGNUM, PPC_PC_REGNUM, PPC_MSR_REGNUM)
	(PPC_CR_REGNUM, PPC_LR_REGNUM, PPC_CTR_REGNUM, PPC_XER_REGNUM)
	(PPC_FPSCR_REGNUM, PPC_MQ_REGNUM, PPC_SPE_UPPER_GP0_REGNUM)
	(PPC_SPE_ACC_REGNUM, PPC_SPE_FSCR_REGNUM, PPC_VR0_REGNUM)
	(PPC_VSCR_REGNUM, PPC_VRSAVE_REGNUM, PPC_NUM_REGS): New constants.
	* rs6000-tdep.c: Include preparsed descriptions.
	(init_sim_regno_table): Do not iterate over pseudo registers.
	Look up segment registers by name.  Use sim_spr_register_name
	for SPRs.
	(rs6000_register_sim_regno): Call init_sim_regno_table here.
	(rs6000_builtin_type_vec128): Delete.
	(rs6000_register_name): Only handle SPE pseudo registers and upper
	halves.  Call tdesc_register_name for everything else.
	(rs6000_register_type): Delete.  Replace with...
	(rs6000_pseudo_register_type): ...this new function.  Only handle
	SPE pseudo registers.
	(rs6000_register_reggroup_p): Delete.  Replace with...
	(rs6000_pseudo_register_reggroup_p): ...this new function.  Only
	handle SPE pseudo registers.
	(rs6000_convert_register_p): Use ppc_fp0_regnum instead of
	"struct reg".
	(rs6000_register_to_value, rs6000_value_to_register): Remove check
	of reg->fpr.
	(e500_register_reggroup_p): Delete.
	(STR, R, R4, R8, R16, F, P8, R32, R64, R0, A4, S, S4, SN4, S64)
	(COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_UISA_NOFP_SPRS)
	(PPC_SEGMENT_REGS, PPC_OEA_SPRS, PPC_ALTIVEC_REGS, PPC_SPE_GP_REGS)
	(PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): Delete macros.
	(registers_powerpc, registers_403, registers_403GC, registers_505)
	(registers_860, registers_601, registers_602, registers_603)
	(registers_604, registers_750, registers_7400, registers_e500): Delete
	variables.
	(struct variant): Delete nregs, npregs, num_tot_regs, and regs.  Add
	tdesc.
	(tot_num_registers, num_registers, num_pseudo_registers): Delete.
	(variants): Delete outdated comment.  Use standard target descriptions
	instead of "struct reg" arrays.
	(init_variants): Delete.
	(rs6000_gdbarch_init): Do not guess word size from the BFD
	architecture if we have a target description.  Select a variant
	before creating a new architecture.  Use the variant's target
	description if the target did not define a register layout.
	Validate target-supplied registers.  Reject mismatches.  Use
	fixed register numbers and new constants instead of magic
	numbers.  Call set_gdbarch_ps_regnum.  Call tdesc_use_registers.
	(_initialize_rs6000_tdep): Initialize the preparsed target
	descriptions.
	* target-descriptions.c (tdesc_predefined_types): Add int128 and
	uint128.
	(tdesc_find_register_early): New function.
	(tdesc_numbered_register): Use it.
	(tdesc_register_size): New function.
	(tdesc_use_registers): Take a target_desc argument.  Do not use
	gdbarch_target_desc.
	* target-descriptions.h (tdesc_use_registers): Update prototype
	and comment.
	(tdesc_register_size): New prototype.
	* Makefile.in (powerpc_32_c, powerpc_403_c, powerpc_403gc_c)
	(powerpc_505_c, powerpc_601_c, powerpc_602_c, powerpc_603_c)
	(powerpc_604_c, powerpc_64_c, powerpc_7400_c, powerpc_750_c)
	(powerpc_860_c, powerpc_e500_c, rs6000_c): New macros.
	(rs6000-tdep.o): Update.
	* arm-tdep.c (arm_gdbarch_init): Update call to tdesc_use_registers.
	* m68k-tdep.c (m68k_gdbarch_init): Likewise.
	* mips-tdep.c (mips_gdbarch_init): Likewise.

	* gdb.texinfo (Predefined Target Types): Add int128
	and uint128.
	(Standard Target Features): Add PowerPC features.

	* gdb.xml/tdesc-regs.exp: Add PowerPC support.

	* sim-ppc.h (sim_spr_register_name): New prototype.

	* gdb-sim.c (regnum2spr): Rename to...
	(sim_spr_register_name): ... this.  Make global.
This commit is contained in:
Daniel Jacobowitz 2007-10-15 19:45:31 +00:00
parent 324300c09f
commit 7cc46491b1
18 changed files with 658 additions and 987 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

72
gdb/ChangeLog
View File

@ -1,3 +1,75 @@
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* NEWS: Document target described register support for PowerPC.
* ppc-tdep.h: Remove ppc_spr constants.
(struct gdbarch_tdep): Remove regs, ppc_sr0_regnum, and
ppc_builtin_type_vec128 members.
(PPC_R0_REGNUM, PPC_F0_REGNUM, PPC_PC_REGNUM, PPC_MSR_REGNUM)
(PPC_CR_REGNUM, PPC_LR_REGNUM, PPC_CTR_REGNUM, PPC_XER_REGNUM)
(PPC_FPSCR_REGNUM, PPC_MQ_REGNUM, PPC_SPE_UPPER_GP0_REGNUM)
(PPC_SPE_ACC_REGNUM, PPC_SPE_FSCR_REGNUM, PPC_VR0_REGNUM)
(PPC_VSCR_REGNUM, PPC_VRSAVE_REGNUM, PPC_NUM_REGS): New constants.
* rs6000-tdep.c: Include preparsed descriptions.
(init_sim_regno_table): Do not iterate over pseudo registers.
Look up segment registers by name. Use sim_spr_register_name
for SPRs.
(rs6000_register_sim_regno): Call init_sim_regno_table here.
(rs6000_builtin_type_vec128): Delete.
(rs6000_register_name): Only handle SPE pseudo registers and upper
halves. Call tdesc_register_name for everything else.
(rs6000_register_type): Delete. Replace with...
(rs6000_pseudo_register_type): ...this new function. Only handle
SPE pseudo registers.
(rs6000_register_reggroup_p): Delete. Replace with...
(rs6000_pseudo_register_reggroup_p): ...this new function. Only
handle SPE pseudo registers.
(rs6000_convert_register_p): Use ppc_fp0_regnum instead of
"struct reg".
(rs6000_register_to_value, rs6000_value_to_register): Remove check
of reg->fpr.
(e500_register_reggroup_p): Delete.
(STR, R, R4, R8, R16, F, P8, R32, R64, R0, A4, S, S4, SN4, S64)
(COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_UISA_NOFP_SPRS)
(PPC_SEGMENT_REGS, PPC_OEA_SPRS, PPC_ALTIVEC_REGS, PPC_SPE_GP_REGS)
(PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): Delete macros.
(registers_powerpc, registers_403, registers_403GC, registers_505)
(registers_860, registers_601, registers_602, registers_603)
(registers_604, registers_750, registers_7400, registers_e500): Delete
variables.
(struct variant): Delete nregs, npregs, num_tot_regs, and regs. Add
tdesc.
(tot_num_registers, num_registers, num_pseudo_registers): Delete.
(variants): Delete outdated comment. Use standard target descriptions
instead of "struct reg" arrays.
(init_variants): Delete.
(rs6000_gdbarch_init): Do not guess word size from the BFD
architecture if we have a target description. Select a variant
before creating a new architecture. Use the variant's target
description if the target did not define a register layout.
Validate target-supplied registers. Reject mismatches. Use
fixed register numbers and new constants instead of magic
numbers. Call set_gdbarch_ps_regnum. Call tdesc_use_registers.
(_initialize_rs6000_tdep): Initialize the preparsed target
descriptions.
* target-descriptions.c (tdesc_predefined_types): Add int128 and
uint128.
(tdesc_find_register_early): New function.
(tdesc_numbered_register): Use it.
(tdesc_register_size): New function.
(tdesc_use_registers): Take a target_desc argument. Do not use
gdbarch_target_desc.
* target-descriptions.h (tdesc_use_registers): Update prototype
and comment.
(tdesc_register_size): New prototype.
* Makefile.in (powerpc_32_c, powerpc_403_c, powerpc_403gc_c)
(powerpc_505_c, powerpc_601_c, powerpc_602_c, powerpc_603_c)
(powerpc_604_c, powerpc_64_c, powerpc_7400_c, powerpc_750_c)
(powerpc_860_c, powerpc_e500_c, rs6000_c): New macros.
(rs6000-tdep.o): Update.
* arm-tdep.c (arm_gdbarch_init): Update call to tdesc_use_registers.
* m68k-tdep.c (m68k_gdbarch_init): Likewise.
* mips-tdep.c (mips_gdbarch_init): Likewise.
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* features/rs6000/powerpc-32.c, features/rs6000/powerpc-403.c,

21
gdb/Makefile.in
View File

@ -888,6 +888,20 @@ features_headers = $(defs_h) $(gdbtypes_h) $(target_descriptions_h)
arm_with_iwmmxt_c = $(srcdir)/features/arm-with-iwmmxt.c $(features_headers)
mips_linux_c = $(srcdir)/features/mips-linux.c $(features_headers)
mips64_linux_c = $(srcdir)/features/mips64-linux.c $(features_headers)
powerpc_32_c = $(srcdir)/features/rs6000/powerpc-32.c $(features_headers)
powerpc_403_c = $(srcdir)/features/rs6000/powerpc-403.c $(features_headers)
powerpc_403gc_c = $(srcdir)/features/rs6000/powerpc-403gc.c $(features_headers)
powerpc_505_c = $(srcdir)/features/rs6000/powerpc-505.c $(features_headers)
powerpc_601_c = $(srcdir)/features/rs6000/powerpc-601.c $(features_headers)
powerpc_602_c = $(srcdir)/features/rs6000/powerpc-602.c $(features_headers)
powerpc_603_c = $(srcdir)/features/rs6000/powerpc-603.c $(features_headers)
powerpc_604_c = $(srcdir)/features/rs6000/powerpc-604.c $(features_headers)
powerpc_64_c = $(srcdir)/features/rs6000/powerpc-64.c $(features_headers)
powerpc_7400_c = $(srcdir)/features/rs6000/powerpc-7400.c $(features_headers)
powerpc_750_c = $(srcdir)/features/rs6000/powerpc-750.c $(features_headers)
powerpc_860_c = $(srcdir)/features/rs6000/powerpc-860.c $(features_headers)
powerpc_e500_c = $(srcdir)/features/rs6000/powerpc-e500.c $(features_headers)
rs6000_c = $(srcdir)/features/rs6000/rs6000.c $(features_headers)
# Header files that need to have srcdir added. Note that in the cases
# where we use a macro like $(gdbcmd_h), things are carefully arranged
@ -2543,7 +2557,12 @@ rs6000-tdep.o: rs6000-tdep.c $(defs_h) $(frame_h) $(inferior_h) $(symtab_h) \
$(reggroups_h) $(libbfd_h) $(coff_internal_h) $(libcoff_h) \
$(coff_xcoff_h) $(libxcoff_h) $(elf_bfd_h) $(solib_svr4_h) \
$(ppc_tdep_h) $(gdb_assert_h) $(dis_asm_h) $(trad_frame_h) \
$(frame_unwind_h) $(frame_base_h) $(rs6000_tdep_h) $(dwarf2_frame_h)
$(frame_unwind_h) $(frame_base_h) $(rs6000_tdep_h) $(dwarf2_frame_h) \
$(target_descriptions) $(user_regs_h) \
$(powerpc_32_c) $(powerpc_403_c) $(powerpc_403gc_c) $(powerpc_505_c) \
$(powerpc_601_c) $(powerpc_602_c) $(powerpc_603_c) $(powerpc_604_c) \
$(powerpc_64_c) $(powerpc_7400_c) $(powerpc_750_c) $(powerpc_860_c) \
$(powerpc_e500_c) $(rs6000_c)
rs6000-aix-tdep.o: rs6000-aix-tdep.c $(defs_h) $(gdb_string_h) $(osabi_h) \
$(regcache_h) $(regset_h) $(rs6000_tdep_h) $(ppc_tdep_h)
s390-nat.o: s390-nat.c $(defs_h) $(regcache_h) $(inferior_h) \

2
gdb/NEWS
View File

@ -10,6 +10,8 @@ is resolved.
including breakpoints on C++ constructors, inside C++ templates,
and in inlined functions.
* Target descriptions can now describe registers for PowerPC.
*** Changes in GDB 6.7
* Resolved 101 resource leaks, null pointer dereferences, etc. in gdb,

2
gdb/arm-tdep.c
View File

@ -3074,7 +3074,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
}
if (tdesc_data)
tdesc_use_registers (gdbarch, tdesc_data);
tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
/* Add standard register aliases. We add aliases even for those
nanes which are used by the current architecture - it's simpler,

6
gdb/doc/ChangeLog
View File

@ -1,3 +1,9 @@
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* gdb.texinfo (Predefined Target Types): Add int128
and uint128.
(Standard Target Features): Add PowerPC features.
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* gdb.texinfo (Maintenance Commands): Document "maint print c-tdesc".

25
gdb/doc/gdb.texinfo
View File

@ -26102,12 +26102,14 @@ types. The currently supported types are:
@itemx int16
@itemx int32
@itemx int64
@itemx int128
Signed integer types holding the specified number of bits.
@item uint8
@itemx uint16
@itemx uint32
@itemx uint64
@itemx uint128
Unsigned integer types holding the specified number of bits.
@item code_ptr
@ -26226,6 +26228,29 @@ This feature is optional. If present, it should contain registers
@samp{fpiaddr}.
@end table
@subsection PowerPC Features
@cindex target descriptions, PowerPC features
The @samp{org.gnu.gdb.power.core} feature is required for PowerPC
targets. It should contain registers @samp{r0} through @samp{r31},
@samp{pc}, @samp{msr}, @samp{cr}, @samp{lr}, @samp{ctr}, and
@samp{xer}. They may be 32-bit or 64-bit depending on the target.
The @samp{org.gnu.gdb.power.fpu} feature is optional. It should
contain registers @samp{f0} through @samp{f31} and @samp{fpscr}.
The @samp{org.gnu.gdb.power.altivec} feature is optional. It should
contain registers @samp{vr0} through @samp{vr31}, @samp{vscr},
and @samp{vrsave}.
The @samp{org.gnu.gdb.power.spe} feature is optional. It should
contain registers @samp{ev0h} through @samp{ev31h}, @samp{acc}, and
@samp{spefscr}. SPE targets should provide 32-bit registers in
@samp{org.gnu.gdb.power.core} and provide the upper halves in
@samp{ev0h} through @samp{ev31h}. @value{GDBN} will combine
these to present registers @samp{ev0} through @samp{ev31} to the
user.
@include gpl.texi
@raisesections

2
gdb/m68k-tdep.c
View File

@ -1257,7 +1257,7 @@ m68k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
frame_unwind_append_sniffer (gdbarch, m68k_frame_sniffer);
if (tdesc_data)
tdesc_use_registers (gdbarch, tdesc_data);
tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
return gdbarch;
}

2
gdb/mips-tdep.c
View File

@ -5649,7 +5649,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
if (tdesc_data)
{
set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
tdesc_use_registers (gdbarch, tdesc_data);
tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
/* Override the normal target description methods to handle our
dual real and pseudo registers. */

211
gdb/ppc-tdep.h
View File

@ -139,7 +139,6 @@ extern void ppc_collect_fpregset (const struct regset *regset,
struct gdbarch_tdep
{
int wordsize; /* size in bytes of fixed-point word */
const struct reg *regs; /* from current variant */
int ppc_gp0_regnum; /* GPR register 0 */
int ppc_toc_regnum; /* TOC register */
int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
@ -156,9 +155,6 @@ struct gdbarch_tdep
int ppc_fp0_regnum; /* floating-point register 0 */
int ppc_fpscr_regnum; /* fp status and condition register */
/* Segment registers. */
int ppc_sr0_regnum; /* segment register 0 */
/* Multiplier-Quotient Register (older POWER architectures only). */
int ppc_mq_regnum;
@ -186,7 +182,6 @@ struct gdbarch_tdep
/* ISA-specific types. */
struct type *ppc_builtin_type_vec64;
struct type *ppc_builtin_type_vec128;
};
@ -200,189 +195,31 @@ enum
};
/* Constants for SPR register numbers. These are *not* GDB register
numbers: they are the numbers used in the PowerPC ISA itself to
refer to these registers.
/* Register number constants. These are GDB internal register
numbers; they are not used for the simulator or remote targets.
Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
numbers above PPC_NUM_REGS. So are segment registers and other
target-defined registers. */
enum {
PPC_R0_REGNUM = 0,
PPC_F0_REGNUM = 32,
PPC_PC_REGNUM = 64,
PPC_MSR_REGNUM = 65,
PPC_CR_REGNUM = 66,
PPC_LR_REGNUM = 67,
PPC_CTR_REGNUM = 68,
PPC_XER_REGNUM = 69,
PPC_FPSCR_REGNUM = 70,
PPC_MQ_REGNUM = 71,
PPC_SPE_UPPER_GP0_REGNUM = 72,
PPC_SPE_ACC_REGNUM = 104,
PPC_SPE_FSCR_REGNUM = 105,
PPC_VR0_REGNUM = 106,
PPC_VSCR_REGNUM = 138,
PPC_VRSAVE_REGNUM = 139,
PPC_NUM_REGS
};
This table includes all the SPRs from all the variants I could find
documentation for.
There may be registers from different PowerPC variants assigned the
same number, but that's fine: GDB and the SIM always use the
numbers in the context of a particular variant, so it's not
ambiguous.
We need to deviate from the naming pattern when variants have
special-purpose registers of the same name, but with different
numbers. Fortunately, this is rare: look below to see how we
handle the 'tcr' registers on the 403/403GX and 602. */
enum
{
ppc_spr_mq = 0,
ppc_spr_xer = 1,
ppc_spr_rtcu = 4,
ppc_spr_rtcl = 5,
ppc_spr_lr = 8,
ppc_spr_ctr = 9,
ppc_spr_cnt = 9,
ppc_spr_dsisr = 18,
ppc_spr_dar = 19,
ppc_spr_dec = 22,
ppc_spr_sdr1 = 25,
ppc_spr_srr0 = 26,
ppc_spr_srr1 = 27,
ppc_spr_eie = 80,
ppc_spr_eid = 81,
ppc_spr_nri = 82,
ppc_spr_sp = 102,
ppc_spr_cmpa = 144,
ppc_spr_cmpb = 145,
ppc_spr_cmpc = 146,
ppc_spr_cmpd = 147,
ppc_spr_icr = 148,
ppc_spr_der = 149,
ppc_spr_counta = 150,
ppc_spr_countb = 151,
ppc_spr_cmpe = 152,
ppc_spr_cmpf = 153,
ppc_spr_cmpg = 154,
ppc_spr_cmph = 155,
ppc_spr_lctrl1 = 156,
ppc_spr_lctrl2 = 157,
ppc_spr_ictrl = 158,
ppc_spr_bar = 159,
ppc_spr_vrsave = 256,
ppc_spr_sprg0 = 272,
ppc_spr_sprg1 = 273,
ppc_spr_sprg2 = 274,
ppc_spr_sprg3 = 275,
ppc_spr_asr = 280,
ppc_spr_ear = 282,
ppc_spr_tbl = 284,
ppc_spr_tbu = 285,
ppc_spr_pvr = 287,
ppc_spr_spefscr = 512,
ppc_spr_ibat0u = 528,
ppc_spr_ibat0l = 529,
ppc_spr_ibat1u = 530,
ppc_spr_ibat1l = 531,
ppc_spr_ibat2u = 532,
ppc_spr_ibat2l = 533,
ppc_spr_ibat3u = 534,
ppc_spr_ibat3l = 535,
ppc_spr_dbat0u = 536,
ppc_spr_dbat0l = 537,
ppc_spr_dbat1u = 538,
ppc_spr_dbat1l = 539,
ppc_spr_dbat2u = 540,
ppc_spr_dbat2l = 541,
ppc_spr_dbat3u = 542,
ppc_spr_dbat3l = 543,
ppc_spr_ic_cst = 560,
ppc_spr_ic_adr = 561,
ppc_spr_ic_dat = 562,
ppc_spr_dc_cst = 568,
ppc_spr_dc_adr = 569,
ppc_spr_dc_dat = 570,
ppc_spr_dpdr = 630,
ppc_spr_dpir = 631,
ppc_spr_immr = 638,
ppc_spr_mi_ctr = 784,
ppc_spr_mi_ap = 786,
ppc_spr_mi_epn = 787,
ppc_spr_mi_twc = 789,
ppc_spr_mi_rpn = 790,
ppc_spr_mi_cam = 816,
ppc_spr_mi_ram0 = 817,
ppc_spr_mi_ram1 = 818,
ppc_spr_md_ctr = 792,
ppc_spr_m_casid = 793,
ppc_spr_md_ap = 794,
ppc_spr_md_epn = 795,
ppc_spr_m_twb = 796,
ppc_spr_md_twc = 797,
ppc_spr_md_rpn = 798,
ppc_spr_m_tw = 799,
ppc_spr_mi_dbcam = 816,
ppc_spr_mi_dbram0 = 817,
ppc_spr_mi_dbram1 = 818,
ppc_spr_md_dbcam = 824,
ppc_spr_md_cam = 824,
ppc_spr_md_dbram0 = 825,
ppc_spr_md_ram0 = 825,
ppc_spr_md_dbram1 = 826,
ppc_spr_md_ram1 = 826,
ppc_spr_ummcr0 = 936,
ppc_spr_upmc1 = 937,
ppc_spr_upmc2 = 938,
ppc_spr_usia = 939,
ppc_spr_ummcr1 = 940,
ppc_spr_upmc3 = 941,
ppc_spr_upmc4 = 942,
ppc_spr_zpr = 944,
ppc_spr_pid = 945,
ppc_spr_mmcr0 = 952,
ppc_spr_pmc1 = 953,
ppc_spr_sgr = 953,
ppc_spr_pmc2 = 954,
ppc_spr_dcwr = 954,
ppc_spr_sia = 955,
ppc_spr_mmcr1 = 956,
ppc_spr_pmc3 = 957,
ppc_spr_pmc4 = 958,
ppc_spr_sda = 959,
ppc_spr_tbhu = 972,
ppc_spr_tblu = 973,
ppc_spr_dmiss = 976,
ppc_spr_dcmp = 977,
ppc_spr_hash1 = 978,
ppc_spr_hash2 = 979,
ppc_spr_icdbdr = 979,
ppc_spr_imiss = 980,
ppc_spr_esr = 980,
ppc_spr_icmp = 981,
ppc_spr_dear = 981,
ppc_spr_rpa = 982,
ppc_spr_evpr = 982,
ppc_spr_cdbcr = 983,
ppc_spr_tsr = 984,
ppc_spr_602_tcr = 984,
ppc_spr_403_tcr = 986,
ppc_spr_ibr = 986,
ppc_spr_pit = 987,
ppc_spr_esasrr = 988,
ppc_spr_tbhi = 988,
ppc_spr_tblo = 989,
ppc_spr_srr2 = 990,
ppc_spr_sebr = 990,
ppc_spr_srr3 = 991,
ppc_spr_ser = 991,
ppc_spr_hid0 = 1008,
ppc_spr_dbsr = 1008,
ppc_spr_hid1 = 1009,
ppc_spr_iabr = 1010,
ppc_spr_dbcr = 1010,
ppc_spr_iac1 = 1012,
ppc_spr_dabr = 1013,
ppc_spr_iac2 = 1013,
ppc_spr_dac1 = 1014,
ppc_spr_dac2 = 1015,
ppc_spr_l2cr = 1017,
ppc_spr_dccr = 1018,
ppc_spr_ictc = 1019,
ppc_spr_iccr = 1019,
ppc_spr_thrm1 = 1020,
ppc_spr_pbl1 = 1020,
ppc_spr_thrm2 = 1021,
ppc_spr_pbu1 = 1021,
ppc_spr_thrm3 = 1022,
ppc_spr_pbl2 = 1022,
ppc_spr_fpecr = 1022,
ppc_spr_lt = 1022,
ppc_spr_pir = 1023,
ppc_spr_pbu2 = 1023
};
/* Instruction size. */
#define PPC_INSN_SIZE 4

1189
gdb/rs6000-tdep.c
View File

File diff suppressed because it is too large Load Diff

58
gdb/target-descriptions.c
View File

@ -352,10 +352,12 @@ static struct
{ "int16", &builtin_type_int16 },
{ "int32", &builtin_type_int32 },
{ "int64", &builtin_type_int64 },
{ "int128", &builtin_type_int128 },
{ "uint8", &builtin_type_uint8 },
{ "uint16", &builtin_type_uint16 },
{ "uint32", &builtin_type_uint32 },
{ "uint64", &builtin_type_uint64 },
{ "uint128", &builtin_type_uint128 },
{ "ieee_single", &builtin_type_ieee_single },
{ "ieee_double", &builtin_type_ieee_double },
{ "arm_fpa_ext", &builtin_type_arm_ext }
@ -421,10 +423,9 @@ tdesc_data_cleanup (void *data_untyped)
/* Search FEATURE for a register named NAME. */
int
tdesc_numbered_register (const struct tdesc_feature *feature,
struct tdesc_arch_data *data,
int regno, const char *name)
static struct tdesc_reg *
tdesc_find_register_early (const struct tdesc_feature *feature,
const char *name)
{
int ixr;
struct tdesc_reg *reg;
@ -433,18 +434,32 @@ tdesc_numbered_register (const struct tdesc_feature *feature,
VEC_iterate (tdesc_reg_p, feature->registers, ixr, reg);
ixr++)
if (strcasecmp (reg->name, name) == 0)
{
/* Make sure the vector includes a REGNO'th element. */
while (regno >= VEC_length (tdesc_reg_p, data->registers))
VEC_safe_push (tdesc_reg_p, data->registers, NULL);
VEC_replace (tdesc_reg_p, data->registers, regno, reg);
return 1;
}
return reg;
return 0;
return NULL;
}
/* Search FEATURE for a register whose name is in NAMES. */
/* Search FEATURE for a register named NAME. Assign REGNO to it. */
int
tdesc_numbered_register (const struct tdesc_feature *feature,
struct tdesc_arch_data *data,
int regno, const char *name)
{
struct tdesc_reg *reg = tdesc_find_register_early (feature, name);
if (reg == NULL)
return 0;
/* Make sure the vector includes a REGNO'th element. */
while (regno >= VEC_length (tdesc_reg_p, data->registers))
VEC_safe_push (tdesc_reg_p, data->registers, NULL);
VEC_replace (tdesc_reg_p, data->registers, regno, reg);
return 1;
}
/* Search FEATURE for a register whose name is in NAMES and assign
REGNO to it. */
int
tdesc_numbered_register_choices (const struct tdesc_feature *feature,
@ -460,6 +475,19 @@ tdesc_numbered_register_choices (const struct tdesc_feature *feature,
return 0;
}
/* Search FEATURE for a register named NAME, and return its size in
bits. The register must exist. */
int
tdesc_register_size (const struct tdesc_feature *feature,
const char *name)
{
struct tdesc_reg *reg = tdesc_find_register_early (feature, name);
gdb_assert (reg != NULL);
return reg->bitsize;
}
/* Look up a register by its GDB internal register number. */
static struct tdesc_reg *
@ -682,18 +710,16 @@ set_tdesc_pseudo_register_reggroup_p
void
tdesc_use_registers (struct gdbarch *gdbarch,
const struct target_desc *target_desc,
struct tdesc_arch_data *early_data)
{
int num_regs = gdbarch_num_regs (gdbarch);
int i, ixf, ixr;
const struct target_desc *target_desc;
struct tdesc_feature *feature;
struct tdesc_reg *reg;
struct tdesc_arch_data *data;
htab_t reg_hash;
target_desc = gdbarch_target_desc (gdbarch);
/* We can't use the description for registers if it doesn't describe
any. This function should only be called after validating
registers, so the caller should know that registers are

15
gdb/target-descriptions.h
View File

@ -61,8 +61,12 @@ void set_tdesc_pseudo_register_reggroup_p
(struct gdbarch *gdbarch,
gdbarch_register_reggroup_p_ftype *pseudo_reggroup_p);
/* Update GDBARCH to use the target description for registers. Fixed
register assignments are taken from EARLY_DATA, which is freed.
/* Update GDBARCH to use the TARGET_DESC for registers. TARGET_DESC
may be GDBARCH's target description or (if GDBARCH does not have
one which describes registers) another target description
constructed by the gdbarch initialization routine.
Fixed register assignments are taken from EARLY_DATA, which is freed.
All registers which have not been assigned fixed numbers are given
numbers above the current value of gdbarch_num_regs.
gdbarch_num_regs and various register-related predicates are updated to
@ -71,6 +75,7 @@ void set_tdesc_pseudo_register_reggroup_p
successfully validating the required registers. */
void tdesc_use_registers (struct gdbarch *gdbarch,
const struct target_desc *target_desc,
struct tdesc_arch_data *early_data);
/* Allocate initial data for validation of a target description during
@ -93,6 +98,12 @@ int tdesc_numbered_register (const struct tdesc_feature *feature,
struct tdesc_arch_data *data,
int regno, const char *name);
/* Search FEATURE for a register named NAME, and return its size in
bits. The register must exist. */
int tdesc_register_size (const struct tdesc_feature *feature,
const char *name);
/* Search FEATURE for a register with any of the names from NAMES
(NULL-terminated). Record REGNO and the register in DATA; when
tdesc_use_registers is called, REGNO will be assigned to the

6
gdb/testsuite/ChangeLog
View File

@ -1,4 +1,8 @@
2007/10/15 Pierre Muller <muller@ics.u-strasbg.fr>
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* gdb.xml/tdesc-regs.exp: Add PowerPC support.
2007-10-15 Pierre Muller <muller@ics.u-strasbg.fr>
* gdb.base/sigstep.c (main): Add checks for
return values for setitimer call.

7
gdb/testsuite/gdb.xml/tdesc-regs.exp
View File

@ -24,6 +24,7 @@ gdb_start
# architecture, or the description will be rejected.
set core-regs ""
set regdir ""
switch -glob -- [istarget] {
"*arm-*-*" {
set core-regs {arm-core.xml}
@ -34,6 +35,10 @@ switch -glob -- [istarget] {
"mips*-*-*" {
set core-regs {mips-cpu.xml mips-cp0.xml mips-fpu.xml}
}
"powerpc*-*-*" {
set regdir "rs6000/"
set core-regs {power-core.xml}
}
}
# If no core registers were specified, assume this target does not
@ -60,7 +65,7 @@ gdb_test "set tdesc file $srcdir/$subdir/single-reg.xml" \
# will be found by <xi:include>.
foreach src ${core-regs} {
file delete "$src"
file copy "$srcdir/../features/$src" "$src"
file copy "$srcdir/../features/$regdir$src" "$src"
}
# Similarly, we need to copy files under test into the objdir.

4
include/gdb/ChangeLog
View File

@ -1,3 +1,7 @@
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* sim-ppc.h (sim_spr_register_name): New prototype.
2007-10-11 Jesper Nilsson <jesper.nilsson@axis.com>
* callback.h (cb_is_stdin, cb_is_stdout, cb_is_stderr): Add prototypes.

4
include/gdb/sim-ppc.h
View File

@ -762,6 +762,10 @@ enum
};
/* Return the register name for the supplied SPR number if any, or
NULL if none. */
extern const char *sim_spr_register_name (int);
#ifdef __cplusplus
}
#endif

5
sim/ppc/ChangeLog
View File

@ -1,3 +1,8 @@
2007-10-15 Daniel Jacobowitz <dan@codesourcery.com>
* gdb-sim.c (regnum2spr): Rename to...
(sim_spr_register_name): ... this. Make global.
2007-09-04 Jerome Guitton <guitton@adacore.com>
* sim/ppc/emul_bugapi.c (emul_bugapi_create): quote the file

14
sim/ppc/gdb-sim.c
View File

@ -28,11 +28,10 @@
#include "gdb/remote-sim.h"
#include "gdb/sim-ppc.h"
/* Return the name of the register whose number is REGNUM, or zero if
REGNUM is an invalid register number. */
static const char *
regnum2spr (int spr)
/* Return the register name for the supplied SPR if any, or NULL if
none. */
const char *
sim_spr_register_name (int spr)
{
if (spr_is_valid (spr))
return spr_name (spr);
@ -40,6 +39,11 @@ regnum2spr (int spr)
return NULL;
}
#define regnum2spr(SPR) sim_spr_register_name (SPR)
/* Return the name of the register whose number is REGNUM, or zero if
REGNUM is an invalid register number. */
static const char *
regnum2name (int regnum)
{