* ppc-opc.c (PPC440): Define.
(powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci, icread instructions when PPC440. Add dlmzb instruction.
This commit is contained in:
Alan Modra
parent
68d23d2157
commit
7d5b217e2c
@ -1,3 +1,9 @@
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2003-08-19 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (PPC440): Define.
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(powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci,
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icread instructions when PPC440. Add dlmzb instruction.
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2003-08-14 Alan Modra <amodra@bigpond.net.au>
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* dep-in.sed: Remove libintl.h.
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@ -1771,6 +1771,7 @@ extract_tbr (unsigned long insn,
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#define PPCONLY PPC_OPCODE_PPC
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#define PPC403 PPC_OPCODE_403
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#define PPC405 PPC403
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#define PPC440 PPC_OPCODE_440
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#define PPC750 PPC
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#define PPC860 PPC
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
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@ -1863,90 +1864,90 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
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{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
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{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
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{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
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{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
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@ -3314,6 +3315,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
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||||
{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
|
||||
|
||||
{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
|
||||
{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
|
||||
|
||||
{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
|
||||
|
||||
{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
|
||||
@ -3783,7 +3787,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
|
||||
{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
|
||||
|
||||
{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
|
||||
{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
|
||||
|
||||
{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
|
||||
{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
|
||||
@ -4065,7 +4069,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
|
||||
{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
|
||||
|
||||
{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
|
||||
{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
|
||||
|
||||
{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
|
||||
|
||||
@ -4288,7 +4292,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
|
||||
{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
|
||||
|
||||
{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
|
||||
{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
|
||||
|
||||
{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
|
||||
|
||||
@ -4305,7 +4309,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
|
||||
{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
|
||||
|
||||
{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
|
||||
{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
|
||||
|
||||
{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
|
||||
{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user