Add support for the MIPS eXtended Physical Address (XPA) ASE.
ChangeLog: binutils/ * doc/binutils.texi: Document the disassemble MIPS XPA instructions command line option. gas/ * config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA. (md_longopts): Add xpa and no-xpa command line options. (mips_ases): Add MIPS XPA ASE. (mips_cpu_info_table): Update p5600 entry to allow the XPA ASE. * doc/as.texinfo: Document the MIPS XPA command line options. * doc/c-mips.texi: Document the MIPS XPA command line options, and assembler directives. gas/testsuite/ * gas/mips/mips.exp: Add xpa tests. * gas/mips/xpa.s: New test. * gas/mips/xpa.d: Likewise. include/ * opcode/mips.h (ASE_XPA): New define. opcodes/ * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2 to allow the MIPS XPA ASE. (parse_mips_dis_option): Process the -Mxpa option. * mips-opc.c (XPA): New define. (mips_builtin_opcodes): Add MIPS XPA instructions and move the locations of the ctc0 and cfc0 instructions.
This commit is contained in:
Andrew Bennett
parent
cd0449ab05
commit
7d64c587c1
@ -1,3 +1,8 @@
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2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
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* doc/binutils.texi: Document the disassemble MIPS XPA instructions
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command line option.
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2014-04-22 Christian Svensson <blue@cmd.nu>
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* readelf.c: Remove openrisc and or32 support. Add support for or1k.
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@ -2132,6 +2132,9 @@ Disassemble MSA instructions.
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@item virt
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Disassemble the virtualization ASE instructions.
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@item xpa
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Disassemble the eXtended Physical Address (XPA) ASE instructions.
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@item gpr-names=@var{ABI}
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Print GPR (general-purpose register) names as appropriate
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for the specified ABI. By default, GPR names are selected according to
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@ -1,3 +1,13 @@
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2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
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* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
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(md_longopts): Add xpa and no-xpa command line options.
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(mips_ases): Add MIPS XPA ASE.
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(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
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* doc/as.texinfo: Document the MIPS XPA command line options.
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* doc/c-mips.texi: Document the MIPS XPA command line options,
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and assembler directives.
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2014-04-22 Sandra Loosemore <sandra@codesourcery.com>
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* config/tc-nios2.c (nios2_consume_arg): Add case for 'E' to
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@ -1338,6 +1338,8 @@ enum options
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OPTION_NO_DSPR2,
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OPTION_EVA,
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OPTION_NO_EVA,
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OPTION_XPA,
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OPTION_NO_XPA,
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OPTION_MICROMIPS,
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OPTION_NO_MICROMIPS,
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OPTION_MCU,
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@ -1447,6 +1449,8 @@ struct option md_longopts[] =
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{"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
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{"mmsa", no_argument, NULL, OPTION_MSA},
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{"mno-msa", no_argument, NULL, OPTION_NO_MSA},
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{"mxpa", no_argument, NULL, OPTION_XPA},
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{"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
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/* Old-style architecture options. Don't add more of these. */
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{"m4650", no_argument, NULL, OPTION_M4650},
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@ -1599,7 +1603,11 @@ static const struct mips_ase mips_ases[] = {
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{ "msa", ASE_MSA, ASE_MSA64,
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OPTION_MSA, OPTION_NO_MSA,
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2, 2, 2, 2 }
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2, 2, 2, 2 },
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{ "xpa", ASE_XPA, 0,
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OPTION_XPA, OPTION_NO_XPA,
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2, 2, -1, -1 }
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};
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/* The set of ASEs that require -mfp64. */
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@ -17903,7 +17911,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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{ "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
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/* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
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{ "p5600", 0, ASE_VIRT | ASE_EVA, ISA_MIPS32R2, CPU_MIPS32R2 },
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{ "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R2, CPU_MIPS32R2 },
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/* MIPS 64 */
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{ "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
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@ -18161,6 +18169,9 @@ MIPS options:\n\
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-mmsa generate MSA instructions\n\
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-mno-msa do not generate MSA instructions\n"));
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fprintf (stream, _("\
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-mxpa generate eXtended Physical Address (XPA) instructions\n\
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-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
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fprintf (stream, _("\
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-mvirt generate Virtualization instructions\n\
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-mno-virt do not generate Virtualization instructions\n"));
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fprintf (stream, _("\
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@ -413,6 +413,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mdsp}] [@b{-mno-dsp}]
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[@b{-mdspr2}] [@b{-mno-dspr2}]
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[@b{-mmsa}] [@b{-mno-msa}]
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[@b{-mxpa}] [@b{-mno-xpa}]
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[@b{-mmt}] [@b{-mno-mt}]
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[@b{-mmcu}] [@b{-mno-mcu}]
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[@b{-minsn32}] [@b{-mno-insn32}]
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@ -1357,6 +1358,12 @@ Generate code for the MIPS SIMD Architecture Extension.
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This tells the assembler to accept MSA instructions.
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@samp{-mno-msa} turns off this option.
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@item -mxpa
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@itemx -mno-xpa
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Generate code for the MIPS eXtended Physical Address (XPA) Extension.
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This tells the assembler to accept XPA instructions.
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@samp{-mno-xpa} turns off this option.
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@item -mmt
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@itemx -mno-mt
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Generate code for the MT Application Specific Extension.
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@ -183,6 +183,12 @@ Generate code for the MIPS SIMD Architecture Extension.
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This tells the assembler to accept MSA instructions.
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@samp{-mno-msa} turns off this option.
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@item -mxpa
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@itemx -mno-xpa
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Generate code for the MIPS eXtended Physical Address (XPA) Extension.
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This tells the assembler to accept XPA instructions.
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@samp{-mno-xpa} turns off this option.
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@item -mvirt
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@itemx -mno-virt
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Generate code for the Virtualization Application Specific Extension.
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@ -879,6 +885,13 @@ from the Virtualization Application Specific Extension from that point
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on in the assembly. The @code{.set novirt} directive prevents Virtualization
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instructions from being accepted.
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@cindex MIPS eXtended Physical Address (XPA) instruction generation override
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@kindex @code{.set xpa}
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@kindex @code{.set noxpa}
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The directive @code{.set xpa} makes the assembler accept instructions
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from the XPA Extension from that point on in the assembly. The
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@code{.set noxpa} directive prevents XPA instructions from being accepted.
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Traditional MIPS assemblers do not support these directives.
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@node MIPS Floating-Point
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@ -1,3 +1,9 @@
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2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
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* gas/mips/mips.exp: Add xpa tests.
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* gas/mips/xpa.s: New test.
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* gas/mips/xpa.d: Likewise.
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2014-04-22 Sandra Loosemore <sandra@codesourcery.com>
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* gas/nios2/selftest.s: New.
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@ -1170,6 +1170,8 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2]
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run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
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run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
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run_dump_test "pcrel-1"
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run_dump_test "pcrel-2"
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run_list_test "pcrel-3" "" "Invalid cross-section PC-relative references"
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24
gas/testsuite/gas/mips/xpa.d
Normal file
24
gas/testsuite/gas/mips/xpa.d
Normal file
@ -0,0 +1,24 @@
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#objdump: -dr --prefix-addresses --show-raw-insn -Mxpa,cp0-names=mips32r2
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#name: XPA instructions
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#as: -32 -mxpa
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 40420800 mfhc0 v0,c0_random
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[0-9a-f]+ <[^>]*> 40428000 mfhc0 v0,c0_config
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[0-9a-f]+ <[^>]*> 40420002 mfhc0 v0,c0_mvpconf0
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[0-9a-f]+ <[^>]*> 40420007 mfhc0 v0,\$0,7
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[0-9a-f]+ <[^>]*> 40c20800 mthc0 v0,c0_random
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[0-9a-f]+ <[^>]*> 40c28000 mthc0 v0,c0_config
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[0-9a-f]+ <[^>]*> 40c20002 mthc0 v0,c0_mvpconf0
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[0-9a-f]+ <[^>]*> 40c20007 mthc0 v0,\$0,7
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[0-9a-f]+ <[^>]*> 40620c00 mfhgc0 v0,c0_random
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[0-9a-f]+ <[^>]*> 40628400 mfhgc0 v0,c0_config
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[0-9a-f]+ <[^>]*> 40620402 mfhgc0 v0,c0_mvpconf0
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[0-9a-f]+ <[^>]*> 40620407 mfhgc0 v0,\$0,7
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[0-9a-f]+ <[^>]*> 40620e00 mthgc0 v0,c0_random
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[0-9a-f]+ <[^>]*> 40628600 mthgc0 v0,c0_config
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[0-9a-f]+ <[^>]*> 40620602 mthgc0 v0,c0_mvpconf0
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[0-9a-f]+ <[^>]*> 40620607 mthgc0 v0,\$0,7
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...
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29
gas/testsuite/gas/mips/xpa.s
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29
gas/testsuite/gas/mips/xpa.s
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@ -0,0 +1,29 @@
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.text
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.set noat
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.set noreorder
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.set nomacro
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test_xpa:
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mfhc0 $2, $1
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mfhc0 $2, $16
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mfhc0 $2, $0, 2
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mfhc0 $2, $0, 7
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mthc0 $2, $1
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mthc0 $2, $16
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mthc0 $2, $0, 2
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mthc0 $2, $0, 7
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mfhgc0 $2, $1
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mfhgc0 $2, $16
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mfhgc0 $2, $0, 2
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mfhgc0 $2, $0, 7
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mthgc0 $2, $1
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mthgc0 $2, $16
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mthgc0 $2, $0, 2
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mthgc0 $2, $0, 7
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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.space 8
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@ -1,3 +1,7 @@
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2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
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* opcode/mips.h (ASE_XPA): New define.
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2014-04-22 Christian Svensson <blue@cmd.nu>
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* dis-asm.h: Remove openrisc and or32 support. Add support for or1k.
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@ -1155,6 +1155,8 @@ static const unsigned int mips_isa_table[] =
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/* MSA Extension */
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#define ASE_MSA 0x00000800
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#define ASE_MSA64 0x00001000
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/* eXtended Physical Address (XPA) Extension. */
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#define ASE_XPA 0x00002000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -1,3 +1,12 @@
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2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
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to allow the MIPS XPA ASE.
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(parse_mips_dis_option): Process the -Mxpa option.
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* mips-opc.c (XPA): New define.
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(mips_builtin_opcodes): Add MIPS XPA instructions and move the
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locations of the ctc0 and cfc0 instructions.
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2014-04-22 Christian Svensson <blue@cmd.nu>
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* Makefile.am: Remove openrisc and or32 support. Add support for or1k.
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@ -551,7 +551,7 @@ const struct mips_arch_choice mips_arch_choices[] =
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{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
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ISA_MIPS32R2,
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(ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
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| ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
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| ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
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mips_cp0_names_mips3264r2,
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mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
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mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
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@ -566,7 +566,7 @@ const struct mips_arch_choice mips_arch_choices[] =
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{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
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ISA_MIPS64R2,
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(ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
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| ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
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| ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
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mips_cp0_names_mips3264r2,
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mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
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mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
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@ -810,6 +810,13 @@ parse_mips_dis_option (const char *option, unsigned int len)
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mips_ase |= ASE_VIRT64;
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return;
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}
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if (CONST_STRNEQ (option, "xpa"))
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{
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mips_ase |= ASE_XPA;
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return;
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}
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/* Look for the = that delimits the end of the option name. */
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for (i = 0; i < len; i++)
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@ -2195,6 +2202,9 @@ with the -M switch (multiple options should be separated by commas):\n"));
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fprintf (stream, _("\n\
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virt Recognize the virtualization ASE instructions.\n"));
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fprintf (stream, _("\n\
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xpa Recognize the eXtended Physical Address (XPA) ASE instructions.\n"));
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fprintf (stream, _("\n\
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gpr-names=ABI Print GPR names according to specified ABI.\n\
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Default: based on binary being disassembled.\n"));
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@ -359,6 +359,9 @@ decode_mips_operand (const char *p)
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#define MSA ASE_MSA
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#define MSA64 ASE_MSA64
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/* eXtended Physical Address (XPA) support. */
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#define XPA ASE_XPA
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/* The order of overloaded instructions matters. Label arguments and
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register arguments look the same. Instructions that can have either
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for arguments must apear in the correct order in this table for the
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@ -895,7 +898,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
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{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF },
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{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE },
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{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
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/* cfc0 is at the bottom of the table. */
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{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 },
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{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 },
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/* cfc2 is at the bottom of the table. */
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@ -908,7 +911,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
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{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 },
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{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 },
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{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
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/* ctc0 is at the bottom of the table. */
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{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 },
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{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 },
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/* ctc2 is at the bottom of the table. */
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@ -1300,6 +1303,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I32, 0, 0 },
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{"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT, 0 },
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{"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT, 0 },
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{"mfhc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I33, XPA, 0 },
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{"mfhc0", "t,G,H", 0x40400000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I33, XPA, 0 },
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{"mfhgc0", "t,G", 0x40600400, 0xffe007ff, WR_1|RD_C0|LCD, 0, I33, IVIRT|XPA, 0 },
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{"mfhgc0", "t,G,H", 0x40600400, 0xffe007f8, WR_1|RD_C0|LCD, 0, I33, IVIRT|XPA, 0 },
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{"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S, 0, I1, 0, 0 },
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||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S, 0, I1, 0, 0 },
|
||||
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 },
|
||||
@ -1393,6 +1400,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I32, 0, 0 },
|
||||
{"mtgc0", "t,G", 0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT, 0 },
|
||||
{"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT, 0 },
|
||||
{"mthc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I33, XPA, 0 },
|
||||
{"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I33, XPA, 0 },
|
||||
{"mthgc0", "t,G", 0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I33, IVIRT|XPA, 0 },
|
||||
{"mthgc0", "t,G,H", 0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I33, IVIRT|XPA, 0 },
|
||||
{"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S, 0, I1, 0, 0 },
|
||||
{"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S, 0, I1, 0, 0 },
|
||||
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 },
|
||||
@ -1954,6 +1965,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
|
||||
{"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 },
|
||||
|
||||
/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
|
||||
mfhc0 and mthc0 XPA instructions, so they have been placed here
|
||||
to allow the XPA instructions to take precedence. */
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
|
||||
|
||||
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
|
||||
instructions so they are here for the latters to take precedence. */
|
||||
{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user