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x86: also correctly support TEST opcode aliases

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Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.
This commit is contained in:
Jan Beulich 2017-02-24 10:04:26 +01:00 committed by Jan Beulich
parent 1b3cee563c
commit 7db2c58848
9 changed files with 38 additions and 2 deletions
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9
gas/ChangeLog
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@ -1,3 +1,12 @@
2017-02-24 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/opcode.s: Add alternative TEST forms.
* testsuite/gas/i386/x86-64-opcode.s: Likewise.
* testsuite/gas/i386/opcode.d: Adjust accordingly.
* testsuite/gas/i386/opcode-intel.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-opcode.d: Likewise.
2017-02-24 Sheldon Lobo <sheldon.lobo@oracle.com>
Test cases for the architecture level aware SPARC ASI work.

4
gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
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@ -302,4 +302,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 07 sysret
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
[ ]*[a-f0-9]+: 48 f7 c9 08 00 00 00 test \$(0x)?0*8,%rcx
#pass

3
gas/testsuite/gas/i386/opcode-intel.d
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@ -601,4 +601,7 @@ Disassembly of section .text:
+[a-f0-9]+: 82 f3 01 xor bl,0x1
+[a-f0-9]+: 82 fb 01 cmp bl,0x1
+[a-f0-9]+: 62 f3 7d 08 15 e8 ab vpextrw eax,xmm5,0xab
+[a-f0-9]+: f6 c9 01 test cl,(0x)?0*1
+[a-f0-9]+: 66 f7 c9 02 00 test cx,(0x)?0*2
+[a-f0-9]+: f7 c9 04 00 00 00 test ecx,(0x)?0*4
#pass

3
gas/testsuite/gas/i386/opcode.d
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@ -600,4 +600,7 @@ Disassembly of section .text:
+[a-f0-9]+: 82 f3 01 xor \$0x1,%bl
+[a-f0-9]+: 82 fb 01 cmp \$0x1,%bl
+[a-f0-9]+: 62 f3 7d 08 15 e8 ab vpextrw \$0xab,%xmm5,%eax
+[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
+[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
+[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
#pass

4
gas/testsuite/gas/i386/opcode.s
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@ -600,3 +600,7 @@ foo:
.byte 0x82, 0xfb, 0x01
.byte 0x62, 0xf3, 0x7d, 0x08, 0x15, 0xe8, 0xab
.byte 0xf6, 0xc9, 0x01
.byte 0x66, 0xf7, 0xc9, 0x02, 0x00
.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00

4
gas/testsuite/gas/i386/x86-64-opcode.d
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@ -301,4 +301,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 07 sysret
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
[ ]*[a-f0-9]+: 48 f7 c9 08 00 00 00 test \$(0x)?0*8,%rcx
#pass

5
gas/testsuite/gas/i386/x86-64-opcode.s
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@ -427,3 +427,8 @@
swapgs # -- -- -- -- 0F 01 f8
pushw $0x2222
.byte 0xf6, 0xc9, 0x01
.byte 0x66, 0xf7, 0xc9, 0x02, 0x00
.byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00
.byte 0x48, 0xf7, 0xc9, 0x08, 0x00, 0x00, 0x00

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2017-02-24 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
Add support for associating SPARC ASIs with an architecture level.

4
opcodes/i386-dis.c
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@ -3511,7 +3511,7 @@ static const struct dis386 reg_table[][8] = {
/* REG_F6 */
{
{ "testA", { Eb, Ib }, 0 },
{ Bad_Opcode },
{ "testA", { Eb, Ib }, 0 },
{ "notA", { Ebh1 }, 0 },
{ "negA", { Ebh1 }, 0 },
{ "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
@ -3522,7 +3522,7 @@ static const struct dis386 reg_table[][8] = {
/* REG_F7 */
{
{ "testQ", { Ev, Iv }, 0 },
{ Bad_Opcode },
{ "testQ", { Ev, Iv }, 0 },
{ "notQ", { Evh1 }, 0 },
{ "negQ", { Evh1 }, 0 },
{ "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */