x86: fix SSE4a dependencies of ".arch .nosse*"
Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
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@ -1,3 +1,8 @@
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2020-02-13 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (cpu_noarch): Use CPU_ANY_SSE4_FLAGS in
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"nosse4" entry.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (avx512): New (at file scope), moved from
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@ -1180,7 +1180,7 @@ static const noarch_entry cpu_noarch[] =
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{ STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
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{ STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
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{ STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
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{ STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
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{ STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_FLAGS },
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{ STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
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{ STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
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{ STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
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@ -1,3 +1,10 @@
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2020-02-13 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (cpu_flag_init): Move CpuSSE4a from
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CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
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CPU_ANY_SSE4_FLAGS entry.
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* i386-init.h: Re-generate.
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2020-02-12 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
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@ -322,17 +322,19 @@ static initializer cpu_flag_init[] =
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{ "CPU_ANY_MMX_FLAGS",
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"CPU_3DNOWA_FLAGS" },
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{ "CPU_ANY_SSE_FLAGS",
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"CPU_ANY_SSE2_FLAGS|CpuSSE|CpuSSE4a" },
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"CPU_ANY_SSE2_FLAGS|CpuSSE" },
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{ "CPU_ANY_SSE2_FLAGS",
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"CPU_ANY_SSE3_FLAGS|CpuSSE2" },
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{ "CPU_ANY_SSE3_FLAGS",
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"CPU_ANY_SSSE3_FLAGS|CpuSSE3" },
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"CPU_ANY_SSSE3_FLAGS|CpuSSE3|CpuSSE4a" },
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{ "CPU_ANY_SSSE3_FLAGS",
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"CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" },
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{ "CPU_ANY_SSE4_1_FLAGS",
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"CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" },
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{ "CPU_ANY_SSE4_2_FLAGS",
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"CpuSSE4_2" },
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{ "CPU_ANY_SSE4_FLAGS",
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"CPU_ANY_SSE4_1_FLAGS|CpuSSE4a" },
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{ "CPU_ANY_AVX_FLAGS",
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"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
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{ "CPU_ANY_AVX2_FLAGS",
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@ -1132,7 +1132,7 @@
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#define CPU_ANY_SSE2_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
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0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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@ -1140,7 +1140,7 @@
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#define CPU_ANY_SSE3_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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@ -1170,6 +1170,14 @@
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ANY_SSE4_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ANY_AVX_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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