PowerPC register expression checks
This stops powerpc gas blithely accepting such nonsense as "addi %f4,%cr3,%r31". PR 21118 gas/ * NEWS: Mention powerpc register checks. * config/tc-ppc.c (struct pd_reg): Make value a short. Add flags. (pre_defined_registers): Delete fpscr and pmr entries. Set register type in flags. (cr_names): Set type in flags. (reg_name_search): Return pointer to struct pd_reg rather than value. (register_name): Adjust to suit. Set X_md from flags. (ppc_parse_name): Likewise. (ppc_optimize_expr): New function. (md_assemble): Verify expresion reg flags match operand. * config/tc-ppc.h (md_optimize_expr): Define. (ppc_optimize_expr): Declare. include/ * opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first. (PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define. opcodes/ * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
This commit is contained in:
Alan Modra
parent
606a935e3a
commit
7e0de605cb
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@ -1,3 +1,19 @@
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2017-02-14 Alan Modra <amodra@gmail.com>
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PR 21118
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* NEWS: Mention powerpc register checks.
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* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
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(pre_defined_registers): Delete fpscr and pmr entries. Set
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register type in flags.
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(cr_names): Set type in flags.
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(reg_name_search): Return pointer to struct pd_reg rather than value.
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(register_name): Adjust to suit. Set X_md from flags.
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(ppc_parse_name): Likewise.
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(ppc_optimize_expr): New function.
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(md_assemble): Verify expresion reg flags match operand.
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* config/tc-ppc.h (md_optimize_expr): Define.
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(ppc_optimize_expr): Declare.
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2017-02-14 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/cell.s: Correct invalid registers.
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4
gas/NEWS
4
gas/NEWS
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@ -1,5 +1,9 @@
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-*- text -*-
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* PowerPC gas now checks that the correct register class is used in
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instructions. For instance, "addi %f4,%cr3,%r31" is now rejected
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rather than silently producing "addi r4,r3,31".
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* Add support for the Texas Instruments PRU processor.
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Changes in 2.28:
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File diff suppressed because it is too large
Load Diff
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@ -264,6 +264,9 @@ extern long md_pcrel_from_section (struct fix *, segT);
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#define md_parse_name(name, exp, mode, c) ppc_parse_name (name, exp)
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extern int ppc_parse_name (const char *, struct expressionS *);
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#define md_optimize_expr(left, op, right) ppc_optimize_expr (left, op, right)
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extern int ppc_optimize_expr (expressionS *, operatorT, expressionS *);
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#define md_operand(x)
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#define md_cleanup() ppc_cleanup ()
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@ -1,3 +1,9 @@
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2017-02-14 Alan Modra <amodra@gmail.com>
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PR 21118
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* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
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(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
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2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
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* opcode/hppa.h: Clarify that file is part of GNU opcodes.
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@ -301,86 +301,70 @@ extern const unsigned int num_powerpc_operands;
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goes in the insn. */
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#define PPC_OPSHIFT_INV (-1U << 31)
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/* Values defined for the flags field of a struct powerpc_operand. */
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/* Values defined for the flags field of a struct powerpc_operand.
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Keep the register bits low: They need to fit in an unsigned short. */
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/* This operand names a register. The disassembler uses this to print
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register names with a leading 'r'. */
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#define PPC_OPERAND_GPR (0x1)
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/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
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#define PPC_OPERAND_GPR_0 (0x2)
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/* This operand names a floating point register. The disassembler
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prints these with a leading 'f'. */
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#define PPC_OPERAND_FPR (0x4)
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/* This operand names a vector unit register. The disassembler
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prints these with a leading 'v'. */
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#define PPC_OPERAND_VR (0x8)
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/* This operand names a vector-scalar unit register. The disassembler
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prints these with a leading 'vs'. */
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#define PPC_OPERAND_VSR (0x10)
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/* This operand may use the symbolic names for the CR fields (even
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without -mregnames), which are
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lt 0 gt 1 eq 2 so 3 un 3
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cr0 0 cr1 1 cr2 2 cr3 3
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cr4 4 cr5 5 cr6 6 cr7 7
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These may be combined arithmetically, as in cr2*4+gt. These are
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only supported on the PowerPC, not the POWER. */
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#define PPC_OPERAND_CR_BIT (0x20)
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/* This is a CR FIELD that does not use symbolic names (unless
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-mregnames is in effect). */
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#define PPC_OPERAND_CR_REG (0x40)
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/* This operand names a special purpose register. */
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#define PPC_OPERAND_SPR (0x80)
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/* This operand names a paired-single graphics quantization register. */
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#define PPC_OPERAND_GQR (0x100)
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_RELATIVE (0x200)
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_ABSOLUTE (0x400)
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/* This operand takes signed values. */
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#define PPC_OPERAND_SIGNED (0x1)
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#define PPC_OPERAND_SIGNED (0x800)
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/* This operand takes signed values, but also accepts a full positive
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range of values when running in 32 bit mode. That is, if bits is
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16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
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this flag is ignored. */
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#define PPC_OPERAND_SIGNOPT (0x2)
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/* This operand does not actually exist in the assembler input. This
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is used to support extended mnemonics such as mr, for which two
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operands fields are identical. The assembler should call the
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insert function with any op value. The disassembler should call
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the extract function, ignore the return value, and check the value
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placed in the valid argument. */
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#define PPC_OPERAND_FAKE (0x4)
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#define PPC_OPERAND_SIGNOPT (0x1000)
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/* The next operand should be wrapped in parentheses rather than
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separated from this one by a comma. This is used for the load and
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store instructions which want their operands to look like
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reg,displacement(reg)
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*/
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#define PPC_OPERAND_PARENS (0x8)
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/* This operand may use the symbolic names for the CR fields, which
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are
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lt 0 gt 1 eq 2 so 3 un 3
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cr0 0 cr1 1 cr2 2 cr3 3
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cr4 4 cr5 5 cr6 6 cr7 7
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These may be combined arithmetically, as in cr2*4+gt. These are
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only supported on the PowerPC, not the POWER. */
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#define PPC_OPERAND_CR_BIT (0x10)
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/* This operand names a register. The disassembler uses this to print
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register names with a leading 'r'. */
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#define PPC_OPERAND_GPR (0x20)
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/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
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#define PPC_OPERAND_GPR_0 (0x40)
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/* This operand names a floating point register. The disassembler
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prints these with a leading 'f'. */
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#define PPC_OPERAND_FPR (0x80)
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_RELATIVE (0x100)
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_ABSOLUTE (0x200)
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/* This operand is optional, and is zero if omitted. This is used for
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example, in the optional BF field in the comparison instructions. The
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assembler must count the number of operands remaining on the line,
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and the number of operands remaining for the opcode, and decide
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whether this operand is present or not. The disassembler should
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print this operand out only if it is not zero. */
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#define PPC_OPERAND_OPTIONAL (0x400)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then for the next operand use this operand value plus
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1, ignoring the next operand field for the opcode. This wretched
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hack is needed because the Power rotate instructions can take
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either 4 or 5 operands. The disassembler should print this operand
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out regardless of the PPC_OPERAND_OPTIONAL field. */
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#define PPC_OPERAND_NEXT (0x800)
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define PPC_OPERAND_NEGATIVE (0x1000)
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/* This operand names a vector unit register. The disassembler
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prints these with a leading 'v'. */
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#define PPC_OPERAND_VR (0x2000)
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#define PPC_OPERAND_PARENS (0x2000)
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/* This operand is for the DS field in a DS form instruction. */
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#define PPC_OPERAND_DS (0x4000)
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@ -388,29 +372,53 @@ extern const unsigned int num_powerpc_operands;
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/* This operand is for the DQ field in a DQ form instruction. */
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#define PPC_OPERAND_DQ (0x8000)
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define PPC_OPERAND_NEGATIVE (0x10000)
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/* Valid range of operand is 0..n rather than 0..n-1. */
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#define PPC_OPERAND_PLUS1 (0x10000)
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#define PPC_OPERAND_PLUS1 (0x20000)
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/* Xilinx APU and FSL related operands */
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#define PPC_OPERAND_FSL (0x20000)
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#define PPC_OPERAND_FCR (0x40000)
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#define PPC_OPERAND_UDI (0x80000)
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/* This operand does not actually exist in the assembler input. This
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is used to support extended mnemonics such as mr, for which two
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operands fields are identical. The assembler should call the
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insert function with any op value. The disassembler should call
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the extract function, ignore the return value, and check the value
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placed in the valid argument. */
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#define PPC_OPERAND_FAKE (0x40000)
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/* This operand names a vector-scalar unit register. The disassembler
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prints these with a leading 'vs'. */
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#define PPC_OPERAND_VSR (0x100000)
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/* This operand is optional, and is zero if omitted. This is used for
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example, in the optional BF field in the comparison instructions. The
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assembler must count the number of operands remaining on the line,
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and the number of operands remaining for the opcode, and decide
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whether this operand is present or not. The disassembler should
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print this operand out only if it is not zero. */
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#define PPC_OPERAND_OPTIONAL (0x80000)
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/* This is a CR FIELD that does not use symbolic names. */
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#define PPC_OPERAND_CR_REG (0x200000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then for the next operand use this operand value plus
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1, ignoring the next operand field for the opcode. This wretched
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hack is needed because the Power rotate instructions can take
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either 4 or 5 operands. The disassembler should print this operand
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out regardless of the PPC_OPERAND_OPTIONAL field. */
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#define PPC_OPERAND_NEXT (0x100000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then the value it should use for the operand is stored
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in the SHIFT field of the immediatly following operand field. */
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#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
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#define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
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only optional when generating 32-bit code. */
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#define PPC_OPERAND_OPTIONAL32 (0x800000)
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#define PPC_OPERAND_OPTIONAL32 (0x400000)
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/* Xilinx APU and FSL related operands */
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#define PPC_OPERAND_FSL (0x800000)
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#define PPC_OPERAND_FCR (0x1000000)
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#define PPC_OPERAND_UDI (0x2000000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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with the operands table for simplicity. The macro table is an
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@ -1,3 +1,9 @@
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2017-02-14 Alan Modra <amodra@gmail.com>
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PR 21118
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* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
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with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
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2017-02-11 Stafford Horne <shorne@gmail.com>
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Alan Modra <amodra@gmail.com>
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@ -667,7 +667,7 @@ const struct powerpc_operand powerpc_operands[] =
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#define PMR SPR
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#define TMR SPR
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#define SPR_MASK (0x3ff << 11)
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{ 0x3ff, 11, insert_spr, extract_spr, 0 },
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{ 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR },
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/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
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#define SPRBAT SPR + 1
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@ -676,7 +676,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The SPRG register number in an XFX form m[ft]sprg instruction. */
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#define SPRG SPRBAT + 1
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{ 0x1f, 16, insert_sprg, extract_sprg, 0 },
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{ 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR },
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/* The SR field in an X form instruction. */
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#define SR SPRG + 1
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field, but it is optional. */
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#define TBR SV + 1
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{ 0x3ff, 11, insert_tbr, extract_tbr,
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PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
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PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
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/* If the TBR operand is ommitted, use the value 268. */
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{ -1, 268, NULL, NULL, 0},
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@ -806,11 +806,11 @@ const struct powerpc_operand powerpc_operands[] =
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/* IDX bits for quantization in the pair singles instructions. */
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#define PSQ PSWM + 1
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{ 0x7, 12, 0, 0, 0 },
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{ 0x7, 12, 0, 0, PPC_OPERAND_GQR },
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/* IDX bits for quantization in the pair singles x-type instructions. */
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#define PSQM PSQ + 1
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{ 0x7, 7, 0, 0, 0 },
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{ 0x7, 7, 0, 0, PPC_OPERAND_GQR },
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/* Smaller D field for quantization in the pair singles instructions. */
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#define PSD PSQM + 1
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