AArch64: Wire through instr_sequence
This patch introduces aarch64_instr_sequence which is a structure similar to IT blocks on Arm in order to track instructions that introduce a constraint or dependency on instruction 1..N positions away from the instruction that opened the block. The struct is also wired through to the locations that require it. gas/ * config/tc-aarch64.c (now_instr_sequence): (*insn_sequence, now_instr_sequence): New. (output_operand_error_record, do_encode): Add insn_sequence. (md_assemble): Update insn_sequence. (try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn): Pass insn_sequence. * config/tc-aarch64.h (struct aarch64_segment_info_type): Add insn_sequence. include/ * opcode/aarch64.h (struct aarch64_instr_sequence): New. (aarch64_opcode_encode): Use it. opcodes/ * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence. * aarch64-dis.c (insn_sequence): New.
This commit is contained in:
Tamar Christina
parent
eae424aef0
commit
7e84b55d8f
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@ -1,3 +1,14 @@
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* config/tc-aarch64.c (now_instr_sequence):
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(*insn_sequence, now_instr_sequence): New.
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(output_operand_error_record, do_encode): Add insn_sequence.
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(md_assemble): Update insn_sequence.
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(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
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Pass insn_sequence.
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* config/tc-aarch64.h (struct aarch64_segment_info_type):
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Add insn_sequence.
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2018-10-02 Palmer Dabbelt <palmer@sifive.com>
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* testsuite/gas/riscv/fence-tso.d: New file.
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@ -55,6 +55,9 @@ static const aarch64_feature_set *march_cpu_opt = NULL;
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/* Constants for known architecture features. */
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static const aarch64_feature_set cpu_default = CPU_DEFAULT;
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/* Currently active instruction sequence. */
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static aarch64_instr_sequence *insn_sequence = NULL;
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#ifdef OBJ_ELF
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/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
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static symbolS *GOT_symbol;
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@ -146,6 +149,13 @@ static aarch64_instruction inst;
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static bfd_boolean parse_operands (char *, const aarch64_opcode *);
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static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
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#ifdef OBJ_ELF
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# define now_instr_sequence seg_info \
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(now_seg)->tc_segment_info_data.insn_sequence
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#else
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static struct aarch64_instr_sequence now_instr_sequence;
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#endif
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/* Diagnostics inline function utilities.
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These are lightweight utilities which should only be called by parse_operands
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@ -4661,7 +4671,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
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&& programmer_friendly_fixup (&inst);
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gas_assert (result);
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result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
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NULL, NULL);
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NULL, NULL, insn_sequence);
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gas_assert (!result);
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/* Find the most matched qualifier sequence. */
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@ -6738,7 +6748,7 @@ do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
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aarch64_operand_error error_info;
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memset (&error_info, '\0', sizeof (error_info));
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error_info.kind = AARCH64_OPDE_NIL;
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if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info)
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if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info, insn_sequence)
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&& !error_info.non_fatal)
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return TRUE;
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@ -6784,6 +6794,9 @@ md_assemble (char *str)
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S_SET_SEGMENT (last_label_seen, now_seg);
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}
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/* Update the current insn_sequence from the segment. */
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insn_sequence = &seg_info (now_seg)->tc_segment_info_data.insn_sequence;
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inst.reloc.type = BFD_RELOC_UNUSED;
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DEBUG_TRACE ("\n\n");
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@ -7376,7 +7389,8 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
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DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
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if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
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if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL,
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insn_sequence))
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return FALSE;
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return TRUE;
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@ -7410,7 +7424,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
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opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
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aarch64_replace_opcode (instr, opcode);
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if (aarch64_opcode_encode (instr->opcode, instr,
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&instr->value, NULL, NULL))
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&instr->value, NULL, NULL, insn_sequence))
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{
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put_aarch64_insn (buf, instr->value);
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return;
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@ -7419,7 +7433,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
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opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
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aarch64_replace_opcode (instr, opcode);
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if (aarch64_opcode_encode (instr->opcode, instr,
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&instr->value, NULL, NULL))
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&instr->value, NULL, NULL, insn_sequence))
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{
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put_aarch64_insn (buf, instr->value);
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return;
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@ -7432,7 +7446,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
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opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
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aarch64_replace_opcode (instr, opcode);
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if (aarch64_opcode_encode (instr->opcode, instr,
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&instr->value, NULL, NULL))
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&instr->value, NULL, NULL, insn_sequence))
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{
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put_aarch64_insn (buf, instr->value);
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return;
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@ -7543,7 +7557,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
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idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
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new_inst->operands[idx].imm.value = value;
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if (aarch64_opcode_encode (new_inst->opcode, new_inst,
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&new_inst->value, NULL, NULL))
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&new_inst->value, NULL, NULL, insn_sequence))
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put_aarch64_insn (buf, new_inst->value);
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else
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as_bad_where (fixP->fx_file, fixP->fx_line,
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@ -7597,7 +7611,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
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/* Encode/fix-up. */
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if (aarch64_opcode_encode (new_inst->opcode, new_inst,
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&new_inst->value, NULL, NULL))
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&new_inst->value, NULL, NULL, insn_sequence))
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{
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put_aarch64_insn (buf, new_inst->value);
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break;
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@ -183,6 +183,7 @@ struct aarch64_segment_info_type
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{
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enum mstate mapstate;
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unsigned int marked_pr_dependency;
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aarch64_instr_sequence insn_sequence;
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};
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/* We want .cfi_* pseudo-ops for generating unwind info. */
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@ -1,3 +1,8 @@
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* opcode/aarch64.h (struct aarch64_instr_sequence): New.
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(aarch64_opcode_encode): Use it.
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
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@ -662,6 +662,13 @@ empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
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return TRUE;
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}
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/* Forward declare error reporting type. */
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typedef struct aarch64_operand_error aarch64_operand_error;
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/* Forward declare instruction sequence type. */
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typedef struct aarch64_instr_sequence aarch64_instr_sequence;
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/* Forward declare instruction definition. */
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typedef struct aarch64_inst aarch64_inst;
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/* This structure holds information for a particular opcode. */
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struct aarch64_opcode
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@ -1124,14 +1131,27 @@ struct aarch64_operand_error
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bfd_boolean non_fatal;
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};
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typedef struct aarch64_operand_error aarch64_operand_error;
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/* AArch64 sequence structure used to track instructions with F_SCAN
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dependencies for both assembler and disassembler. */
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struct aarch64_instr_sequence
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{
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/* The instruction that caused this sequence to be opened. */
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aarch64_inst *instr;
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/* The number of instructions the above instruction allows to be kept in the
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sequence before an automatic close is done. */
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int num_insns;
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/* The instructions currently added to the sequence. */
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aarch64_inst **current_insns;
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/* The number of instructions already in the sequence. */
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int next_insn;
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};
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/* Encoding entrypoint. */
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extern int
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aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
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aarch64_insn *, aarch64_opnd_qualifier_t *,
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aarch64_operand_error *);
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aarch64_operand_error *, aarch64_instr_sequence *);
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extern const aarch64_opcode *
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aarch64_replace_opcode (struct aarch64_inst *,
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@ -1,3 +1,8 @@
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
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* aarch64-dis.c (insn_sequence): New.
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2018-10-03 Tamar Christina <tamar.christina@arm.com>
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* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
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@ -1948,7 +1948,8 @@ bfd_boolean
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aarch64_opcode_encode (const aarch64_opcode *opcode,
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const aarch64_inst *inst_ori, aarch64_insn *code,
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aarch64_opnd_qualifier_t *qlf_seq,
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aarch64_operand_error *mismatch_detail)
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aarch64_operand_error *mismatch_detail,
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aarch64_instr_sequence* insn_sequence ATTRIBUTE_UNUSED)
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{
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int i;
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const aarch64_opcode *aliased;
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@ -49,6 +49,9 @@ static int no_aliases = 0; /* If set disassemble as most general inst. */
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static int no_notes = 1; /* If set do not print disassemble notes in the
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output as comments. */
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/* Currently active instruction sequence. */
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static aarch64_instr_sequence insn_sequence ATTRIBUTE_UNUSED;
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static void
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set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
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{
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