[MIPS] Add RDHWR with the SEL field for MIPS R6.
In Release 6 of the MIPS architecture [1], instruction RDHWR supports
a 3rd operand to serve as the 3-bit select field for the hardware
register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 332-334
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
gas/
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
This commit is contained in:
Robert Suchanek
Chenghua Xu
parent
2b0c8b0199
commit
7e96e219a4
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@ -1,3 +1,10 @@
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2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
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* testsuite/gas/mips/mips.exp: Run hwr-names test.
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* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
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the SEL field.
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* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (output_insn): Support
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@ -40,5 +40,16 @@ text_label:
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rdhwr $0, $30
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rdhwr $0, $31
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.ifdef r6
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rdhwr $0, $4, 0
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rdhwr $0, $4, 1
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rdhwr $0, $4, 2
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rdhwr $0, $4, 3
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rdhwr $0, $4, 4
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rdhwr $0, $4, 5
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rdhwr $0, $4, 6
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rdhwr $0, $4, 7
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.endif
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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@ -1342,6 +1342,8 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test "hwr-names-numeric"
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run_dump_test "hwr-names-mips32r2"
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run_dump_test "hwr-names-mips64r2"
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run_dump_test_arches "hwr-names" [mips_arch_list_matching mips32r6 \
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!micromipsr6]
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run_dump_test "ldstla-32"
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run_dump_test "ldstla-32-mips3"
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@ -0,0 +1,51 @@
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#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32r6 -M gpr-names=numeric,hwr-names=mips32r6
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#name: MIPS HWR disassembly (mips32r6)
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#as: -32
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#source: hwr-names.s
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# Check objdump's handling of -M hwr-names=foo options.
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.*: +file format .*mips.*
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Disassembly of section .text:
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0+0000 <[^>]*> 7c00003b rdhwr \$0,hwr_cpunum
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0+0004 <[^>]*> 7c00083b rdhwr \$0,hwr_synci_step
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0+0008 <[^>]*> 7c00103b rdhwr \$0,hwr_cc
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0+000c <[^>]*> 7c00183b rdhwr \$0,hwr_ccres
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0+0010 <[^>]*> 7c00203b rdhwr \$0,\$4
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0+0014 <[^>]*> 7c00283b rdhwr \$0,\$5
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0+0018 <[^>]*> 7c00303b rdhwr \$0,\$6
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0+001c <[^>]*> 7c00383b rdhwr \$0,\$7
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0+0020 <[^>]*> 7c00403b rdhwr \$0,\$8
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0+0024 <[^>]*> 7c00483b rdhwr \$0,\$9
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0+0028 <[^>]*> 7c00503b rdhwr \$0,\$10
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0+002c <[^>]*> 7c00583b rdhwr \$0,\$11
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0+0030 <[^>]*> 7c00603b rdhwr \$0,\$12
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0+0034 <[^>]*> 7c00683b rdhwr \$0,\$13
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0+0038 <[^>]*> 7c00703b rdhwr \$0,\$14
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0+003c <[^>]*> 7c00783b rdhwr \$0,\$15
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0+0040 <[^>]*> 7c00803b rdhwr \$0,\$16
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0+0044 <[^>]*> 7c00883b rdhwr \$0,\$17
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0+0048 <[^>]*> 7c00903b rdhwr \$0,\$18
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0+004c <[^>]*> 7c00983b rdhwr \$0,\$19
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0+0050 <[^>]*> 7c00a03b rdhwr \$0,\$20
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0+0054 <[^>]*> 7c00a83b rdhwr \$0,\$21
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0+0058 <[^>]*> 7c00b03b rdhwr \$0,\$22
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0+005c <[^>]*> 7c00b83b rdhwr \$0,\$23
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0+0060 <[^>]*> 7c00c03b rdhwr \$0,\$24
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0+0064 <[^>]*> 7c00c83b rdhwr \$0,\$25
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0+0068 <[^>]*> 7c00d03b rdhwr \$0,\$26
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0+006c <[^>]*> 7c00d83b rdhwr \$0,\$27
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0+0070 <[^>]*> 7c00e03b rdhwr \$0,\$28
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0+0074 <[^>]*> 7c00e83b rdhwr \$0,\$29
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0+0078 <[^>]*> 7c00f03b rdhwr \$0,\$30
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0+007c <[^>]*> 7c00f83b rdhwr \$0,\$31
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0+0080 <[^>]*> 7c00203b rdhwr \$0,\$4
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0+0084 <[^>]*> 7c00207b rdhwr \$0,\$4,1
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0+0088 <[^>]*> 7c0020bb rdhwr \$0,\$4,2
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0+008c <[^>]*> 7c0020fb rdhwr \$0,\$4,3
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0+0090 <[^>]*> 7c00213b rdhwr \$0,\$4,4
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0+0094 <[^>]*> 7c00217b rdhwr \$0,\$4,5
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0+0098 <[^>]*> 7c0021bb rdhwr \$0,\$4,6
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0+009c <[^>]*> 7c0021fb rdhwr \$0,\$4,7
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\.\.\.
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@ -1,3 +1,7 @@
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2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
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* mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
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2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.tbl: Consolidate AVX512 BF16 entries.
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@ -1781,6 +1781,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 },
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{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 },
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{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 },
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{"rdhwr", "t,K,+O", 0x7c00003b, 0xffe0063f, WR_1, 0, I37, 0, 0 },
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{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 },
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/* rfe is moved below as it now conflicts with tlbgp */
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{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_1|RD_2|FP_D, RD_MACC, 0, MX, 0 },
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