Rewrite for H8/300-H
This commit is contained in:
Steve Chamberlain
parent
357992027a
commit
7ecaa5af33
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@ -29,12 +29,9 @@ ChangeLog
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Makefile.in
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configure.in
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h8300.mt
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writecode.c
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compile.c
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run.c
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p1.c
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p3.c
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perifs.c
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state.h
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inst.h
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Things-to-lose:
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@ -0,0 +1,71 @@
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#define DEBUG
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#define MPOWER 16
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#define MSIZE (1<<MPOWER)
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#define CSIZE 1000
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/* Local register names */
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typedef enum
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{
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R0, R1, R2, R3, R4, R5, R6, R7,
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R_ZERO,
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R_PC,
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R_CCR,
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R_HARD_0,
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R_LAST,
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} reg_type;
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/* Structure used to describe addressing */
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typedef struct
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{
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int type;
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int reg;
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int literal;
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} ea_type;
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typedef struct
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{
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ea_type src;
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ea_type dst;
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int opcode;
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int next_pc;
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int oldpc;
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int cycles;
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#ifdef DEBUG
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struct h8_opcode *op;
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#endif
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}
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decoded_inst;
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typedef struct
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{
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int exception;
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unsigned int regs[9];
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int pc;
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int ccr;
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unsigned char *memory;
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unsigned short *cache_idx;
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int cache_top;
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int maximum;
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int csize;
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int mask;
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decoded_inst *cache;
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int cycles;
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int insts;
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int ticks;
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int compiles;
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#ifdef ADEBUG
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int stats[O_LAST];
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#endif
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}
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cpu_state_type;
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246
sim/h8300/p1.c
246
sim/h8300/p1.c
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@ -1,246 +0,0 @@
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/* Interpreter fragment for the Hitachi H8/300 architecture simulator.
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Written by Steve Chamberlain of Cygnus Support.
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sac@cygnus.com
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This file is part of H8/300 sim
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THIS SOFTWARE IS NOT COPYRIGHTED
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Cygnus offers the following for use in the public domain. Cygnus
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makes no warranty with regard to the software or it's performance
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and the user accepts the software "AS IS" with all faults.
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CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
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THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <signal.h>
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#include "state.h"
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#define V (v!=0)
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#define C (c!=0)
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#define N (n!=0)
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#define Z (z!=0)
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#define SET_CCR(x) n = x & 0x8; v = x & 0x2; z = x & 0x4; c = x & 0x1;saved_state.ienable=x&0x80;
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#define GET_CCR() ((N << 3) | (Z<<2) | (V<<1) | C) | ((!saved_state.ienable)<<7)
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static union
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{
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short int i;
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struct
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{
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char low;
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char high;
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}
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u;
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}
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littleendian;
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static void
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meminit ()
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{
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if (saved_state.mem == 0)
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{
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int tmp;
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saved_state.mem = (unsigned short *)calloc (1024, 64);
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littleendian.i = 1;
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/* initialze the array of pointers to byte registers */
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for (tmp = 0; tmp < 8; tmp++)
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{
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if (littleendian.u.high)
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{
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saved_state.bregp[tmp] = (unsigned char *) (saved_state.reg + tmp);
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saved_state.bregp[tmp + 8] = saved_state.bregp[tmp] + 1;
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}
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else
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{
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saved_state.bregp[tmp + 8] = (unsigned char *) (saved_state.reg + tmp);
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saved_state.bregp[tmp] = saved_state.bregp[tmp + 8] + 1;
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}
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}
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/* we keep two 256 sized pointers to byte regs, one for when we
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want to look at the reg descibed by bits NNNNxxxx and one for
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when we want to look at xxxxNNNN */
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for (tmp = 0; tmp < 256; tmp++)
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{
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saved_state.bregp_NNNNxxxx[tmp] = saved_state.bregp[(tmp >> 4) & 0xf];
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saved_state.bregp_xxxxNNNN[tmp] = saved_state.bregp[tmp & 0xf];
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}
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/* We keep two 256 sized pointers to word regs, one for regs in
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xNNNxxxx and one for regs in xxxxxNNNN */
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for (tmp = 0; tmp < 256; tmp++)
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{
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saved_state.wregp_xNNNxxxx[tmp] = &saved_state.reg[(tmp >> 4) & 0x7];
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saved_state.wregp_xxxxxNNN[tmp] = &saved_state.reg[tmp & 0x7];
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}
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saved_state.reg[HCHECK] = 10000000; /* don't check the hardware
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often */
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}
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}
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void
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control_c (sig, code, scp, addr)
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int sig;
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int code;
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char *scp;
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char *addr;
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{
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saved_state.exception = SIGINT;
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}
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void
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sim_store_register (reg, val)
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int reg;
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int val;
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{
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saved_state.reg[reg] = val;
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}
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void
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sim_fetch_register (reg, buf)
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int reg;
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char *buf;
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{
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meminit();
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buf[0] = saved_state.reg[reg] >> 8;
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buf[1] = saved_state.reg[reg];
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}
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void
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sim_write (to, from, len)
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int to;
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char *from;
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int len;
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{
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int i;
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meminit ();
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for ( i = 0; i < len; i++)
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SET_BYTE_MEM(to + i, from[i]);
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}
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void
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sim_read (from, to, len)
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int from;
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char *to;
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int len;
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{
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int i;
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meminit ();
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for (i = 0; i < len; i++) {
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to[i] = BYTE_MEM(from + i);
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}
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}
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int
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sim_stop_signal ()
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{
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return saved_state.exception;
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}
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void
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load_timer_state_from_mem()
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{
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saved_state.reg[TIER] = BYTE_MEM(0xff90);
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saved_state.reg[TCSR] = BYTE_MEM(0xff91);
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saved_state.reg[FRC] = WORD_MEM(0xff92);
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saved_state.reg[TCR] = BYTE_MEM(0xff96);
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saved_state.reg[TOCR] = BYTE_MEM(0xff97);
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if ((saved_state.reg[TOCR] & OCRS) == 0)
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{
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saved_state.reg[OCRA] = WORD_MEM(0xff94);
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}
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else
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{
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saved_state.reg[OCRB] = WORD_MEM(0xff94);
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}
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}
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void
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store_timer_state_to_mem()
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{
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BYTE_MEM(0xff91) = saved_state.reg[TCSR];
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SET_WORD_MEM(0xff92, saved_state.reg[FRC]);
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}
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void
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sim_resume (step, sig)
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int step;
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int sig;
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{
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int lval;
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int tmp;
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int b0;
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int b1;
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int checkfreq;
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int ni; /* Number of insts to execute before checking hw state */
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unsigned char **blow;
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unsigned char **bhigh;
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unsigned short **wlow;
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unsigned short **whigh;
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unsigned short *npc;
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int rn;
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unsigned short int *reg;
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unsigned char **bregp;
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void (*prev) ();
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unsigned short *pc;
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int srca;
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int srcb;
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int dst;
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int cycles ;
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int n;
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int v;
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int z;
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int c;
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/* Set up pointers to areas */
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reg = saved_state.reg;
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bregp = saved_state.bregp;
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blow = saved_state.bregp_xxxxNNNN;
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bhigh = saved_state.bregp_NNNNxxxx;
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wlow = saved_state.wregp_xxxxxNNN;
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whigh = saved_state.wregp_xNNNxxxx;
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prev = signal (SIGINT, control_c);
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meminit();
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LOAD_INTERPRETER_STATE();
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if (step)
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saved_state.exception = SIGTRAP;
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else
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{
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saved_state.exception = sig;
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}
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do
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{
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b1 = pc[0];
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b0 = b1>> 8;
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b1 &= 0xff;
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@ -1,78 +0,0 @@
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/* Interpreter fragment for the Hitachi H8/300 architecture simulator.
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Written by Steve Chamberlain of Cygnus Support.
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sac@cygnus.com
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This file is part of H8/300 sim
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THIS SOFTWARE IS NOT COPYRIGHTED
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Cygnus offers the following for use in the public domain. Cygnus
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makes no warranty with regard to the software or it's performance
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and the user accepts the software "AS IS" with all faults.
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CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
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THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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movflags8:
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n = dst & 0x80;
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z = !(dst & 0xff);
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v = 0;
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goto next;
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movflags16:
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n = dst & 0x8000;
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z = !(dst & 0xffff);
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v = 0;
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goto next;
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aluflags8:
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n = dst & 0x80;
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z = !(dst & 0xff);
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v = ((srca & 0x80) == (srcb & 0x80)) && ((srca & 0x80) != (dst & 0x80));
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c = dst & 0x100;
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goto next;
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aluflags16:
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n = dst & 0x8000;
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z = !(dst & 0xffff);
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v = ((srca & 0x8000) == (srcb & 0x8000)) && ((srca & 0x8000) != (dst & 0x8000));
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c = dst & 0x10000;
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goto next;
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setflags:;
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SET_CCR(tmp);
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goto next;
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logflags:
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shiftflags:
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v = 0;
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incflags:
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z = !(dst & 0xff);
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n = dst & 0x80;
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goto next;
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next: ;
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pc = npc;
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if (ni > checkfreq)
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{
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ni = 0;
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SAVE_INTERPRETER_STATE();
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perifs();
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LOAD_INTERPRETER_STATE();
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#ifdef __GO32__
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if (kbhit())
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saved_state.exception = SIGINT;
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#endif
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}
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ni++;
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} while (!saved_state.exception);
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SAVE_INTERPRETER_STATE();
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}
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sim_info()
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{
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int cycles = saved_state.reg[CYCLES];
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printf("cycles (v approximate) %10d\n", cycles);
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}
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@ -35,6 +35,18 @@ main (ac, av)
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char *name = "";
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for (i = 1; i < ac; i++)
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{
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<<<<<<< run.c
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verbose ++;
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}
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else if (strcmp(av[i],"-t") == 0)
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{
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trace = 1;
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}
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else if (strcmp(av[i],"-c") == 0)
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{
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sim_csize(atoi(av[i+1]));
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i++;
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=======
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if (strcmp (av[i], "-v") == 0)
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{
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verbose = 1;
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@ -48,15 +60,55 @@ main (ac, av)
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{
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name = av[i];
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}
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>>>>>>> 1.4
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}
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<<<<<<< run.c
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else
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=======
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if (verbose)
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>>>>>>> 1.4
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{
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<<<<<<< run.c
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name = av[i];
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=======
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printf ("run %s\n", name);
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>>>>>>> 1.4
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}
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<<<<<<< run.c
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}
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if (verbose)
|
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{
|
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printf("run %s\n", name);
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}
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abfd = bfd_openr(name,"coff-h8300");
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=======
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abfd = bfd_openr (name, "coff-h8300");
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>>>>>>> 1.4
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<<<<<<< run.c
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if (abfd)
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=======
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if (abfd)
|
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>>>>>>> 1.4
|
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{
|
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<<<<<<< run.c
|
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if (bfd_check_format(abfd, bfd_object))
|
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{
|
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|
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for (s = abfd->sections; s; s=s->next)
|
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{
|
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char *buffer = malloc(bfd_section_size(abfd,s));
|
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bfd_get_section_contents(abfd, s, buffer, 0, bfd_section_size(abfd,s));
|
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sim_write(s->vma, buffer, bfd_section_size(abfd,s));
|
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}
|
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|
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start_address = bfd_get_start_address(abfd);
|
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sim_store_register(
|
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9,start_address);
|
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sim_resume(0,0);
|
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if (verbose)
|
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sim_info (verbose);
|
||||
=======
|
||||
if (bfd_check_format (abfd, bfd_object))
|
||||
{
|
||||
|
||||
|
|
@ -73,9 +125,14 @@ main (ac, av)
|
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sim_resume (0, 0);
|
||||
if (verbose)
|
||||
sim_info ();
|
||||
>>>>>>> 1.4
|
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|
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<<<<<<< run.c
|
||||
return 0;
|
||||
=======
|
||||
return 0;
|
||||
}
|
||||
>>>>>>> 1.4
|
||||
}
|
||||
|
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return 1;
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|
|
|
|||
|
|
@ -1,86 +0,0 @@
|
|||
/*
|
||||
Written by Steve Chamberlain of Cygnus Support.
|
||||
sac@cygnus.com
|
||||
|
||||
This file is part of H8/300 sim
|
||||
|
||||
|
||||
THIS SOFTWARE IS NOT COPYRIGHTED
|
||||
|
||||
Cygnus offers the following for use in the public domain. Cygnus
|
||||
makes no warranty with regard to the software or it's performance
|
||||
and the user accepts the software "AS IS" with all faults.
|
||||
|
||||
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
|
||||
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||
|
||||
*/
|
||||
#include "../endian.h"
|
||||
#define SET_WORD_MEM(x,y) {saved_state.mem[(x)>>1] = y;}
|
||||
#define SET_BYTE_MEM(x,y) {BYTE_MEM(x)=y;}
|
||||
|
||||
#define WORD_MEM(x) (saved_state.mem[(x)>>1])
|
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#define BYTE_MEM(x) (*(((char *)(saved_state.mem))+((x)^HOST_IS_LITTLE_ENDIAN)))
|
||||
|
||||
#define CCR 8
|
||||
#define PC 9
|
||||
#define CYCLES 10
|
||||
#define HCHECK 11
|
||||
#define TIER 12
|
||||
#define TCSR 13
|
||||
#define FRC 14
|
||||
#define OCRA 15
|
||||
#define OCRB 16
|
||||
#define TCR 17
|
||||
#define TOCR 18
|
||||
#define ICRA 19
|
||||
#define NREG 20
|
||||
struct state
|
||||
{
|
||||
unsigned short int reg[NREG];
|
||||
unsigned char *(bregp[16]);
|
||||
unsigned char *(bregp_NNNNxxxx[256]);
|
||||
unsigned char *(bregp_xxxxNNNN[256]);
|
||||
unsigned short int *(wregp_xNNNxxxx[256]);
|
||||
unsigned short int *(wregp_xxxxxNNN[256]);
|
||||
int exception;
|
||||
int ienable;
|
||||
unsigned short *mem;
|
||||
}
|
||||
|
||||
saved_state;
|
||||
|
||||
|
||||
|
||||
#define OCFA (1<<3)
|
||||
#define OCFB (1<<2)
|
||||
#define CCLRA (1<<0)
|
||||
/* TCR bits */
|
||||
#define OCIEA (1<<3)
|
||||
#define OCIEB (1<<2)
|
||||
#define OVIE (1<<1)
|
||||
#define OVF (1<<1)
|
||||
|
||||
/* TOCR bits */
|
||||
#define OCRS (1<<4)
|
||||
|
||||
|
||||
#ifdef LITTLE_ENDIAN_HOST
|
||||
#define HOST_IS_LITTLE_ENDIAN 1
|
||||
#else
|
||||
#define HOST_IS_LITTLE_ENDIAN 0
|
||||
#endif
|
||||
|
||||
#define SAVE_INTERPRETER_STATE() \
|
||||
saved_state.reg[CYCLES] = cycles; \
|
||||
saved_state.reg[PC] = (pc - saved_state.mem) <<1; \
|
||||
saved_state.reg[CCR] = GET_CCR(); \
|
||||
store_timer_state_to_mem();
|
||||
|
||||
#define LOAD_INTERPRETER_STATE() \
|
||||
SET_CCR (saved_state.reg[CCR]); \
|
||||
checkfreq = saved_state.reg[HCHECK]; \
|
||||
pc = (saved_state.reg[PC]>>1) + saved_state.mem; \
|
||||
load_timer_state_from_mem(); \
|
||||
cycles=saved_state.reg[CYCLES];
|
||||
Loading…
Reference in New Issue