More debug support; Enable -t/-v to work correctly; Add --enable-sim-cflags configure switch
This commit is contained in:
parent
10d183a0f0
commit
7eebfc6296
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@ -5,17 +5,41 @@ Wed Sep 4 11:35:17 1996 Michael Meissner <meissner@tiktok.cygnus.com>
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(_ins_type): New enumeration to specify which container an
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instruction is in, and whether it is part of a parallel operation.
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(_state): Add ins_type field.
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* simops.c: Change all #ifdef DEBUG code so that the input and
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output values can be traced, along with the instruction type.
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({,u}int{8,16,32,64}): Use limits.h to size the appropriate types.
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(ins_type_counters): Counters for the various instruction types.
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({left,right}_nops): Counters for the number of nops in each
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container.
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(d10v_debug): New variable to indicate whether debugging is turned
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on.
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* simops.c: (all functions): Change all #ifdef DEBUG code so that
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the input and output values can be traced, along with the
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instruction type. Make the -t option enable tracing.
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(all functions): Change printf calls to use the printf_filtered
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function in the callback table.
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* interp.c (_leftright): New enumeration to say whether 2 short
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instructions are done left first or right first.
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(do_{long,2_short,parallel}): Indicate in the machine state which
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type of instruction this is.
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type of instruction this is. Count each of the types of
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instructions executed.
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(sim_size): Only print the memory sizes if DEBUG_MEMSIZE debug
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flag is set.
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(sim_resume): Pass left/right indication to do_2_short.
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(all functions): Change printf calls to use the printf_filtered
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function in the callback table.
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(sim_trace): Turn on debug flag if DEBUG was defined, and call
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sim_resume.
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(sim_info): Print out statistics on instructions.
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(sim_{trace,create_inferior}): Eliminate extraneous output unless
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debugging.
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* Makefile.in: Make objects depend on d10v_sim.h.
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({,SIM_}CFLAGS): Include configure dependent switches.
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* configure.in (--enable-sim-cflags): New switch to allow user to
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set the defaults.
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* configure: Regenerate.
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Wed Sep 04 04:45:34 1996 Mark Alexander <marka@cygnus.com>
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@ -1,5 +1,5 @@
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# Makefile template for Configure for the SH sim library.
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# Copyright (C) 1990, 1991, 1992, 1995 Free Software Foundation, Inc.
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# Copyright (C) 1996 Free Software Foundation, Inc.
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# Written by Cygnus Support.
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#
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# This program is free software; you can redistribute it and/or modify
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@ -56,7 +56,8 @@ INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1
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AR = @AR@
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AR_FLAGS = rc
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CC = @CC@
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CFLAGS = @CFLAGS@ @DEFS@
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SIM_CFLAGS = @sim_cflags@
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CFLAGS = @CFLAGS@ @DEFS@ $(SIM_CFLAGS)
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MAKEINFO = makeinfo
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RANLIB = @RANLIB@
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CC_FOR_BUILD = @CC_FOR_BUILD@
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@ -67,14 +68,15 @@ TDEFINES =
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.NOEXPORT:
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MAKEOVERRIDES=
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X=xstuff.o
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XL=-lX11
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#X=xstuff.o
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#XL=-lX11
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X=
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XL=
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INCLUDE = d10v_sim.h
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INCDIR = $(srcdir)/../../include
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CSEARCH = -I. -I$(srcdir) -I../../include \
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-I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/sh
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-I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/d10v
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DEP = mkdep
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all: run libsim.a
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@ -82,8 +84,9 @@ all: run libsim.a
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run: interp.o $(X) run.o table.o callback.o simops.o
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$(CC) $(CFLAGS) -o run $(X) interp.o table.o callback.o simops.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a $(XL) -lm
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interp.o:interp.c table.c
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run.o:run.c
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interp.o:interp.c table.c $(INCLUDE)
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run.o:run.c $(INCLUDE)
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simops.o:simops.c $(INCLUDE)
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libsim.a:interp.o table.o simops.o
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$(AR) $(ARFLAGS) libsim.a interp.o table.o simops.o
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@ -95,7 +98,7 @@ simops.h: gencode
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table.c: gencode simops.h
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./gencode >$@
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gencode: gencode.c ../../opcodes/libopcodes.a
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gencode: gencode.c ../../opcodes/libopcodes.a $(INCLUDE)
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$(CC) $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHE) -o gencode $(srcdir)/gencode.c ../../opcodes/libopcodes.a -lc
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.c.o:
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File diff suppressed because it is too large
Load Diff
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@ -11,11 +11,24 @@ AC_C_BIGENDIAN
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. ${srcdir}/../../bfd/configure.host
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AC_ARG_ENABLE(sim-cflags,
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[ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator],
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[case "${enableval}" in
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yes) sim_cflags="-O2";;
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trace) sim_cflags="-O2 -DDEBUG=3";;
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no) sim_cflags="";;
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*) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
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esac
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if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
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echo "Setting sim cflags = $sim_cflags" 6>&1
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fi],[sim_cflags=""])dnl
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AC_SUBST(CFLAGS)
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AC_SUBST(HDEFINES)
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AR=${AR-ar}
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AC_SUBST(AR)
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AC_PROG_RANLIB
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AC_SUBST(sim_cflags)
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# Put a plausible default for CC_FOR_BUILD in Makefile.
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AC_C_CROSS
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@ -1,26 +1,55 @@
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#include <stdio.h>
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#include <ctype.h>
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#include <limits.h>
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#include "ansidecl.h"
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#include "callback.h"
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#include "opcode/d10v.h"
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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#define DEBUG_MEMSIZE 0x00000004
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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#define DEBUG_MEMSIZE 0x00000004
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#define DEBUG_INSTRUCTION 0x00000008
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#ifndef DEBUG
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#define DEBUG 0
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extern int d10v_debug;
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#if UCHAR_MAX == 255
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typedef unsigned char uint8;
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typedef signed char int8;
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#else
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#error "Char is not an 8-bit type"
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#endif
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/* FIXME: host defines */
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typedef unsigned char uint8;
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#if SHRT_MAX == 32767
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typedef unsigned short uint16;
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typedef unsigned int uint32;
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typedef signed char int8;
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typedef signed short int16;
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#else
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#error "Short is not a 16-bit type"
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#endif
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#if INT_MAX == 2147483647
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typedef unsigned int uint32;
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typedef signed int int32;
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#elif LONG_MAX == 2147483647
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typedef unsigned long uint32;
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typedef signed long int32;
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#else
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#error "Neither int nor long is a 32-bit type"
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#endif
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#if LONG_MAX > 2147483647
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typedef unsigned long uint64;
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typedef signed long int64;
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#elif __GNUC__
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typedef unsigned long long uint64;
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typedef signed long long int64;
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#else
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#error "Can't find an appropriate 64-bit type"
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#endif
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/* FIXME: D10V defines */
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typedef uint16 reg_t;
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@ -44,9 +73,13 @@ enum _ins_type
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INS_RIGHT,
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INS_LEFT_PARALLEL,
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INS_RIGHT_PARALLEL,
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INS_LONG
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INS_LONG,
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INS_MAX
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};
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extern long ins_type_counters[ (int)INS_MAX ];
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extern long left_nops, right_nops;
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struct _state
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{
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reg_t regs[16]; /* general-purpose registers */
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@ -10,7 +10,10 @@
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enum _leftright { LEFT_FIRST, RIGHT_FIRST };
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int d10v_debug;
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host_callback *d10v_callback;
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long ins_type_counters[ (int)INS_MAX ];
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long left_nops, right_nops;
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uint16 OP[4];
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@ -54,7 +57,7 @@ lookup_hash (ins, size)
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{
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if (h->next == NULL)
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{
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printf ("ERROR looking up hash for %x at PC %x\n",ins, PC);
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(*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
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exit(1);
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}
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h = h->next;
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@ -145,10 +148,14 @@ do_long (ins)
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uint32 ins;
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{
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struct hash_entry *h;
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/* printf ("do_long %x\n",ins); */
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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(*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
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#endif
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h = lookup_hash (ins, 1);
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get_operands (h->ops, ins);
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State.ins_type = INS_LONG;
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ins_type_counters[ (int)State.ins_type ]++;
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(h->ops->func)();
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}
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static void
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enum _leftright leftright;
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{
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struct hash_entry *h;
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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(*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
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ins1, (leftright) ? "left" : "right", ins2);
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#endif
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/* printf ("do_2_short %x -> %x\n",ins1,ins2); */
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h = lookup_hash (ins1, 0);
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get_operands (h->ops, ins1);
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State.ins_type = (leftright == LEFT_FIRST) ? INS_LEFT : INS_RIGHT;
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ins_type_counters[ (int)State.ins_type ]++;
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(h->ops->func)();
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h = lookup_hash (ins2, 0);
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get_operands (h->ops, ins2);
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State.ins_type = (leftright == LEFT_FIRST) ? INS_RIGHT : INS_LEFT;
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ins_type_counters[ (int)State.ins_type ]++;
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(h->ops->func)();
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}
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static void
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uint16 ins1, ins2;
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{
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struct hash_entry *h1, *h2;
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/* printf ("do_parallel %x || %x\n",ins1,ins2); */
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
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(*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
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#endif
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h1 = lookup_hash (ins1, 0);
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h2 = lookup_hash (ins2, 0);
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@ -180,6 +197,7 @@ do_parallel (ins1, ins2)
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT;
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ins_type_counters[ (int)State.ins_type ]++;
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(h1->ops->func)();
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if (State.exe)
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{
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@ -192,6 +210,7 @@ do_parallel (ins1, ins2)
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{
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT;
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ins_type_counters[ (int)State.ins_type ]++;
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(h2->ops->func)();
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if (State.exe)
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{
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@ -204,9 +223,11 @@ do_parallel (ins1, ins2)
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{
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get_operands (h1->ops, ins1);
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State.ins_type = INS_LEFT_PARALLEL;
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ins_type_counters[ (int)State.ins_type ]++;
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(h1->ops->func)();
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get_operands (h2->ops, ins2);
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State.ins_type = INS_RIGHT_PARALLEL;
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ins_type_counters[ (int)State.ins_type ]++;
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(h2->ops->func)();
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}
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}
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@ -227,12 +248,16 @@ sim_size (power)
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State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
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if (!State.imem || !State.dmem )
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{
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fprintf (stderr,"Memory allocation failed.\n");
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(*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
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exit(1);
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}
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#if (DEBUG & DEBUG_MEMSIZE) != 0
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printf ("Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE);
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printf (" %d bytes data memory.\n",1<<DMEM_SIZE);
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#ifdef DEBUG
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if ((d10v_debug & DEBUG_MEMSIZE) != 0)
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{
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(*d10v_callback->printf_filtered) (d10v_callback, "Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE);
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(*d10v_callback->printf_filtered) (d10v_callback, " %d bytes data memory.\n", 1<<DMEM_SIZE);
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}
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#endif
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}
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@ -252,7 +277,7 @@ sim_write (addr, buffer, size)
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int i;
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init_system ();
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/* printf ("sim_write %d bytes to 0x%x\n",size,addr); */
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/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n",size,addr); */
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for (i = 0; i < size; i++)
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{
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State.imem[i+addr] = buffer[i];
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@ -267,7 +292,7 @@ sim_open (args)
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struct simops *s;
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struct hash_entry *h, *prev;
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if (args != NULL)
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printf ("sim_open %s\n",args);
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_open %s\n",args);
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/* put all the opcodes in the hash table */
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for (s = Simops; s->func; s++)
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@ -301,14 +326,14 @@ void
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sim_set_profile (n)
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int n;
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{
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printf ("sim_set_profile %d\n",n);
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
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}
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void
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sim_set_profile_size (n)
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int n;
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{
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printf ("sim_set_profile_size %d\n",n);
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(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
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}
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void
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@ -319,7 +344,7 @@ sim_resume (step, siggnal)
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int i;
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reg_t oldpc;
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/* printf ("sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
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/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
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if (step)
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State.exception = SIGTRAP;
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@ -368,15 +393,47 @@ sim_resume (step, siggnal)
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int
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sim_trace ()
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{
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printf ("sim_trace\n");
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return 0;
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#ifdef DEBUG
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d10v_debug = DEBUG;
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#endif
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sim_resume (0, 0);
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return 1;
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}
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void
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sim_info (verbose)
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int verbose;
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{
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printf ("sim_info\n");
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char buf[40];
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int size;
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long total = (ins_type_counters[ (int)INS_LONG ]
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+ ins_type_counters[ (int)INS_LEFT ]
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+ ins_type_counters[ (int)INS_LEFT_PARALLEL ]
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+ ins_type_counters[ (int)INS_RIGHT ]
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+ ins_type_counters[ (int)INS_RIGHT_PARALLEL ]);
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sprintf (buf, "%ld", total);
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size = strlen (buf);
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(*d10v_callback->printf_filtered) (d10v_callback,
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"executed %*ld instructions in the left container, %*ld parallel, %*ld nops\n",
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size, ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_PARALLEL ],
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size, ins_type_counters[ (int)INS_LEFT_PARALLEL ],
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size, left_nops);
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(*d10v_callback->printf_filtered) (d10v_callback,
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"executed %*ld instructions in the right container, %*ld parallel, %*ld nops\n",
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size, ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_PARALLEL ],
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size, ins_type_counters[ (int)INS_RIGHT_PARALLEL ],
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size, right_nops);
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(*d10v_callback->printf_filtered) (d10v_callback,
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"executed %*ld long instructions\n",
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size, ins_type_counters[ (int)INS_LONG ]);
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(*d10v_callback->printf_filtered) (d10v_callback,
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"executed %*ld total instructions\n",
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size, total);
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}
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void
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@ -385,7 +442,10 @@ sim_create_inferior (start_address, argv, env)
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char **argv;
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char **env;
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{
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printf ("sim_create_inferior: PC=0x%x\n",start_address);
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#ifdef DEBUG
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if (d10v_debug)
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%x\n", start_address);
|
||||
#endif
|
||||
PC = start_address >> 2;
|
||||
}
|
||||
|
||||
|
@ -409,7 +469,7 @@ sim_stop_reason (reason, sigrc)
|
|||
enum sim_stop *reason;
|
||||
int *sigrc;
|
||||
{
|
||||
/* printf ("sim_stop_reason: PC=0x%x\n",PC<<2); */
|
||||
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
|
||||
|
||||
if (State.exception == SIGQUIT)
|
||||
{
|
||||
|
@ -431,12 +491,12 @@ sim_fetch_register (rn, memory)
|
|||
if (rn > 31)
|
||||
{
|
||||
WRITE_64 (memory, State.a[rn-32]);
|
||||
/* printf ("sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
|
||||
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_16 (memory, State.regs[rn]);
|
||||
/* printf ("sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
|
||||
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -448,12 +508,12 @@ sim_store_register (rn, memory)
|
|||
if (rn > 31)
|
||||
{
|
||||
State.a[rn-32] = READ_64 (memory) & MASK40;
|
||||
/* printf ("store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
|
||||
/* (*d10v_callback->printf_filtered) (d10v_callback, "store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
|
||||
}
|
||||
else
|
||||
{
|
||||
State.regs[rn]= READ_16 (memory);
|
||||
/* printf ("store: r%d=0x%x\n",rn,State.regs[rn]); */
|
||||
/* (*d10v_callback->printf_filtered) (d10v_callback, "store: r%d=0x%x\n",rn,State.regs[rn]); */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -474,7 +534,7 @@ void
|
|||
sim_do_command (cmd)
|
||||
char *cmd;
|
||||
{
|
||||
printf("sim_do_command: %s\n",cmd);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
|
||||
}
|
||||
|
||||
int
|
||||
|
|
|
@ -31,7 +31,7 @@ enum op_types {
|
|||
OP_PREDEC
|
||||
};
|
||||
|
||||
#if (DEBUG & DEBUG_TRACE) != 0
|
||||
#ifdef DEBUG
|
||||
static void trace_input PARAMS ((char *name,
|
||||
enum op_types in1,
|
||||
enum op_types in2,
|
||||
|
@ -66,6 +66,9 @@ trace_input (name, in1, in2, in3)
|
|||
long tmp;
|
||||
char *type;
|
||||
|
||||
if ((d10v_debug & DEBUG_TRACE) == 0)
|
||||
return;
|
||||
|
||||
switch (State.ins_type)
|
||||
{
|
||||
default:
|
||||
|
@ -77,7 +80,10 @@ trace_input (name, in1, in2, in3)
|
|||
case INS_LONG: type = " B"; break;
|
||||
}
|
||||
|
||||
printf ("0x%.6x %s: %-*s", (unsigned)PC, type, SIZE_INSTRUCTION, name);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback,
|
||||
"0x%.6x %s: %-*s",
|
||||
(unsigned)PC, type,
|
||||
SIZE_INSTRUCTION, name);
|
||||
|
||||
in[0] = in1;
|
||||
in[1] = in2;
|
||||
|
@ -180,150 +186,164 @@ trace_input (name, in1, in2, in3)
|
|||
}
|
||||
}
|
||||
|
||||
#if (DEBUG & DEBUG_VALUES) == 0
|
||||
*p++ = '\n';
|
||||
*p = '\0';
|
||||
fputs (buf, stdout);
|
||||
|
||||
#else /* DEBUG_VALUES */
|
||||
*p = '\0';
|
||||
printf ("%-*s", SIZE_OPERANDS, buf);
|
||||
|
||||
p = buf;
|
||||
for (i = 0; i < 3; i++)
|
||||
if ((d10v_debug & DEBUG_VALUES) == 0)
|
||||
{
|
||||
buf[0] = '\0';
|
||||
switch (in[i])
|
||||
*p++ = '\n';
|
||||
*p = '\0';
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
*p = '\0';
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
|
||||
|
||||
p = buf;
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
case OP_VOID:
|
||||
printf ("%*s", SIZE_VALUES, "");
|
||||
break;
|
||||
buf[0] = '\0';
|
||||
switch (in[i])
|
||||
{
|
||||
case OP_VOID:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
|
||||
break;
|
||||
|
||||
case OP_REG_OUTPUT:
|
||||
case OP_DREG_OUTPUT:
|
||||
case OP_CR_OUTPUT:
|
||||
case OP_ACCUM_OUTPUT:
|
||||
printf ("%*s", SIZE_VALUES, "---");
|
||||
break;
|
||||
case OP_REG_OUTPUT:
|
||||
case OP_DREG_OUTPUT:
|
||||
case OP_CR_OUTPUT:
|
||||
case OP_ACCUM_OUTPUT:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
|
||||
break;
|
||||
|
||||
case OP_REG:
|
||||
case OP_MEMREF:
|
||||
case OP_POSTDEC:
|
||||
case OP_POSTINC:
|
||||
case OP_PREDEC:
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[i]]);
|
||||
break;
|
||||
case OP_REG:
|
||||
case OP_MEMREF:
|
||||
case OP_POSTDEC:
|
||||
case OP_POSTINC:
|
||||
case OP_PREDEC:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)State.regs[OP[i]]);
|
||||
break;
|
||||
|
||||
case OP_DREG:
|
||||
tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
|
||||
printf ("%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
|
||||
break;
|
||||
case OP_DREG:
|
||||
tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
|
||||
break;
|
||||
|
||||
case OP_CR:
|
||||
case OP_CR_REVERSE:
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.cregs[OP[i]]);
|
||||
break;
|
||||
case OP_CR:
|
||||
case OP_CR_REVERSE:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)State.cregs[OP[i]]);
|
||||
break;
|
||||
|
||||
case OP_ACCUM:
|
||||
case OP_ACCUM_REVERSE:
|
||||
printf ("%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
|
||||
((int)(State.a[OP[i]] >> 32) & 0xff),
|
||||
((unsigned long)State.a[OP[i]]) & 0xffffffff);
|
||||
break;
|
||||
case OP_ACCUM:
|
||||
case OP_ACCUM_REVERSE:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
|
||||
((int)(State.a[OP[i]] >> 32) & 0xff),
|
||||
((unsigned long)State.a[OP[i]]) & 0xffffffff);
|
||||
break;
|
||||
|
||||
case OP_CONSTANT16:
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
|
||||
break;
|
||||
case OP_CONSTANT16:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)OP[i]);
|
||||
break;
|
||||
|
||||
case OP_CONSTANT4:
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT4(OP[i]));
|
||||
break;
|
||||
case OP_CONSTANT4:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)SEXT4(OP[i]));
|
||||
break;
|
||||
|
||||
case OP_CONSTANT3:
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT3(OP[i]));
|
||||
break;
|
||||
case OP_CONSTANT3:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)SEXT3(OP[i]));
|
||||
break;
|
||||
|
||||
case OP_FLAG:
|
||||
if (OP[i] == 0)
|
||||
printf ("%*sF0 = %d", SIZE_VALUES-6, "", State.F0 != 0);
|
||||
case OP_FLAG:
|
||||
if (OP[i] == 0)
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
|
||||
State.F0 != 0);
|
||||
|
||||
else if (OP[i] == 1)
|
||||
printf ("%*sF1 = %d", SIZE_VALUES-6, "", State.F1 != 0);
|
||||
else if (OP[i] == 1)
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
|
||||
State.F1 != 0);
|
||||
|
||||
else
|
||||
printf ("%*sC = %d", SIZE_VALUES-5, "", State.C != 0);
|
||||
else
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
|
||||
State.C != 0);
|
||||
|
||||
break;
|
||||
break;
|
||||
|
||||
case OP_MEMREF2:
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
|
||||
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[++i]]);
|
||||
break;
|
||||
case OP_MEMREF2:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)OP[i]);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
|
||||
(uint16)State.regs[OP[++i]]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
trace_output (result)
|
||||
enum op_types result;
|
||||
{
|
||||
#if (DEBUG & DEBUG_VALUES) != 0
|
||||
long tmp;
|
||||
|
||||
switch (result)
|
||||
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
|
||||
{
|
||||
default:
|
||||
putchar ('\n');
|
||||
break;
|
||||
long tmp;
|
||||
|
||||
case OP_REG:
|
||||
case OP_REG_OUTPUT:
|
||||
printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.regs[OP[0]],
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
switch (result)
|
||||
{
|
||||
default:
|
||||
putchar ('\n');
|
||||
break;
|
||||
|
||||
case OP_DREG:
|
||||
case OP_DREG_OUTPUT:
|
||||
tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
|
||||
printf (" :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
case OP_REG:
|
||||
case OP_REG_OUTPUT:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
|
||||
(uint16)State.regs[OP[0]],
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
|
||||
case OP_CR:
|
||||
case OP_CR_OUTPUT:
|
||||
printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[0]],
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
case OP_DREG:
|
||||
case OP_DREG_OUTPUT:
|
||||
tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
|
||||
case OP_CR_REVERSE:
|
||||
printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[1]],
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
case OP_CR:
|
||||
case OP_CR_OUTPUT:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
|
||||
(uint16)State.cregs[OP[0]],
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
|
||||
case OP_ACCUM:
|
||||
case OP_ACCUM_OUTPUT:
|
||||
printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
|
||||
((int)(State.a[OP[0]] >> 32) & 0xff),
|
||||
((unsigned long)State.a[OP[0]]) & 0xffffffff,
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
case OP_CR_REVERSE:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
|
||||
(uint16)State.cregs[OP[1]],
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
|
||||
case OP_ACCUM_REVERSE:
|
||||
printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
|
||||
((int)(State.a[OP[1]] >> 32) & 0xff),
|
||||
((unsigned long)State.a[OP[1]]) & 0xffffffff,
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
case OP_ACCUM:
|
||||
case OP_ACCUM_OUTPUT:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
|
||||
((int)(State.a[OP[0]] >> 32) & 0xff),
|
||||
((unsigned long)State.a[OP[0]]) & 0xffffffff,
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
|
||||
case OP_FLAG:
|
||||
printf (" :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
case OP_ACCUM_REVERSE:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
|
||||
((int)(State.a[OP[1]] >> 32) & 0xff),
|
||||
((unsigned long)State.a[OP[1]]) & 0xffffffff,
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
|
||||
case OP_FLAG:
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
|
||||
State.F0 != 0, State.F1 != 0, State.C != 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
fflush (stdout);
|
||||
#endif
|
||||
}
|
||||
|
||||
#else
|
||||
|
@ -836,7 +856,7 @@ OP_4E09 ()
|
|||
void
|
||||
OP_5F20 ()
|
||||
{
|
||||
printf("***** DBT ***** PC=%x\n",PC);
|
||||
d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
|
||||
State.exception = SIGTRAP;
|
||||
}
|
||||
|
||||
|
@ -1601,7 +1621,9 @@ OP_5600 ()
|
|||
State.C = PSW & 1;
|
||||
if (State.ST && !State.FX)
|
||||
{
|
||||
fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback,
|
||||
"ERROR at PC 0x%x: ST can only be set when FX is set.\n",
|
||||
PC<<2);
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
}
|
||||
|
@ -1655,6 +1677,11 @@ OP_5E00 ()
|
|||
{
|
||||
trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
|
||||
trace_output (OP_VOID);
|
||||
|
||||
if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
|
||||
left_nops++;
|
||||
else
|
||||
right_nops++;
|
||||
}
|
||||
|
||||
/* not */
|
||||
|
@ -1694,7 +1721,9 @@ OP_5201 ()
|
|||
trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
|
||||
if (OP[1] != 0)
|
||||
{
|
||||
fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback,
|
||||
"ERROR at PC 0x%x: instruction only valid for A0\n",
|
||||
PC<<2);
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
|
||||
|
@ -1769,12 +1798,12 @@ OP_27000000 ()
|
|||
State.RP = 1;
|
||||
if (RPT_C == 0)
|
||||
{
|
||||
fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
if (OP[1] < 4)
|
||||
{
|
||||
fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
trace_output (OP_VOID);
|
||||
|
@ -1791,12 +1820,12 @@ OP_2F000000 ()
|
|||
State.RP = 1;
|
||||
if (RPT_C == 0)
|
||||
{
|
||||
fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
if (OP[1] < 4)
|
||||
{
|
||||
fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
trace_output (OP_VOID);
|
||||
|
@ -1806,7 +1835,7 @@ OP_2F000000 ()
|
|||
void
|
||||
OP_5F60 ()
|
||||
{
|
||||
fprintf(stderr, "ERROR: rtd - NOT IMPLEMENTED\n");
|
||||
d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
|
||||
State.exception = SIGILL;
|
||||
}
|
||||
|
||||
|
@ -2064,7 +2093,7 @@ OP_6C1F ()
|
|||
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
|
||||
if ( OP[1] != 15 )
|
||||
{
|
||||
fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
|
||||
State.exception = SIGILL;
|
||||
return;
|
||||
}
|
||||
|
@ -2120,7 +2149,7 @@ OP_6E1F ()
|
|||
trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
|
||||
if ( OP[1] != 15 )
|
||||
{
|
||||
fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
|
||||
State.exception = SIGILL;
|
||||
return;
|
||||
}
|
||||
|
@ -2367,7 +2396,7 @@ OP_5F00 ()
|
|||
switch (OP[0])
|
||||
{
|
||||
default:
|
||||
fprintf (stderr, "Unknown trap code %d\n", OP[0]);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
|
||||
State.exception = SIGILL;
|
||||
|
||||
case 0:
|
||||
|
@ -2542,7 +2571,10 @@ OP_5F00 ()
|
|||
/* Trap 2 calls printf */
|
||||
{
|
||||
char *fstr = State.regs[2] + State.imem;
|
||||
printf (fstr, (int16)State.regs[3], (int16)State.regs[4], (int16)State.regs[5]);
|
||||
(*d10v_callback->printf_filtered) (d10v_callback, fstr,
|
||||
(int16)State.regs[3],
|
||||
(int16)State.regs[4],
|
||||
(int16)State.regs[5]);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue