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More debug support; Enable -t/-v to work correctly; Add --enable-sim-cflags configure switch

This commit is contained in:
Michael Meissner 1996-09-04 17:42:51 +00:00
parent 10d183a0f0
commit 7eebfc6296
7 changed files with 1576 additions and 170 deletions
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32
sim/d10v/ChangeLog
View File

@ -5,17 +5,41 @@ Wed Sep 4 11:35:17 1996 Michael Meissner <meissner@tiktok.cygnus.com>
(_ins_type): New enumeration to specify which container an
instruction is in, and whether it is part of a parallel operation.
(_state): Add ins_type field.
* simops.c: Change all #ifdef DEBUG code so that the input and
output values can be traced, along with the instruction type.
({,u}int{8,16,32,64}): Use limits.h to size the appropriate types.
(ins_type_counters): Counters for the various instruction types.
({left,right}_nops): Counters for the number of nops in each
container.
(d10v_debug): New variable to indicate whether debugging is turned
on.
* simops.c: (all functions): Change all #ifdef DEBUG code so that
the input and output values can be traced, along with the
instruction type. Make the -t option enable tracing.
(all functions): Change printf calls to use the printf_filtered
function in the callback table.
* interp.c (_leftright): New enumeration to say whether 2 short
instructions are done left first or right first.
(do_{long,2_short,parallel}): Indicate in the machine state which
type of instruction this is.
type of instruction this is. Count each of the types of
instructions executed.
(sim_size): Only print the memory sizes if DEBUG_MEMSIZE debug
flag is set.
(sim_resume): Pass left/right indication to do_2_short.
(all functions): Change printf calls to use the printf_filtered
function in the callback table.
(sim_trace): Turn on debug flag if DEBUG was defined, and call
sim_resume.
(sim_info): Print out statistics on instructions.
(sim_{trace,create_inferior}): Eliminate extraneous output unless
debugging.
* Makefile.in: Make objects depend on d10v_sim.h.
({,SIM_}CFLAGS): Include configure dependent switches.
* configure.in (--enable-sim-cflags): New switch to allow user to
set the defaults.
* configure: Regenerate.
Wed Sep 04 04:45:34 1996 Mark Alexander <marka@cygnus.com>

19
sim/d10v/Makefile.in
View File

@ -1,5 +1,5 @@
# Makefile template for Configure for the SH sim library.
# Copyright (C) 1990, 1991, 1992, 1995 Free Software Foundation, Inc.
# Copyright (C) 1996 Free Software Foundation, Inc.
# Written by Cygnus Support.
#
# This program is free software; you can redistribute it and/or modify
@ -56,7 +56,8 @@ INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1
AR = @AR@
AR_FLAGS = rc
CC = @CC@
CFLAGS = @CFLAGS@ @DEFS@
SIM_CFLAGS = @sim_cflags@
CFLAGS = @CFLAGS@ @DEFS@ $(SIM_CFLAGS)
MAKEINFO = makeinfo
RANLIB = @RANLIB@
CC_FOR_BUILD = @CC_FOR_BUILD@
@ -67,14 +68,15 @@ TDEFINES =
.NOEXPORT:
MAKEOVERRIDES=
X=xstuff.o
XL=-lX11
#X=xstuff.o
#XL=-lX11
X=
XL=
INCLUDE = d10v_sim.h
INCDIR = $(srcdir)/../../include
CSEARCH = -I. -I$(srcdir) -I../../include \
-I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/sh
-I../../bfd -I$(INCDIR) -I$(srcdir)/../../bfd -I$(srcdir)/../../gdb -I$(srcdir)/../../newlib/libc/sys/d10v
DEP = mkdep
all: run libsim.a
@ -82,8 +84,9 @@ all: run libsim.a
run: interp.o $(X) run.o table.o callback.o simops.o
$(CC) $(CFLAGS) -o run $(X) interp.o table.o callback.o simops.o run.o ../../bfd/libbfd.a ../../libiberty/libiberty.a $(XL) -lm
interp.o:interp.c table.c
run.o:run.c
interp.o:interp.c table.c $(INCLUDE)
run.o:run.c $(INCLUDE)
simops.o:simops.c $(INCLUDE)
libsim.a:interp.o table.o simops.o
$(AR) $(ARFLAGS) libsim.a interp.o table.o simops.o
@ -95,7 +98,7 @@ simops.h: gencode
table.c: gencode simops.h
./gencode >$@
gencode: gencode.c ../../opcodes/libopcodes.a
gencode: gencode.c ../../opcodes/libopcodes.a $(INCLUDE)
$(CC) $(CFLAGS) $(HDEFINES) $(TDEFINES) $(CSEARCH) $(CSWITCHE) -o gencode $(srcdir)/gencode.c ../../opcodes/libopcodes.a -lc
.c.o:

1241
sim/d10v/configure vendored Executable file
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File diff suppressed because it is too large Load Diff

13
sim/d10v/configure.in
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@ -11,11 +11,24 @@ AC_C_BIGENDIAN
. ${srcdir}/../../bfd/configure.host
AC_ARG_ENABLE(sim-cflags,
[ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator],
[case "${enableval}" in
yes) sim_cflags="-O2";;
trace) sim_cflags="-O2 -DDEBUG=3";;
no) sim_cflags="";;
*) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
esac
if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
echo "Setting sim cflags = $sim_cflags" 6>&1
fi],[sim_cflags=""])dnl
AC_SUBST(CFLAGS)
AC_SUBST(HDEFINES)
AR=${AR-ar}
AC_SUBST(AR)
AC_PROG_RANLIB
AC_SUBST(sim_cflags)
# Put a plausible default for CC_FOR_BUILD in Makefile.
AC_C_CROSS

53
sim/d10v/d10v_sim.h
View File

@ -1,26 +1,55 @@
#include <stdio.h>
#include <ctype.h>
#include <limits.h>
#include "ansidecl.h"
#include "callback.h"
#include "opcode/d10v.h"
#define DEBUG_TRACE 0x00000001
#define DEBUG_VALUES 0x00000002
#define DEBUG_MEMSIZE 0x00000004
#define DEBUG_TRACE 0x00000001
#define DEBUG_VALUES 0x00000002
#define DEBUG_MEMSIZE 0x00000004
#define DEBUG_INSTRUCTION 0x00000008
#ifndef DEBUG
#define DEBUG 0
extern int d10v_debug;
#if UCHAR_MAX == 255
typedef unsigned char uint8;
typedef signed char int8;
#else
#error "Char is not an 8-bit type"
#endif
/* FIXME: host defines */
typedef unsigned char uint8;
#if SHRT_MAX == 32767
typedef unsigned short uint16;
typedef unsigned int uint32;
typedef signed char int8;
typedef signed short int16;
#else
#error "Short is not a 16-bit type"
#endif
#if INT_MAX == 2147483647
typedef unsigned int uint32;
typedef signed int int32;
#elif LONG_MAX == 2147483647
typedef unsigned long uint32;
typedef signed long int32;
#else
#error "Neither int nor long is a 32-bit type"
#endif
#if LONG_MAX > 2147483647
typedef unsigned long uint64;
typedef signed long int64;
#elif __GNUC__
typedef unsigned long long uint64;
typedef signed long long int64;
#else
#error "Can't find an appropriate 64-bit type"
#endif
/* FIXME: D10V defines */
typedef uint16 reg_t;
@ -44,9 +73,13 @@ enum _ins_type
INS_RIGHT,
INS_LEFT_PARALLEL,
INS_RIGHT_PARALLEL,
INS_LONG
INS_LONG,
INS_MAX
};
extern long ins_type_counters[ (int)INS_MAX ];
extern long left_nops, right_nops;
struct _state
{
reg_t regs[16]; /* general-purpose registers */

104
sim/d10v/interp.c
View File

@ -10,7 +10,10 @@
enum _leftright { LEFT_FIRST, RIGHT_FIRST };
int d10v_debug;
host_callback *d10v_callback;
long ins_type_counters[ (int)INS_MAX ];
long left_nops, right_nops;
uint16 OP[4];
@ -54,7 +57,7 @@ lookup_hash (ins, size)
{
if (h->next == NULL)
{
printf ("ERROR looking up hash for %x at PC %x\n",ins, PC);
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
exit(1);
}
h = h->next;
@ -145,10 +148,14 @@ do_long (ins)
uint32 ins;
{
struct hash_entry *h;
/* printf ("do_long %x\n",ins); */
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
(*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
#endif
h = lookup_hash (ins, 1);
get_operands (h->ops, ins);
State.ins_type = INS_LONG;
ins_type_counters[ (int)State.ins_type ]++;
(h->ops->func)();
}
static void
@ -157,14 +164,21 @@ do_2_short (ins1, ins2, leftright)
enum _leftright leftright;
{
struct hash_entry *h;
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
(*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
ins1, (leftright) ? "left" : "right", ins2);
#endif
/* printf ("do_2_short %x -> %x\n",ins1,ins2); */
h = lookup_hash (ins1, 0);
get_operands (h->ops, ins1);
State.ins_type = (leftright == LEFT_FIRST) ? INS_LEFT : INS_RIGHT;
ins_type_counters[ (int)State.ins_type ]++;
(h->ops->func)();
h = lookup_hash (ins2, 0);
get_operands (h->ops, ins2);
State.ins_type = (leftright == LEFT_FIRST) ? INS_RIGHT : INS_LEFT;
ins_type_counters[ (int)State.ins_type ]++;
(h->ops->func)();
}
static void
@ -172,7 +186,10 @@ do_parallel (ins1, ins2)
uint16 ins1, ins2;
{
struct hash_entry *h1, *h2;
/* printf ("do_parallel %x || %x\n",ins1,ins2); */
#ifdef DEBUG
if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
(*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
#endif
h1 = lookup_hash (ins1, 0);
h2 = lookup_hash (ins2, 0);
@ -180,6 +197,7 @@ do_parallel (ins1, ins2)
{
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT;
ins_type_counters[ (int)State.ins_type ]++;
(h1->ops->func)();
if (State.exe)
{
@ -192,6 +210,7 @@ do_parallel (ins1, ins2)
{
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT;
ins_type_counters[ (int)State.ins_type ]++;
(h2->ops->func)();
if (State.exe)
{
@ -204,9 +223,11 @@ do_parallel (ins1, ins2)
{
get_operands (h1->ops, ins1);
State.ins_type = INS_LEFT_PARALLEL;
ins_type_counters[ (int)State.ins_type ]++;
(h1->ops->func)();
get_operands (h2->ops, ins2);
State.ins_type = INS_RIGHT_PARALLEL;
ins_type_counters[ (int)State.ins_type ]++;
(h2->ops->func)();
}
}
@ -227,12 +248,16 @@ sim_size (power)
State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
if (!State.imem || !State.dmem )
{
fprintf (stderr,"Memory allocation failed.\n");
(*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
exit(1);
}
#if (DEBUG & DEBUG_MEMSIZE) != 0
printf ("Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE);
printf (" %d bytes data memory.\n",1<<DMEM_SIZE);
#ifdef DEBUG
if ((d10v_debug & DEBUG_MEMSIZE) != 0)
{
(*d10v_callback->printf_filtered) (d10v_callback, "Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE);
(*d10v_callback->printf_filtered) (d10v_callback, " %d bytes data memory.\n", 1<<DMEM_SIZE);
}
#endif
}
@ -252,7 +277,7 @@ sim_write (addr, buffer, size)
int i;
init_system ();
/* printf ("sim_write %d bytes to 0x%x\n",size,addr); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n",size,addr); */
for (i = 0; i < size; i++)
{
State.imem[i+addr] = buffer[i];
@ -267,7 +292,7 @@ sim_open (args)
struct simops *s;
struct hash_entry *h, *prev;
if (args != NULL)
printf ("sim_open %s\n",args);
(*d10v_callback->printf_filtered) (d10v_callback, "sim_open %s\n",args);
/* put all the opcodes in the hash table */
for (s = Simops; s->func; s++)
@ -301,14 +326,14 @@ void
sim_set_profile (n)
int n;
{
printf ("sim_set_profile %d\n",n);
(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
}
void
sim_set_profile_size (n)
int n;
{
printf ("sim_set_profile_size %d\n",n);
(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
}
void
@ -319,7 +344,7 @@ sim_resume (step, siggnal)
int i;
reg_t oldpc;
/* printf ("sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
if (step)
State.exception = SIGTRAP;
@ -368,15 +393,47 @@ sim_resume (step, siggnal)
int
sim_trace ()
{
printf ("sim_trace\n");
return 0;
#ifdef DEBUG
d10v_debug = DEBUG;
#endif
sim_resume (0, 0);
return 1;
}
void
sim_info (verbose)
int verbose;
{
printf ("sim_info\n");
char buf[40];
int size;
long total = (ins_type_counters[ (int)INS_LONG ]
+ ins_type_counters[ (int)INS_LEFT ]
+ ins_type_counters[ (int)INS_LEFT_PARALLEL ]
+ ins_type_counters[ (int)INS_RIGHT ]
+ ins_type_counters[ (int)INS_RIGHT_PARALLEL ]);
sprintf (buf, "%ld", total);
size = strlen (buf);
(*d10v_callback->printf_filtered) (d10v_callback,
"executed %*ld instructions in the left container, %*ld parallel, %*ld nops\n",
size, ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_PARALLEL ],
size, ins_type_counters[ (int)INS_LEFT_PARALLEL ],
size, left_nops);
(*d10v_callback->printf_filtered) (d10v_callback,
"executed %*ld instructions in the right container, %*ld parallel, %*ld nops\n",
size, ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_PARALLEL ],
size, ins_type_counters[ (int)INS_RIGHT_PARALLEL ],
size, right_nops);
(*d10v_callback->printf_filtered) (d10v_callback,
"executed %*ld long instructions\n",
size, ins_type_counters[ (int)INS_LONG ]);
(*d10v_callback->printf_filtered) (d10v_callback,
"executed %*ld total instructions\n",
size, total);
}
void
@ -385,7 +442,10 @@ sim_create_inferior (start_address, argv, env)
char **argv;
char **env;
{
printf ("sim_create_inferior: PC=0x%x\n",start_address);
#ifdef DEBUG
if (d10v_debug)
(*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%x\n", start_address);
#endif
PC = start_address >> 2;
}
@ -409,7 +469,7 @@ sim_stop_reason (reason, sigrc)
enum sim_stop *reason;
int *sigrc;
{
/* printf ("sim_stop_reason: PC=0x%x\n",PC<<2); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
if (State.exception == SIGQUIT)
{
@ -431,12 +491,12 @@ sim_fetch_register (rn, memory)
if (rn > 31)
{
WRITE_64 (memory, State.a[rn-32]);
/* printf ("sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_fetch_register %d 0x%llx\n",rn,State.a[rn-32]); */
}
else
{
WRITE_16 (memory, State.regs[rn]);
/* printf ("sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_fetch_register %d 0x%x\n",rn,State.regs[rn]); */
}
}
@ -448,12 +508,12 @@ sim_store_register (rn, memory)
if (rn > 31)
{
State.a[rn-32] = READ_64 (memory) & MASK40;
/* printf ("store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "store: a%d=0x%llx\n",rn-32,State.a[rn-32]); */
}
else
{
State.regs[rn]= READ_16 (memory);
/* printf ("store: r%d=0x%x\n",rn,State.regs[rn]); */
/* (*d10v_callback->printf_filtered) (d10v_callback, "store: r%d=0x%x\n",rn,State.regs[rn]); */
}
}
@ -474,7 +534,7 @@ void
sim_do_command (cmd)
char *cmd;
{
printf("sim_do_command: %s\n",cmd);
(*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
}
int

284
sim/d10v/simops.c
View File

@ -31,7 +31,7 @@ enum op_types {
OP_PREDEC
};
#if (DEBUG & DEBUG_TRACE) != 0
#ifdef DEBUG
static void trace_input PARAMS ((char *name,
enum op_types in1,
enum op_types in2,
@ -66,6 +66,9 @@ trace_input (name, in1, in2, in3)
long tmp;
char *type;
if ((d10v_debug & DEBUG_TRACE) == 0)
return;
switch (State.ins_type)
{
default:
@ -77,7 +80,10 @@ trace_input (name, in1, in2, in3)
case INS_LONG: type = " B"; break;
}
printf ("0x%.6x %s: %-*s", (unsigned)PC, type, SIZE_INSTRUCTION, name);
(*d10v_callback->printf_filtered) (d10v_callback,
"0x%.6x %s: %-*s",
(unsigned)PC, type,
SIZE_INSTRUCTION, name);
in[0] = in1;
in[1] = in2;
@ -180,150 +186,164 @@ trace_input (name, in1, in2, in3)
}
}
#if (DEBUG & DEBUG_VALUES) == 0
*p++ = '\n';
*p = '\0';
fputs (buf, stdout);
#else /* DEBUG_VALUES */
*p = '\0';
printf ("%-*s", SIZE_OPERANDS, buf);
p = buf;
for (i = 0; i < 3; i++)
if ((d10v_debug & DEBUG_VALUES) == 0)
{
buf[0] = '\0';
switch (in[i])
*p++ = '\n';
*p = '\0';
(*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
}
else
{
*p = '\0';
(*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
p = buf;
for (i = 0; i < 3; i++)
{
case OP_VOID:
printf ("%*s", SIZE_VALUES, "");
break;
buf[0] = '\0';
switch (in[i])
{
case OP_VOID:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
break;
case OP_REG_OUTPUT:
case OP_DREG_OUTPUT:
case OP_CR_OUTPUT:
case OP_ACCUM_OUTPUT:
printf ("%*s", SIZE_VALUES, "---");
break;
case OP_REG_OUTPUT:
case OP_DREG_OUTPUT:
case OP_CR_OUTPUT:
case OP_ACCUM_OUTPUT:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
break;
case OP_REG:
case OP_MEMREF:
case OP_POSTDEC:
case OP_POSTINC:
case OP_PREDEC:
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[i]]);
break;
case OP_REG:
case OP_MEMREF:
case OP_POSTDEC:
case OP_POSTINC:
case OP_PREDEC:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)State.regs[OP[i]]);
break;
case OP_DREG:
tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
printf ("%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_DREG:
tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_CR:
case OP_CR_REVERSE:
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.cregs[OP[i]]);
break;
case OP_CR:
case OP_CR_REVERSE:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)State.cregs[OP[i]]);
break;
case OP_ACCUM:
case OP_ACCUM_REVERSE:
printf ("%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
((int)(State.a[OP[i]] >> 32) & 0xff),
((unsigned long)State.a[OP[i]]) & 0xffffffff);
break;
case OP_ACCUM:
case OP_ACCUM_REVERSE:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
((int)(State.a[OP[i]] >> 32) & 0xff),
((unsigned long)State.a[OP[i]]) & 0xffffffff);
break;
case OP_CONSTANT16:
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
break;
case OP_CONSTANT16:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
break;
case OP_CONSTANT4:
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT4(OP[i]));
break;
case OP_CONSTANT4:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT4(OP[i]));
break;
case OP_CONSTANT3:
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT3(OP[i]));
break;
case OP_CONSTANT3:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT3(OP[i]));
break;
case OP_FLAG:
if (OP[i] == 0)
printf ("%*sF0 = %d", SIZE_VALUES-6, "", State.F0 != 0);
case OP_FLAG:
if (OP[i] == 0)
(*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
State.F0 != 0);
else if (OP[i] == 1)
printf ("%*sF1 = %d", SIZE_VALUES-6, "", State.F1 != 0);
else if (OP[i] == 1)
(*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
State.F1 != 0);
else
printf ("%*sC = %d", SIZE_VALUES-5, "", State.C != 0);
else
(*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
State.C != 0);
break;
break;
case OP_MEMREF2:
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]);
printf ("%*s0x%.4x", SIZE_VALUES-6, "", (uint16)State.regs[OP[++i]]);
break;
case OP_MEMREF2:
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
(*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)State.regs[OP[++i]]);
break;
}
}
}
#endif
}
static void
trace_output (result)
enum op_types result;
{
#if (DEBUG & DEBUG_VALUES) != 0
long tmp;
switch (result)
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
default:
putchar ('\n');
break;
long tmp;
case OP_REG:
case OP_REG_OUTPUT:
printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.regs[OP[0]],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
switch (result)
{
default:
putchar ('\n');
break;
case OP_DREG:
case OP_DREG_OUTPUT:
tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
printf (" :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_REG:
case OP_REG_OUTPUT:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
(uint16)State.regs[OP[0]],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_CR:
case OP_CR_OUTPUT:
printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[0]],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_DREG:
case OP_DREG_OUTPUT:
tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_CR_REVERSE:
printf (" :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", (uint16)State.cregs[OP[1]],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_CR:
case OP_CR_OUTPUT:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
(uint16)State.cregs[OP[0]],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_ACCUM:
case OP_ACCUM_OUTPUT:
printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
((int)(State.a[OP[0]] >> 32) & 0xff),
((unsigned long)State.a[OP[0]]) & 0xffffffff,
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_CR_REVERSE:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
(uint16)State.cregs[OP[1]],
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_ACCUM_REVERSE:
printf (" :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
((int)(State.a[OP[1]] >> 32) & 0xff),
((unsigned long)State.a[OP[1]]) & 0xffffffff,
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_ACCUM:
case OP_ACCUM_OUTPUT:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
((int)(State.a[OP[0]] >> 32) & 0xff),
((unsigned long)State.a[OP[0]]) & 0xffffffff,
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_FLAG:
printf (" :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_ACCUM_REVERSE:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
((int)(State.a[OP[1]] >> 32) & 0xff),
((unsigned long)State.a[OP[1]]) & 0xffffffff,
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
case OP_FLAG:
(*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
State.F0 != 0, State.F1 != 0, State.C != 0);
break;
}
}
fflush (stdout);
#endif
}
#else
@ -836,7 +856,7 @@ OP_4E09 ()
void
OP_5F20 ()
{
printf("***** DBT ***** PC=%x\n",PC);
d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
State.exception = SIGTRAP;
}
@ -1601,7 +1621,9 @@ OP_5600 ()
State.C = PSW & 1;
if (State.ST && !State.FX)
{
fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
(*d10v_callback->printf_filtered) (d10v_callback,
"ERROR at PC 0x%x: ST can only be set when FX is set.\n",
PC<<2);
State.exception = SIGILL;
}
}
@ -1655,6 +1677,11 @@ OP_5E00 ()
{
trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
trace_output (OP_VOID);
if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
left_nops++;
else
right_nops++;
}
/* not */
@ -1694,7 +1721,9 @@ OP_5201 ()
trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
if (OP[1] != 0)
{
fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
(*d10v_callback->printf_filtered) (d10v_callback,
"ERROR at PC 0x%x: instruction only valid for A0\n",
PC<<2);
State.exception = SIGILL;
}
@ -1769,12 +1798,12 @@ OP_27000000 ()
State.RP = 1;
if (RPT_C == 0)
{
fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
State.exception = SIGILL;
}
if (OP[1] < 4)
{
fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
State.exception = SIGILL;
}
trace_output (OP_VOID);
@ -1791,12 +1820,12 @@ OP_2F000000 ()
State.RP = 1;
if (RPT_C == 0)
{
fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
State.exception = SIGILL;
}
if (OP[1] < 4)
{
fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
State.exception = SIGILL;
}
trace_output (OP_VOID);
@ -1806,7 +1835,7 @@ OP_2F000000 ()
void
OP_5F60 ()
{
fprintf(stderr, "ERROR: rtd - NOT IMPLEMENTED\n");
d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
State.exception = SIGILL;
}
@ -2064,7 +2093,7 @@ OP_6C1F ()
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
State.exception = SIGILL;
return;
}
@ -2120,7 +2149,7 @@ OP_6E1F ()
trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
State.exception = SIGILL;
return;
}
@ -2367,7 +2396,7 @@ OP_5F00 ()
switch (OP[0])
{
default:
fprintf (stderr, "Unknown trap code %d\n", OP[0]);
(*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
State.exception = SIGILL;
case 0:
@ -2542,7 +2571,10 @@ OP_5F00 ()
/* Trap 2 calls printf */
{
char *fstr = State.regs[2] + State.imem;
printf (fstr, (int16)State.regs[3], (int16)State.regs[4], (int16)State.regs[5]);
(*d10v_callback->printf_filtered) (d10v_callback, fstr,
(int16)State.regs[3],
(int16)State.regs[4],
(int16)State.regs[5]);
break;
}