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sim: mcore: pull cpu state out of global scope 

This avoids using global variables to hold the cpu state so we can
better integrate with the sim common code.

There's also a minor fix here where we move the pc register back into
the state that is accessible by the asints array.  When it was pulled
out previously, the reg store/fetch functions broke, but no one really
noticed as the mcore gdb port was dropped a while back.
This commit is contained in:
Mike Frysinger 2015-11-15 00:42:33 -08:00
parent 9ef4651c49
commit 7eed1055b8
3 changed files with 308 additions and 293 deletions
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28
sim/mcore/ChangeLog
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@ -1,3 +1,31 @@
2015-11-15 Mike Frysinger <vapier@gentoo.org>
* interp.c (mcore_regset, LAST_VALID_CREG, NUM_MCORE_REGS: Move
to sim-main.h.
(cpu): Delete.
(gr, cr): Change from asregs to cpu.
(sr, vbr, esr, fsr, epc, fpc, ss0, ss1, ss2, ss3, ss4, gcr, gsr):
Change from asregs to cr.
(C_ON, C_VALUE, C_OFF, SET_C, CLR_C, NEW_C, SR_AF): Change from
cpu.sr to sr.
(set_active_regs): Define.
(set_initial_gprs): Rename scpu to cpu. Change cpu.sr to sr and
cpu.gr to gr. Replace for loop with memset. Replace SR_AF with
set_active_regs.
(handle_trap1): Add cpu arg.
(process_stub): Likewise. Change cpu.gr to gr.
(util): Rename scpu to cpu. Change cpu.gr to gr.
(rbat, rhat, rlat, wbat, what, wlat, ILLEGAL, sim_engine_run,
mcore_reg_store, mcore_reg_fetch, sim_create_inferior): Rename scpu
to cpu.
(step_once): Likewise. Replace SR_AF with set_active_regs. Adjust
cpu.asregs to cpu.
(mcore_pc_get, mcore_pc_set): Adjust cpu->pc to cpu->regs.pc.
* sim-main.h (mcore_regset, LAST_VALID_CREG, NUM_MCORE_REGS: Move
from interp.c.
(_sim_cpu): Add regs, asints, active_gregs, ticks, stalls, cycles,
and insts members.
2015-11-15 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (SIM_OBJS): Add sim-reg.o.

537
sim/mcore/interp.c
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File diff suppressed because it is too large Load Diff

36
sim/mcore/sim-main.h
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@ -27,9 +27,43 @@ typedef unsigned long int uword;
#include "sim-base.h"
#include "bfd.h"
/* The machine state.
This state is maintained in host byte order. The
fetch/store register functions must translate between host
byte order and the target processor byte order.
Keeping this data in target byte order simplifies the register
read/write functions. Keeping this data in native order improves
the performance of the simulator. Simulation speed is deemed more
important. */
/* The ordering of the mcore_regset structure is matched in the
gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
struct mcore_regset
{
word gregs[16]; /* primary registers */
word alt_gregs[16]; /* alt register file */
word cregs[32]; /* control registers */
word pc;
};
#define LAST_VALID_CREG 32 /* only 0..12 implemented */
#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
struct _sim_cpu {
word pc;
union
{
struct mcore_regset regs;
/* Used by the fetch/store reg helpers to access registers linearly. */
word asints[NUM_MCORE_REGS];
};
/* Used to switch between gregs/alt_gregs based on the control state. */
word *active_gregs;
int ticks;
int stalls;
int cycles;
int insts;
sim_cpu_base base;
};