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IA-64 ELF support.

This commit is contained in:
Jim Wilson 2000-04-21 20:22:24 +00:00
parent c9637625e4
commit 800eeca487
110 changed files with 40578 additions and 1 deletions
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28
bfd/ChangeLog
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@ -1,3 +1,31 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@cygnus.com>
Jim Wilson <wilson@cygnus.com>
* Makefile.am (ALL_MACHINES): Add cpu-ia64.lo.
(ALL_MACHINES_CFILES): Add cpu-ia64.c.
(BFD64_BACKENDS): Add elf64-ia64.lo.
(BFD64_BACKENDS_CFILES): Add elf64-ia64.c.
(cpu-ia64.lo, elf64-ia64.lo): New rules.
* Makefile.in: Rebuild.
* archures.c (enum bfd_architecture): Add bfd_arch_ia64.
(bfd_ia64_arch): Declare.
(bfd_archures_list): Add bfd_ia64_arch.
* bfd-in2.h: Rebuild.
* config.bfd: (ia64*-*-linux-gnu*, ia64*-*-elf*): New targets.
* configure: Rebuild.
* configure.host: (ia64-*-linux*): New host.
* configure.in (bfd_elf64_ia64_little_vec, bfd_elf64_ia64_big_vec,
bfd_efi_app_ia64_vec, bfd_efi_app_ia64_vec): New vectors.
* elf.c (prep_headers): Add bfd_arch_ia64.
* libbfd.h: Rebuild.
* reloc.c: Add IA-64 relocations.
* targets.c (bfd_elf64_ia64_little_vec, bfd_elf64_ia64_big_vec):
Declare.
(bfd_target_vect): Add bfd_elf64_ia64_little_vec.
* cpu-ia64-opc.c, cpu-ia64.c, elf64-ia64.c: New files.
2000-04-21 Richard Henderson <rth@cygnus.com>
* elf32-d30v.c (bfd_elf_d30v_reloc): Don't modify section

9
bfd/Makefile.am
View File

@ -51,6 +51,7 @@ ALL_MACHINES = \
cpu-h8300.lo \
cpu-h8500.lo \
cpu-hppa.lo \
cpu-ia64.lo \
cpu-i370.lo \
cpu-i386.lo \
cpu-i860.lo \
@ -89,6 +90,7 @@ ALL_MACHINES_CFILES = \
cpu-h8300.c \
cpu-h8500.c \
cpu-hppa.c \
cpu-ia64.c \
cpu-i370.c \
cpu-i386.c \
cpu-i860.c \
@ -388,6 +390,7 @@ BFD64_BACKENDS = \
coff-ia64.lo \
demo64.lo \
elf64-alpha.lo \
elf64-ia64.lo \
elf64-gen.lo \
elf64-mips.lo \
elf64-sparc.lo \
@ -401,6 +404,7 @@ BFD64_BACKENDS_CFILES = \
coff-ia64.c \
demo64.c \
elf64-alpha.c \
elf64-ia64.c \
elf64-gen.c \
elf64-mips.c \
elf64-sparc.c \
@ -654,6 +658,11 @@ config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host
$(SHELL) ./config.status --recheck
cpu-ia64.lo: cpu-ia64.c cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h
elf64-ia64.lo: elf64-ia64.c elf-bfd.h $(INCDIR)/opcode/ia64.h \
$(INCDIR)/elf/ia64.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/reloc-macros.h \
elf64-target.h
elfarm-oabi.lo: elfarm-oabi.c elf32-arm.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h

9
bfd/Makefile.in
View File

@ -166,6 +166,7 @@ ALL_MACHINES = \
cpu-h8300.lo \
cpu-h8500.lo \
cpu-hppa.lo \
cpu-ia64.lo \
cpu-i370.lo \
cpu-i386.lo \
cpu-i860.lo \
@ -205,6 +206,7 @@ ALL_MACHINES_CFILES = \
cpu-h8300.c \
cpu-h8500.c \
cpu-hppa.c \
cpu-ia64.c \
cpu-i370.c \
cpu-i386.c \
cpu-i860.c \
@ -507,6 +509,7 @@ BFD64_BACKENDS = \
coff-ia64.lo \
demo64.lo \
elf64-alpha.lo \
elf64-ia64.lo \
elf64-gen.lo \
elf64-mips.lo \
elf64-sparc.lo \
@ -521,6 +524,7 @@ BFD64_BACKENDS_CFILES = \
coff-ia64.c \
demo64.c \
elf64-alpha.c \
elf64-ia64.c \
elf64-gen.c \
elf64-mips.c \
elf64-sparc.c \
@ -1182,6 +1186,11 @@ stmp-lcoff-h: $(LIBCOFF_H_FILES)
config.status: $(srcdir)/configure $(srcdir)/config.bfd $(srcdir)/configure.host
$(SHELL) ./config.status --recheck
cpu-ia64.lo: cpu-ia64.c cpu-ia64-opc.c $(srcdir)/../opcodes/ia64-opc.h
elf64-ia64.lo: elf64-ia64.c elf-bfd.h $(INCDIR)/opcode/ia64.h \
$(INCDIR)/elf/ia64.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
$(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/reloc-macros.h \
elf64-target.h
elfarm-oabi.lo: elfarm-oabi.c elf32-arm.h elf-bfd.h $(INCDIR)/elf/common.h \
$(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
$(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h elf32-target.h

3
bfd/archures.c
View File

@ -199,6 +199,7 @@ DESCRIPTION
. bfd_arch_fr30,
.#define bfd_mach_fr30 0x46523330
. bfd_arch_mcore,
. bfd_arch_ia64, {* HP/Intel ia64 *}
. bfd_arch_pj,
. bfd_arch_avr, {* Atmel AVR microcontrollers *}
.#define bfd_mach_avr1 1
@ -279,6 +280,7 @@ extern const bfd_arch_info_type bfd_v850_arch;
extern const bfd_arch_info_type bfd_fr30_arch;
extern const bfd_arch_info_type bfd_mcore_arch;
extern const bfd_arch_info_type bfd_avr_arch;
extern const bfd_arch_info_type bfd_ia64_arch;
static const bfd_arch_info_type * const bfd_archures_list[] =
{
@ -320,6 +322,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_fr30_arch,
&bfd_mcore_arch,
&bfd_avr_arch,
&bfd_ia64_arch,
#endif
0
};

66
bfd/bfd-in2.h
View File

@ -1432,6 +1432,7 @@ enum bfd_architecture
bfd_arch_fr30,
#define bfd_mach_fr30 0x46523330
bfd_arch_mcore,
bfd_arch_ia64, /* HP/Intel ia64 */
bfd_arch_pj,
bfd_arch_avr, /* Atmel AVR microcontrollers */
#define bfd_mach_avr1 1
@ -2448,6 +2449,71 @@ is stored in the reloc's addend. For Rel hosts, we are forced to put
this offset in the reloc's section offset. */
BFD_RELOC_VTABLE_INHERIT,
BFD_RELOC_VTABLE_ENTRY,
/* Intel IA64 Relocations. */
BFD_RELOC_IA64_IMM14,
BFD_RELOC_IA64_IMM22,
BFD_RELOC_IA64_IMM64,
BFD_RELOC_IA64_DIR32MSB,
BFD_RELOC_IA64_DIR32LSB,
BFD_RELOC_IA64_DIR64MSB,
BFD_RELOC_IA64_DIR64LSB,
BFD_RELOC_IA64_GPREL22,
BFD_RELOC_IA64_GPREL64I,
BFD_RELOC_IA64_GPREL32MSB,
BFD_RELOC_IA64_GPREL32LSB,
BFD_RELOC_IA64_GPREL64MSB,
BFD_RELOC_IA64_GPREL64LSB,
BFD_RELOC_IA64_LTOFF22,
BFD_RELOC_IA64_LTOFF64I,
BFD_RELOC_IA64_PLTOFF22,
BFD_RELOC_IA64_PLTOFF64I,
BFD_RELOC_IA64_PLTOFF64MSB,
BFD_RELOC_IA64_PLTOFF64LSB,
BFD_RELOC_IA64_FPTR64I,
BFD_RELOC_IA64_FPTR32MSB,
BFD_RELOC_IA64_FPTR32LSB,
BFD_RELOC_IA64_FPTR64MSB,
BFD_RELOC_IA64_FPTR64LSB,
BFD_RELOC_IA64_PCREL21B,
BFD_RELOC_IA64_PCREL21M,
BFD_RELOC_IA64_PCREL21F,
BFD_RELOC_IA64_PCREL32MSB,
BFD_RELOC_IA64_PCREL32LSB,
BFD_RELOC_IA64_PCREL64MSB,
BFD_RELOC_IA64_PCREL64LSB,
BFD_RELOC_IA64_LTOFF_FPTR22,
BFD_RELOC_IA64_LTOFF_FPTR64I,
BFD_RELOC_IA64_LTOFF_FPTR64MSB,
BFD_RELOC_IA64_LTOFF_FPTR64LSB,
BFD_RELOC_IA64_SEGBASE,
BFD_RELOC_IA64_SEGREL32MSB,
BFD_RELOC_IA64_SEGREL32LSB,
BFD_RELOC_IA64_SEGREL64MSB,
BFD_RELOC_IA64_SEGREL64LSB,
BFD_RELOC_IA64_SECREL32MSB,
BFD_RELOC_IA64_SECREL32LSB,
BFD_RELOC_IA64_SECREL64MSB,
BFD_RELOC_IA64_SECREL64LSB,
BFD_RELOC_IA64_REL32MSB,
BFD_RELOC_IA64_REL32LSB,
BFD_RELOC_IA64_REL64MSB,
BFD_RELOC_IA64_REL64LSB,
BFD_RELOC_IA64_LTV32MSB,
BFD_RELOC_IA64_LTV32LSB,
BFD_RELOC_IA64_LTV64MSB,
BFD_RELOC_IA64_LTV64LSB,
BFD_RELOC_IA64_IPLTMSB,
BFD_RELOC_IA64_IPLTLSB,
BFD_RELOC_IA64_EPLTMSB,
BFD_RELOC_IA64_EPLTLSB,
BFD_RELOC_IA64_COPY,
BFD_RELOC_IA64_TPREL22,
BFD_RELOC_IA64_TPREL64MSB,
BFD_RELOC_IA64_TPREL64LSB,
BFD_RELOC_IA64_LTOFF_TP22,
BFD_RELOC_IA64_LTOFF22X,
BFD_RELOC_IA64_LDXMOV,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *

4
bfd/config.bfd
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@ -80,6 +80,10 @@ case "${targ}" in
alpha*-*-*)
targ_defvec=ecoffalpha_little_vec
;;
ia64*-*-linux-gnu* | ia64*-*-elf*)
targ_defvec=bfd_elf64_ia64_little_vec
targ_selvecs="bfd_elf64_ia64_big_vec bfd_efi_app_ia64_vec"
;;
#endif /* BFD64 */
arc-*-elf*)

7
bfd/configure vendored
View File

@ -5112,6 +5112,13 @@ do
target64=true ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"
target64=true ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
target64=true ;;
bfd_elf64_ia64_big_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
target64=true ;;
bfd_efi_app_ia32_vec) tb="$tb efi-app-ia32.lo cofflink.lo" ;;
bfd_efi_app_ia64_vec) tb="$tb efi-app-ia64.lo cofflink.lo"
target64=true ;;
bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;

2
bfd/configure.host
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@ -27,6 +27,8 @@ hppa*-*-mpeix*) HDEFINES=-DHOST_HPPAMPEIX ;;
hppa*-*-bsd*) HDEFINES=-DHOST_HPPABSD ;;
hppa*-*-osf*) HDEFINES=-DHOST_HPPAOSF ;;
ia64-*-linux*) host64=true; HOST_64BIT_TYPE=long ;;
i[3456]86-sequent-bsd*) HDEFINES=-Dshared=genshared ;;
i[3456]86-sequent-sysv4*) ;;
i[3456]86-sequent-sysv*) HDEFINES=-Dshared=genshared ;;

7
bfd/configure.in
View File

@ -469,6 +469,13 @@ do
target64=true ;;
bfd_elf64_alpha_vec) tb="$tb elf64-alpha.lo elf64.lo $elf"
target64=true ;;
bfd_elf64_ia64_little_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
target64=true ;;
bfd_elf64_ia64_big_vec) tb="$tb elf64-ia64.lo elf64.lo $elf"
target64=true ;;
bfd_efi_app_ia32_vec) tb="$tb efi-app-ia32.lo cofflink.lo" ;;
bfd_efi_app_ia64_vec) tb="$tb efi-app-ia64.lo cofflink.lo"
target64=true ;;
bfd_elf32_avr_vec) tb="$tb elf32-avr.lo elf32.lo $elf" ;;
bfd_elf32_littlearc_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
bfd_elf32_littlearm_vec) tb="$tb elfarm-nabi.lo elf32.lo $elf" ;;

586
bfd/cpu-ia64-opc.c Normal file
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@ -0,0 +1,586 @@
/* Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* Logically, this code should be part of libopcode but since some of
the operand insertion/extraction functions help bfd to implement
relocations, this code is included as part of elf64-ia64.c. This
avoids circular dependencies between libopcode and libbfd and also
obviates the need for applications to link in libopcode when all
they really want is libbfd.
--davidm Mon Apr 13 22:14:02 1998 */
#include "../opcodes/ia64-opc.h"
#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
static const char*
ins_rsvd (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return "internal error---this shouldn't happen";
}
static const char*
ext_rsvd (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return "internal error---this shouldn't happen";
}
static const char*
ins_const (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return 0;
}
static const char*
ext_const (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return 0;
}
static const char*
ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value >= 1u << self->field[0].bits)
return "register number out of range";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift)
& ((1u << self->field[0].bits) - 1));
return 0;
}
static const char*
ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
ia64_insn new = 0;
int i;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
<< self->field[i].shift);
value >>= self->field[i].bits;
}
if (value)
return "integer operand out of range";
*code |= new;
return 0;
}
static const char*
ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
BFD_HOST_U_64_BIT value = 0;
int i, bits = 0, total = 0;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
bits = self->field[i].bits;
value |= ((code >> self->field[i].shift)
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
total += bits;
}
*valuep = value;
return 0;
}
static const char*
ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value & 0x7)
return "value not an integer multiple of 8";
return ins_immu (self, value >> 3, code);
}
static const char*
ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *result;
result = ext_immu (self, code, valuep);
if (result)
return result;
*valuep = *valuep << 3;
return 0;
}
static const char*
ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code, int scale)
{
BFD_HOST_64_BIT svalue = value, sign_bit;
ia64_insn new = 0;
int i;
svalue >>= scale;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
<< self->field[i].shift);
sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
svalue >>= self->field[i].bits;
}
if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
return "integer operand out of range";
*code |= new;
return 0;
}
static const char*
ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
ia64_insn *valuep, int scale)
{
int i, bits = 0, total = 0, shift;
BFD_HOST_64_BIT val = 0;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
bits = self->field[i].bits;
val |= ((code >> self->field[i].shift)
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
total += bits;
}
/* sign extend: */
shift = 8*sizeof (val) - total;
val = (val << shift) >> shift;
*valuep = (val << scale);
return 0;
}
static const char*
ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value == (BFD_HOST_U_64_BIT) 0x100000000)
value = 0;
else
value = (((BFD_HOST_64_BIT)value << 32) >> 32);
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 0);
}
static const char*
ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code)
{
if (value == (BFD_HOST_U_64_BIT) 0x100000000)
value = 0;
else
value = (((BFD_HOST_64_BIT)value << 32) >> 32);
--value;
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *res = ext_imms_scaled (self, code, valuep, 0);
++*valuep;
return res;
}
static const char*
ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 1);
}
static const char*
ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 1);
}
static const char*
ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 4);
}
static const char*
ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 4);
}
static const char*
ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 16);
}
static const char*
ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 16);
}
static const char*
ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
return ins_immu (self, value ^ mask, code);
}
static const char*
ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *result;
ia64_insn mask;
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
result = ext_immu (self, code, valuep);
if (!result)
{
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
*valuep ^= mask;
}
return result;
}
static const char*
ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
return "count out of range";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift)
& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
return 0;
}
static const char*
ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
if (value > 2)
return "count must be in range 1..3";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
return 0;
}
static const char*
ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
switch (value)
{
case 0: value = 0; break;
case 7: value = 1; break;
case 15: value = 2; break;
case 16: value = 3; break;
default: return "count must be 0, 7, 15, or 16";
}
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
ia64_insn value;
value = (code >> self->field[0].shift) & 0x3;
switch (value)
{
case 0: value = 0; break;
case 1: value = 7; break;
case 2: value = 15; break;
case 3: value = 16; break;
}
*valuep = value;
return 0;
}
static const char*
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
BFD_HOST_64_BIT val = value;
BFD_HOST_U_64_BIT sign = 0;
if (val < 0)
{
sign = 0x4;
value = -value;
}
switch (value)
{
case 1: value = 3; break;
case 4: value = 2; break;
case 8: value = 1; break;
case 16: value = 0; break;
default: return "count must be +/- 1, 4, 8, or 16";
}
*code |= (sign | value) << self->field[0].shift;
return 0;
}
static const char*
ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
BFD_HOST_64_BIT val;
int negate;
val = (code >> self->field[0].shift) & 0x7;
negate = val & 0x4;
switch (val & 0x3)
{
case 0: val = 16; break;
case 1: val = 8; break;
case 2: val = 4; break;
case 3: val = 1; break;
}
if (negate)
val = -val;
*valuep = val;
return 0;
}
#define CST IA64_OPND_CLASS_CST
#define REG IA64_OPND_CLASS_REG
#define IND IA64_OPND_CLASS_IND
#define ABS IA64_OPND_CLASS_ABS
#define REL IA64_OPND_CLASS_REL
#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
{
/* constants: */
{ CST, ins_const, ext_const, "NIL", {{ 0, }}, 0, "<none>" },
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, }}, 0, "ar.ccv" },
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, }}, 0, "ar.pfs" },
{ CST, ins_const, ext_const, "1", {{ 0, }}, 0, "1" },
{ CST, ins_const, ext_const, "8", {{ 0, }}, 0, "1" },
{ CST, ins_const, ext_const, "16", {{ 0, }}, 0, "16" },
{ CST, ins_const, ext_const, "r0", {{ 0, }}, 0, "r0" },
{ CST, ins_const, ext_const, "ip", {{ 0, }}, 0, "ip" },
{ CST, ins_const, ext_const, "pr", {{ 0, }}, 0, "pr" },
{ CST, ins_const, ext_const, "pr.rot", {{ 0, }}, 0, "pr.rot" },
{ CST, ins_const, ext_const, "psr", {{ 0, }}, 0, "psr" },
{ CST, ins_const, ext_const, "psr.l", {{ 0, }}, 0, "psr.l" },
{ CST, ins_const, ext_const, "psr.um", {{ 0, }}, 0, "psr.um" },
/* register operands: */
{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
"an application register" },
{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
"a branch register" },
{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
"a branch register"},
{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
"a control register"},
{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
"a predicate register" },
{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
"a predicate register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
"a general register r0-r3" },
/* indirect operands: */
{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
"a cpuid register" },
{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
"a dbr register" },
{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
"a dtr register" },
{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
"an itr register" },
{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
"an ibr register" },
{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
"an indirect memory address" },
{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
"an msr register" },
{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
"a pkr register" },
{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
"a pmc register" },
{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
"a pmd register" },
{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
"an rr register" },
/* immediate operands: */
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
"a 5-bit count (0-31)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
"a 2-bit count (1-4)" },
{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
"a 2-bit count (1-3)" },
{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
"a count (0, 7, 15, or 16)" },
{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
"a 5-bit count (0-31)" },
{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
"a 6-bit count (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
"a 1-bit integer (-1, 0)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
"a 2-bit unsigned (0-3)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
"a frame size (register count)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
"a local register count" },
{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
"a rotating register count (integer multiple of 8)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer (-128-127)" },
{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer (-127-128)" },
{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
"a 9-bit unsigned (0-511)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
"a 9-bit integer (-256-255)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
"a 9-bit integer (-256-255)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
"a 14-bit integer (-8192-8191)" },
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
"a 17-bit integer (-65536-65535)" },
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
"a 21-bit unsigned" },
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
"a 22-bit integer" },
{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
{{21, 6}, { 2, 31}, { 1, 36}}, 0,
"a 24-bit unsigned" },
{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
"a 62-bit unsigned" },
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
"a 64-bit unsigned" },
{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
"an increment (+/- 1, 4, 8, or 16)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
"a 4-bit length (1-16)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
"a 6-bit length (1-64)" },
{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
"an 8-bit mix type" },
{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
"a 6-bit bit pos (0-63)" },
{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
"a branch tag" },
{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
"a branch tag" },
{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
"a branch target" },
{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
"a branch target" },
{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
"a branch target" },
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
"a branch target" },
};

42
bfd/cpu-ia64.c Normal file
View File

@ -0,0 +1,42 @@
/* BFD support for the ia64 architecture.
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_ia64_arch =
{
64, /* 64 bits in a word */
64, /* 64 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_ia64,
0, /* only 1 machine */
"ia64",
"ia64",
3, /* log2 of section alignment */
true, /* the one and only */
bfd_default_compatible,
bfd_default_scan ,
0,
};
#include "cpu-ia64-opc.c"

3
bfd/elf.c
View File

@ -3237,6 +3237,9 @@ prep_headers (abfd)
case bfd_arch_i386:
i_ehdrp->e_machine = EM_386;
break;
case bfd_arch_ia64:
i_ehdrp->e_machine = EM_IA_64;
break;
case bfd_arch_m68k:
i_ehdrp->e_machine = EM_68K;
break;

3696
bfd/elf64-ia64.c Normal file
View File

File diff suppressed because it is too large Load Diff

63
bfd/libbfd.h
View File

@ -898,6 +898,69 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_AVR_CALL",
"BFD_RELOC_VTABLE_INHERIT",
"BFD_RELOC_VTABLE_ENTRY",
"BFD_RELOC_IA64_IMM14",
"BFD_RELOC_IA64_IMM22",
"BFD_RELOC_IA64_IMM64",
"BFD_RELOC_IA64_DIR32MSB",
"BFD_RELOC_IA64_DIR32LSB",
"BFD_RELOC_IA64_DIR64MSB",
"BFD_RELOC_IA64_DIR64LSB",
"BFD_RELOC_IA64_GPREL22",
"BFD_RELOC_IA64_GPREL64I",
"BFD_RELOC_IA64_GPREL32MSB",
"BFD_RELOC_IA64_GPREL32LSB",
"BFD_RELOC_IA64_GPREL64MSB",
"BFD_RELOC_IA64_GPREL64LSB",
"BFD_RELOC_IA64_LTOFF22",
"BFD_RELOC_IA64_LTOFF64I",
"BFD_RELOC_IA64_PLTOFF22",
"BFD_RELOC_IA64_PLTOFF64I",
"BFD_RELOC_IA64_PLTOFF64MSB",
"BFD_RELOC_IA64_PLTOFF64LSB",
"BFD_RELOC_IA64_FPTR64I",
"BFD_RELOC_IA64_FPTR32MSB",
"BFD_RELOC_IA64_FPTR32LSB",
"BFD_RELOC_IA64_FPTR64MSB",
"BFD_RELOC_IA64_FPTR64LSB",
"BFD_RELOC_IA64_PCREL21B",
"BFD_RELOC_IA64_PCREL21M",
"BFD_RELOC_IA64_PCREL21F",
"BFD_RELOC_IA64_PCREL32MSB",
"BFD_RELOC_IA64_PCREL32LSB",
"BFD_RELOC_IA64_PCREL64MSB",
"BFD_RELOC_IA64_PCREL64LSB",
"BFD_RELOC_IA64_LTOFF_FPTR22",
"BFD_RELOC_IA64_LTOFF_FPTR64I",
"BFD_RELOC_IA64_LTOFF_FPTR64MSB",
"BFD_RELOC_IA64_LTOFF_FPTR64LSB",
"BFD_RELOC_IA64_SEGBASE",
"BFD_RELOC_IA64_SEGREL32MSB",
"BFD_RELOC_IA64_SEGREL32LSB",
"BFD_RELOC_IA64_SEGREL64MSB",
"BFD_RELOC_IA64_SEGREL64LSB",
"BFD_RELOC_IA64_SECREL32MSB",
"BFD_RELOC_IA64_SECREL32LSB",
"BFD_RELOC_IA64_SECREL64MSB",
"BFD_RELOC_IA64_SECREL64LSB",
"BFD_RELOC_IA64_REL32MSB",
"BFD_RELOC_IA64_REL32LSB",
"BFD_RELOC_IA64_REL64MSB",
"BFD_RELOC_IA64_REL64LSB",
"BFD_RELOC_IA64_LTV32MSB",
"BFD_RELOC_IA64_LTV32LSB",
"BFD_RELOC_IA64_LTV64MSB",
"BFD_RELOC_IA64_LTV64LSB",
"BFD_RELOC_IA64_IPLTMSB",
"BFD_RELOC_IA64_IPLTLSB",
"BFD_RELOC_IA64_EPLTMSB",
"BFD_RELOC_IA64_EPLTLSB",
"BFD_RELOC_IA64_COPY",
"BFD_RELOC_IA64_TPREL22",
"BFD_RELOC_IA64_TPREL64MSB",
"BFD_RELOC_IA64_TPREL64LSB",
"BFD_RELOC_IA64_LTOFF_TP22",
"BFD_RELOC_IA64_LTOFF22X",
"BFD_RELOC_IA64_LDXMOV",
"@@overflow: BFD_RELOC_UNUSED@@",
};
#endif

128
bfd/reloc.c
View File

@ -2749,6 +2749,134 @@ ENUMDOC
is stored in the reloc's addend. For Rel hosts, we are forced to put
this offset in the reloc's section offset.
ENUM
BFD_RELOC_IA64_IMM14
ENUMX
BFD_RELOC_IA64_IMM22
ENUMX
BFD_RELOC_IA64_IMM64
ENUMX
BFD_RELOC_IA64_DIR32MSB
ENUMX
BFD_RELOC_IA64_DIR32LSB
ENUMX
BFD_RELOC_IA64_DIR64MSB
ENUMX
BFD_RELOC_IA64_DIR64LSB
ENUMX
BFD_RELOC_IA64_GPREL22
ENUMX
BFD_RELOC_IA64_GPREL64I
ENUMX
BFD_RELOC_IA64_GPREL32MSB
ENUMX
BFD_RELOC_IA64_GPREL32LSB
ENUMX
BFD_RELOC_IA64_GPREL64MSB
ENUMX
BFD_RELOC_IA64_GPREL64LSB
ENUMX
BFD_RELOC_IA64_LTOFF22
ENUMX
BFD_RELOC_IA64_LTOFF64I
ENUMX
BFD_RELOC_IA64_PLTOFF22
ENUMX
BFD_RELOC_IA64_PLTOFF64I
ENUMX
BFD_RELOC_IA64_PLTOFF64MSB
ENUMX
BFD_RELOC_IA64_PLTOFF64LSB
ENUMX
BFD_RELOC_IA64_FPTR64I
ENUMX
BFD_RELOC_IA64_FPTR32MSB
ENUMX
BFD_RELOC_IA64_FPTR32LSB
ENUMX
BFD_RELOC_IA64_FPTR64MSB
ENUMX
BFD_RELOC_IA64_FPTR64LSB
ENUMX
BFD_RELOC_IA64_PCREL21B
ENUMX
BFD_RELOC_IA64_PCREL21M
ENUMX
BFD_RELOC_IA64_PCREL21F
ENUMX
BFD_RELOC_IA64_PCREL32MSB
ENUMX
BFD_RELOC_IA64_PCREL32LSB
ENUMX
BFD_RELOC_IA64_PCREL64MSB
ENUMX
BFD_RELOC_IA64_PCREL64LSB
ENUMX
BFD_RELOC_IA64_LTOFF_FPTR22
ENUMX
BFD_RELOC_IA64_LTOFF_FPTR64I
ENUMX
BFD_RELOC_IA64_LTOFF_FPTR64MSB
ENUMX
BFD_RELOC_IA64_LTOFF_FPTR64LSB
ENUMX
BFD_RELOC_IA64_SEGBASE
ENUMX
BFD_RELOC_IA64_SEGREL32MSB
ENUMX
BFD_RELOC_IA64_SEGREL32LSB
ENUMX
BFD_RELOC_IA64_SEGREL64MSB
ENUMX
BFD_RELOC_IA64_SEGREL64LSB
ENUMX
BFD_RELOC_IA64_SECREL32MSB
ENUMX
BFD_RELOC_IA64_SECREL32LSB
ENUMX
BFD_RELOC_IA64_SECREL64MSB
ENUMX
BFD_RELOC_IA64_SECREL64LSB
ENUMX
BFD_RELOC_IA64_REL32MSB
ENUMX
BFD_RELOC_IA64_REL32LSB
ENUMX
BFD_RELOC_IA64_REL64MSB
ENUMX
BFD_RELOC_IA64_REL64LSB
ENUMX
BFD_RELOC_IA64_LTV32MSB
ENUMX
BFD_RELOC_IA64_LTV32LSB
ENUMX
BFD_RELOC_IA64_LTV64MSB
ENUMX
BFD_RELOC_IA64_LTV64LSB
ENUMX
BFD_RELOC_IA64_IPLTMSB
ENUMX
BFD_RELOC_IA64_IPLTLSB
ENUMX
BFD_RELOC_IA64_EPLTMSB
ENUMX
BFD_RELOC_IA64_EPLTLSB
ENUMX
BFD_RELOC_IA64_COPY
ENUMX
BFD_RELOC_IA64_TPREL22
ENUMX
BFD_RELOC_IA64_TPREL64MSB
ENUMX
BFD_RELOC_IA64_TPREL64LSB
ENUMX
BFD_RELOC_IA64_LTOFF_TP22
ENUMX
BFD_RELOC_IA64_LTOFF22X
ENUMX
BFD_RELOC_IA64_LDXMOV
ENUMDOC
Intel IA64 Relocations.
ENDSENUM
BFD_RELOC_UNUSED
CODE_FRAGMENT

4
bfd/targets.c
View File

@ -508,6 +508,8 @@ extern const bfd_target b_out_vec_little_host;
extern const bfd_target bfd_efi_app_ia32_vec;
extern const bfd_target bfd_efi_app_ia64_vec;
extern const bfd_target bfd_elf64_alpha_vec;
extern const bfd_target bfd_elf64_ia64_little_vec;
extern const bfd_target bfd_elf64_ia64_big_vec;
extern const bfd_target bfd_elf32_avr_vec;
extern const bfd_target bfd_elf32_bigarc_vec;
extern const bfd_target bfd_elf32_bigarm_vec;
@ -703,6 +705,8 @@ const bfd_target * const bfd_target_vector[] = {
&bfd_elf32_big_generic_vec,
#ifdef BFD64
&bfd_elf64_alpha_vec,
&bfd_elf64_ia64_little_vec,
&bfd_elf64_ia64_big_vec,
#endif
&bfd_elf32_avr_vec,
&bfd_elf32_bigarc_vec,

8
binutils/ChangeLog
View File

@ -1,3 +1,11 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
* Makefile.am (readelf.o): Add elf/ia64.h.
* Makefile.in: Rebuild.
* readelf.c: Include elf/ia64.h.
(guess_is_rela, dump_relocations): Handle EM_IA_64.
2000-04-17 Timothy Wall <twall@cygnus.com>
* objdump.c (disassemble_data): Set octets per byte *after*

1
binutils/Makefile.am
View File

@ -481,6 +481,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \
$(INCDIR)/elf/sparc.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/d10v.h \
$(INCDIR)/elf/d30v.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/mn10200.h \
$(INCDIR)/elf/mn10300.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/arc.h \
$(INCDIR)/elf/ia64.h \
$(INCDIR)/elf/fr30.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/i960.h \
$(INCDIR)/elf/pj.h $(INCDIR)/elf/avr.h bucomm.h config.h \
$(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h

1
binutils/Makefile.in
View File

@ -1337,6 +1337,7 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \
$(INCDIR)/elf/sparc.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/d10v.h \
$(INCDIR)/elf/d30v.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/mn10200.h \
$(INCDIR)/elf/mn10300.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/arc.h \
$(INCDIR)/elf/ia64.h \
$(INCDIR)/elf/fr30.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/i960.h \
$(INCDIR)/elf/pj.h $(INCDIR)/elf/avr.h bucomm.h config.h \
$(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h

5
binutils/readelf.c
View File

@ -70,6 +70,7 @@
#include "elf/i960.h"
#include "elf/pj.h"
#include "elf/avr.h"
#include "elf/ia64.h"
#include "bucomm.h"
#include "getopt.h"
@ -562,6 +563,7 @@ guess_is_rela (e_machine)
case EM_SH:
case EM_ALPHA:
case EM_MCORE:
case EM_IA_64:
return TRUE;
case EM_MMA:
@ -873,6 +875,9 @@ dump_relocations (file, rel_offset, rel_size, symtab, nsyms, strtab, is_rela)
case EM_PJ:
rtype = elf_pj_reloc_type (type);
break;
case EM_IA_64:
rtype = elf_ia64_reloc_type (type);
break;
}
if (rtype == NULL)

18
gas/ChangeLog
View File

@ -1,3 +1,21 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@cygnus.com>
Andrew MacLeod <amacleod@cygnus.com>
Jim Wilson <wilson@cygnus.com>
* Makefile.am (CPU_TYPES): Add ia64.
(TARGET_CPU_CFILES): Add cofnig/tc-ia64.c.
(TARGET_CPU_HFILES): Add config/tc-ia64.h.
* Makefile.in: Rebuild.
* app.c (do_scrub_chars): Handle DOUBLESLASH_COMMENTS.
* configure: Rebuild.
* configure.in: Recognize ia64 as cpu type. Set bfd_gas.
(ia64-*-elf*, ia64-*-linux-gnu*): New targets.
* expr.c (expr): Handle md_optimize_expr.
* read.c (LEX_HASH): Add comment.
* config/tc-ia64.c, config/tc-ia64.h: New files.
2000-04-21 Richard Henderson <rth@cygnus.com>
* config/tc-d30v.c (write_2_short): Disregard opcode1->ecc when

3
gas/Makefile.am
View File

@ -48,6 +48,7 @@ CPU_TYPES = \
h8300 \
h8500 \
hppa \
ia64 \
i370 \
i386 \
i860 \
@ -218,6 +219,7 @@ TARGET_CPU_CFILES = \
config/tc-h8300.c \
config/tc-h8500.c \
config/tc-hppa.c \
config/tc-ia64.c \
config/tc-i370.c \
config/tc-i386.c \
config/tc-i860.c \
@ -254,6 +256,7 @@ TARGET_CPU_HFILES = \
config/tc-h8300.h \
config/tc-h8500.h \
config/tc-hppa.h \
config/tc-ia64.h \
config/tc-i370.h \
config/tc-i386.h \
config/tc-i860.h \

3
gas/Makefile.in
View File

@ -152,6 +152,7 @@ CPU_TYPES = \
h8300 \
h8500 \
hppa \
ia64 \
i370 \
i386 \
i860 \
@ -328,6 +329,7 @@ TARGET_CPU_CFILES = \
config/tc-h8300.c \
config/tc-h8500.c \
config/tc-hppa.c \
config/tc-ia64.c \
config/tc-i370.c \
config/tc-i386.c \
config/tc-i860.c \
@ -365,6 +367,7 @@ TARGET_CPU_HFILES = \
config/tc-h8300.h \
config/tc-h8500.h \
config/tc-hppa.h \
config/tc-ia64.h \
config/tc-i370.h \
config/tc-i386.h \
config/tc-i860.h \

15
gas/app.c
View File

@ -913,6 +913,21 @@ do_scrub_chars (get, tostart, tolen)
ch = ' ';
goto recycle;
}
#ifdef DOUBLESLASH_LINE_COMMENTS
else if (ch2 == '/')
{
do
{
ch = GET ();
}
while (ch != EOF && !IS_NEWLINE (ch));
if (ch == EOF)
as_warn ("end of file in comment; newline inserted");
state = 0;
PUT ('\n');
break;
}
#endif
else
{
if (ch2 != EOF)

8295
gas/config/tc-ia64.c Normal file
View File

File diff suppressed because it is too large Load Diff

218
gas/config/tc-ia64.h Normal file
View File

@ -0,0 +1,218 @@
/* tc-ia64.h -- Header file for tc-ia64.c.
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#include <opcode/ia64.h>
#include <elf/ia64.h>
#define TC_IA64
#define TARGET_FORMAT (OUTPUT_FLAVOR == bfd_target_elf_flavour \
? "elf64-ia64-little" \
: "unknown-format")
#define TARGET_ARCH bfd_arch_ia64
#define TARGET_BYTES_BIG_ENDIAN 0
#define DOUBLESLASH_LINE_COMMENTS /* allow //-style comments */
#define md_number_to_chars number_to_chars_littleendian
#define TC_HANDLES_FX_DONE
#define NEED_LITERAL_POOL /* need gp literal pool */
#define RELOC_REQUIRES_SYMBOL
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define NEED_INDEX_OPERATOR /* [ ] is index operator */
#define QUOTES_IN_INSN /* allow `string "foo;bar"' */
#define LEX_AT LEX_NAME /* allow `@' inside name */
#define LEX_QM LEX_NAME /* allow `?' inside name */
#define LEX_HASH LEX_END_NAME /* allow `#' ending a name */
struct ia64_fix
{
int bigendian; /* byte order at fix location */
enum ia64_opnd opnd;
};
extern void ia64_do_align PARAMS((int n));
extern void ia64_end_of_source PARAMS((void));
extern void ia64_start_line PARAMS((void));
extern int ia64_unrecognized_line PARAMS((int ch));
extern void ia64_frob_label PARAMS((struct symbol *sym));
extern void ia64_flush_pending_output PARAMS((void));
extern int ia64_parse_name (char *name, expressionS *e);
extern int ia64_optimize_expr PARAMS((expressionS *l, operatorT op,
expressionS *r));
extern void ia64_cons_align PARAMS((int));
extern void ia64_flush_insns PARAMS((void));
extern int ia64_fix_adjustable PARAMS((struct fix *fix));
extern int ia64_force_relocation PARAMS((struct fix *));
extern void ia64_cons_fix_new PARAMS ((fragS *f, int where, int nbytes,
expressionS *exp));
extern void ia64_validate_fix PARAMS ((struct fix *fix));
extern char * ia64_canonicalize_symbol_name PARAMS ((char *));
extern flagword ia64_elf_section_flags PARAMS ((flagword, int, int));
extern long ia64_pcrel_from_section PARAMS ((struct fix *fix, segT sec));
extern int ia64_md_do_align PARAMS ((int, const char *, int, int));
#define md_end() ia64_end_of_source ()
#define md_start_line_hook() ia64_start_line ()
#define tc_unrecognized_line(ch) ia64_unrecognized_line (ch)
#define tc_frob_label(s) ia64_frob_label (s)
#define md_flush_pending_output() ia64_flush_pending_output ()
#define md_parse_name(s,e) ia64_parse_name (s, e)
#define tc_canonicalize_symbol_name(s) ia64_canonicalize_symbol_name (s)
#define md_optimize_expr(l,o,r) ia64_optimize_expr (l, o, r)
#define md_cons_align(n) ia64_cons_align (n)
#define TC_FORCE_RELOCATION(f) ia64_force_relocation (f)
#define tc_fix_adjustable(f) ia64_fix_adjustable (f)
#define md_convert_frag(b,s,f) as_fatal ("ia64_convert_frag")
#define md_create_long_jump(p,f,t,fr,s) as_fatal("ia64_create_long_jump")
#define md_create_short_jump(p,f,t,fr,s) \
as_fatal("ia64_create_short_jump")
#define md_estimate_size_before_relax(f,s) \
(as_fatal ("ia64_estimate_size_before_relax"), 1)
#define md_elf_section_flags ia64_elf_section_flags
#define TC_FIX_TYPE struct ia64_fix
#define TC_INIT_FIX_DATA(f) { f->tc_fix_data.opnd = 0; }
#define TC_CONS_FIX_NEW(f,o,l,e) ia64_cons_fix_new (f, o, l, e)
#define TC_VALIDATE_FIX(fix,seg,skip) ia64_validate_fix (fix)
#define MD_PCREL_FROM_SECTION(fix,sec) ia64_pcrel_from_section (fix, sec)
#define md_do_align(n,f,l,m,j) if (ia64_md_do_align (n,f,l,m)) goto j
/* Call md_apply_fix3 with segment instead of md_apply_fix. */
#define MD_APPLY_FIX3
#define WORKING_DOT_WORD /* don't do broken word processing for now */
#define ELF_TC_SPECIAL_SECTIONS \
{ ".sbss", SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \
{ ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \
{ ".IA_64.unwind", SHT_IA_64_UNWIND, SHF_ALLOC }, \
{ ".IA_64.unwind_info", SHT_PROGBITS, SHF_ALLOC },
#define DWARF2_LINE_MIN_INSN_LENGTH 1 /* so slot-multipliers can be 1 */
/* This is the information required for unwind records in an ia64
object file. This is required by GAS and the compiler runtime. */
/* These are the starting point masks for the various types of
unwind records. To create a record of type R3 for instance, one
starts by using the value UNW_R3 and or-ing in any other required values.
These values are also unique (in context), so they can be used to identify
the various record types as well. UNW_Bx and some UNW_Px do have the
same value, but Px can only occur in a prologue context, and Bx in
a body context. */
#define UNW_R1 0x00
#define UNW_R2 0x40
#define UNW_R3 0x60
#define UNW_P1 0x80
#define UNW_P2 0xA0
#define UNW_P3 0xB0
#define UNW_P4 0xB8
#define UNW_P5 0xB9
#define UNW_P6 0xC0
#define UNW_P7 0xE0
#define UNW_P8 0xF0
#define UNW_P9 0xF1
#define UNW_P10 0xFF
#define UNW_X1 0xF9
#define UNW_X2 0xFA
#define UNW_X3 0xFB
#define UNW_X4 0xFC
#define UNW_B1 0x80
#define UNW_B2 0xC0
#define UNW_B3 0xE0
#define UNW_B4 0xF0
/* These are all the various types of unwind records. */
typedef enum
{
prologue, prologue_gr, body, mem_stack_f, mem_stack_v, psp_gr, psp_sprel,
rp_when, rp_gr, rp_br, rp_psprel, rp_sprel, pfs_when, pfs_gr, pfs_psprel,
pfs_sprel, preds_when, preds_gr, preds_psprel, preds_sprel,
fr_mem, frgr_mem, gr_gr, gr_mem, br_mem, br_gr, spill_base, spill_mask,
unat_when, unat_gr, unat_psprel, unat_sprel, lc_when, lc_gr, lc_psprel,
lc_sprel, fpsr_when, fpsr_gr, fpsr_psprel, fpsr_sprel,
priunat_when_gr, priunat_when_mem, priunat_gr, priunat_psprel,
priunat_sprel, bsp_when, bsp_gr, bsp_psprel, bsp_sprel, bspstore_when,
bspstore_gr, bspstore_psprel, bspstore_sprel, rnat_when, rnat_gr,
rnat_psprel, rnat_sprel, epilogue, label_state, copy_state,
spill_psprel, spill_sprel, spill_reg, spill_psprel_p, spill_sprel_p,
spill_reg_p
} unw_record_type;
/* These structures declare the fields that can be used in each of the
4 record formats, R, P, B and X. */
typedef struct unw_r_record
{
unsigned long rlen;
unsigned short mask;
unsigned short grsave;
} unw_r_record;
typedef struct unw_p_record
{
void *imask;
unsigned long t;
unsigned long size;
unsigned long spoff;
unsigned long br;
unsigned long pspoff;
unsigned short gr;
unsigned short rmask;
unsigned short grmask;
unsigned long frmask;
unsigned short brmask;
} unw_p_record;
typedef struct unw_b_record
{
unsigned long t;
unsigned long label;
unsigned short ecount;
} unw_b_record;
typedef struct unw_x_record
{
unsigned long t;
unsigned long spoff;
unsigned long pspoff;
unsigned short reg;
unsigned short treg;
unsigned short qp;
unsigned short xy; /* Value of the XY field.. */
} unw_x_record;
/* This structure is used to determine the specific record type and
its fields. */
typedef struct unwind_record
{
unw_record_type type;
union {
unw_r_record r;
unw_p_record p;
unw_b_record b;
unw_x_record x;
} record;
} unwind_record;

5
gas/configure vendored
View File

@ -1659,6 +1659,7 @@ for this_target in $target $canon_targets ; do
thumb*) cpu_type=arm endian=little ;;
hppa*) cpu_type=hppa ;;
i[456]86) cpu_type=i386 ;;
ia64) cpu_type=ia64 ;;
m680[012346]0) cpu_type=m68k ;;
m68008) cpu_type=m68k ;;
m683??) cpu_type=m68k ;;
@ -1797,6 +1798,9 @@ EOF
i960-*-vxworks*) fmt=bout ;;
i960-*-elf*) fmt=elf ;;
ia64-*-elf*) fmt=elf ;;
ia64-*-linux-gnu*) fmt=elf em=linux ;;
m32r-*-*) fmt=elf bfd_gas=yes ;;
m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*)
@ -1963,6 +1967,7 @@ EOF
arm-*) bfd_gas=yes ;;
# not yet
# i386-aout) bfd_gas=preferred ;;
ia64*-*) bfd_gas=yes ;;
mips-*) bfd_gas=yes ;;
ns32k-*) bfd_gas=yes ;;
ppc-*) bfd_gas=yes ;;

5
gas/configure.in
View File

@ -121,6 +121,7 @@ changequote([,])dnl
hppa*) cpu_type=hppa ;;
changequote(,)dnl
i[456]86) cpu_type=i386 ;;
ia64) cpu_type=ia64 ;;
m680[012346]0) cpu_type=m68k ;;
changequote([,])dnl
m68008) cpu_type=m68k ;;
@ -258,6 +259,9 @@ changequote([,])dnl
i960-*-vxworks*) fmt=bout ;;
i960-*-elf*) fmt=elf ;;
ia64-*-elf*) fmt=elf ;;
ia64-*-linux-gnu*) fmt=elf em=linux ;;
m32r-*-*) fmt=elf bfd_gas=yes ;;
m68k-*-vxworks* | m68k-ericsson-ose | m68k-*-sunos*)
@ -418,6 +422,7 @@ changequote([,])dnl
arm-*) bfd_gas=yes ;;
# not yet
# i386-aout) bfd_gas=preferred ;;
ia64*-*) bfd_gas=yes ;;
mips-*) bfd_gas=yes ;;
ns32k-*) bfd_gas=yes ;;
ppc-*) bfd_gas=yes ;;

7
gas/expr.c
View File

@ -1744,6 +1744,13 @@ expr (rankarg, resultP)
}
/* Optimize common cases. */
#ifdef md_optimize_expr
if (md_optimize_expr (resultP, op_left, &right))
{
/* skip */;
}
else
#endif
if (op_left == O_add && right.X_op == O_constant)
{
/* X + constant. */

2
gas/read.c
View File

@ -105,6 +105,8 @@ die horribly;
#endif
#ifndef LEX_HASH
/* The IA-64 assembler uses # as a suffix designating a symbol. We include
it in the symbol and strip it out in tc_canonicalize_symbol_name. */
#define LEX_HASH 0
#endif

8
gas/testsuite/ChangeLog
View File

@ -1,3 +1,11 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@cygnus.com>
Jim Wilson <wilson@cygnus.com>
* gas/vtable/vtable.exp: Disable for ia64.
* gas/testsuite/gas/ia64: New testsuite directory.
2000-04-03 Alan Modra <alan@linuxcare.com.au>
* gas/i386/general.s: Check 16-bit immediates, and move call/jump

15
gas/testsuite/gas/ia64/dv-branch.d Normal file
View File

@ -0,0 +1,15 @@
# as: -xexplicit
# objdump: -d
# name ia64 dv-branch
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <\.text>:
0: d0 08 00 10 18 90 \[MIB\] \(p06\) ld8 r1=\[r8\]
6: 61 10 04 80 03 03 \(p06\) mov b6=r2
c: 68 00 00 10 \(p06\) br\.call\.sptk\.many b0=b6
10: 11 08 00 3c 00 21 \[MIB\] mov r1=r30
16: 00 00 00 02 00 03 nop\.i 0x0
1c: f0 ff ff 48 \(p06\) br\.cond\.sptk\.few 0x0;;

16
gas/testsuite/gas/ia64/dv-branch.s Normal file
View File

@ -0,0 +1,16 @@
//
// Verify DV detection on branch variations
//
.text
.explicit
// example from rth
3:
{ .mib
(p6) ld8 gp = [ret0]
(p6) mov b6 = r2
(p6) br.call.sptk.many b0 = b6 // if taken, clears b6/r2 usage
}
{ .mib
mov gp = r30
(p6) br.sptk.few 3b
}

3
gas/testsuite/gas/ia64/dv-entry-err.l Normal file
View File

@ -0,0 +1,3 @@
.*: Assembler messages:
.*:14: Warning: Use of 'mov' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\) when entry is at label 'L', specific resource number is 5
.*:13: Warning: This is the location of the conflicting usage

15
gas/testsuite/gas/ia64/dv-entry-err.s Normal file
View File

@ -0,0 +1,15 @@
//
// Verify DV detection on multiple paths
//
.text
.explicit
// RAW on r4 is avoided on both paths
// RAW on r5 is avoided on path 0 (from top) but not path 1 (from L)
cmp.eq p1, p2 = r1, r2
cmp.eq p3, p4 = r3, r0
(p1) mov r4 = 2
L:
(p2) mov r4 = 5
(p3) mov r5 = r7
(p4) mov r5 = r8

42
gas/testsuite/gas/ia64/dv-imply.d Normal file
View File

@ -0,0 +1,42 @@
# as: -xexplicit
# objdump: -d
# name ia64 dv-mutex
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <L-0xb0>:
0: 30 20 08 00 00 21 \[MIB\] \(p01\) mov r4=2
6: 00 00 00 02 00 01 nop\.i 0x0
c: b0 00 00 40 \(p02\) br\.cond\.sptk\.few b0 <L>
10: 11 20 1c 00 00 21 \[MIB\] mov r4=7
16: 00 00 00 02 00 00 nop\.i 0x0
1c: 00 00 20 00 rfi;;
20: 10 20 08 00 00 21 \[MIB\] mov r4=2
26: 00 00 00 02 00 01 nop\.i 0x0
2c: 90 00 00 40 \(p02\) br\.cond\.sptk\.few b0 <L>
30: 31 20 1c 00 00 21 \[MIB\] \(p01\) mov r4=7
36: 00 00 00 02 00 00 nop\.i 0x0
3c: 00 00 20 00 rfi;;
40: 70 08 06 04 02 78 \[MIB\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
46: 40 10 00 00 c2 01 \(p01\) mov r4=2
4c: 70 00 00 40 \(p03\) br\.cond\.sptk\.few b0 <L>
50: 11 20 1c 00 00 21 \[MIB\] mov r4=7
56: 00 00 00 02 00 00 nop\.i 0x0
5c: 00 00 20 00 rfi;;
60: 60 08 06 04 02 38 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
66: 30 28 18 88 e8 80 cmp\.eq\.or p3,p4=r5,r6
6c: 20 00 00 84 \(p01\) mov r4=2
70: 10 00 00 00 01 00 \[MIB\] nop\.m 0x0
76: 00 00 00 02 80 01 nop\.i 0x0
7c: 40 00 00 40 \(p03\) br\.cond\.sptk\.few b0 <L>
80: 11 20 1c 00 00 21 \[MIB\] mov r4=7
86: 00 00 00 02 00 00 nop\.i 0x0
8c: 00 00 20 00 rfi;;
90: 10 08 16 0c 42 70 \[MIB\] cmp\.ne\.and p1,p2=r5,r6
96: 40 10 00 00 c2 01 \(p01\) mov r4=2
9c: 20 00 00 40 \(p03\) br\.cond\.sptk\.few b0 <L>
a0: 11 20 1c 00 00 21 \[MIB\] mov r4=7
a6: 00 00 00 02 00 00 nop\.i 0x0
ac: 00 00 20 00 rfi;;

44
gas/testsuite/gas/ia64/dv-imply.s Normal file
View File

@ -0,0 +1,44 @@
//
// Test various implies relations
//
.text
// User-supplied hint
.pred.rel.imply p1, p2
(p1) mov r4 = 2
(p2) br.cond.sptk L
mov r4 = 7
rfi
// Symmetric to previous example
.pred.rel.imply p1, p2
mov r4 = 2
(p2) br.cond.sptk L
(p1) mov r4 = 7
rfi
// Verify that the implies relationship caused by the unconditional compare
// prevents RAW on r4.
(p3) cmp.eq.unc p1, p2 = r1, r2 // p1,p2 imply p3
(p1) mov r4 = 2
(p3) br.cond.sptk L
mov r4 = 7
rfi
// An instance of cmp.rel.or should not affect an implies relation.
(p3) cmp.eq.unc p1, p2 = r1, r2 // p1,p2 imply p3
cmp.eq.or p3, p4 = r5, r6 // doesn't affect implies rel
(p1) mov r4 = 2
(p3) br.cond.sptk L
mov r4 = 7
rfi
// An instance of cmp.rel.and only affects imply targets
.pred.rel.imply p1,p3
cmp.ne.and p1, p2 = r5, r6 // doesn't affect imply source
(p1) mov r4 = 2
(p3) br.cond.sptk L
mov r4 = 7
rfi
// FIXME -- add tests for and.orcm and or.andcm
L:

4
gas/testsuite/gas/ia64/dv-mutex-err.l Normal file
View File

@ -0,0 +1,4 @@
.*: Assembler messages:
.*:9: Warning: Use of 'ld8' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 26
.*:9: Warning: Only the first path encountering the conflict is reported
.*:8: Warning: This is the location of the conflicting usage

9
gas/testsuite/gas/ia64/dv-mutex-err.s Normal file
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//
// Test mutex relation handling
//
.text
.explicit
start:
cmp.eq p6, p0 = r29, r0
add r26 = r26, r29
ld8 r29 = [r26]

27
gas/testsuite/gas/ia64/dv-mutex.d Normal file
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# as: -xexplicit
# objdump: -d
# name ia64 dv-mutex
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <start>:
0: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2
6: 40 28 00 00 c2 81 \(p02\) mov r4=5
c: 70 00 00 84 \(p03\) mov r4=7
10: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0
16: 00 00 00 02 00 00 nop\.i 0x0
1c: 00 00 20 00 rfi;;
20: 00 08 04 04 02 78 \[MII\] cmp\.eq p1,p2=r1,r2
26: 40 10 00 00 42 81 \(p01\) mov r4=2
2c: 40 00 00 84 \(p02\) mov r4=4
30: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0
36: 00 00 00 02 00 00 nop\.i 0x0
3c: 00 00 20 00 rfi;;
40: 60 08 06 04 02 78 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
46: 40 10 00 00 42 81 \(p01\) mov r4=2
4c: 40 00 00 84 \(p02\) mov r4=4
50: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0
56: 00 00 00 02 00 00 nop\.i 0x0
5c: 00 00 20 00 rfi;;

24
gas/testsuite/gas/ia64/dv-mutex.s Normal file
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//
// Test mutex relation handling
//
.text
start:
// user annotation
.pred.rel.mutex p1, p2, p3
(p1) mov r4 = 2
(p2) mov r4 = 5
(p3) mov r4 = 7
rfi
// non-predicated compares generate a mutex
cmp.eq p1, p2 = r1, r2
(p1) mov r4 = 2
(p2) mov r4 = 4
rfi
// unconditional compares generate a mutex
(p3) cmp.eq.unc p1, p2 = r1, r2
(p1) mov r4 = 2
(p2) mov r4 = 4
rfi
L:

267
gas/testsuite/gas/ia64/dv-raw-err.l Normal file
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.*: Assembler messages:
.*:10: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[BSP\]' \(impliedf\)
.*:9: Warning: This is the location of the conflicting usage
.*:10: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
.*:9: Warning: This is the location of the conflicting usage
.*:15: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[BSPSTORE\]' \(impliedf\)
.*:14: Warning: This is the location of the conflicting usage
.*:15: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
.*:14: Warning: This is the location of the conflicting usage
.*:20: Warning: Use of 'cmpxchg8\.acq' .* RAW dependency 'AR\[CCV\]' \(impliedf\)
.*:19: Warning: This is the location of the conflicting usage
.*:25: Warning: Use of 'mov\.i' .* RAW dependency 'AR\[EC\]' \(impliedf\)
.*:24: Warning: This is the location of the conflicting usage
.*:30: Warning: Use of 'fpcmp\.eq\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:29: Warning: This is the location of the conflicting usage
.*:35: Warning: Use of 'fpcmp\.eq\.s1' .* RAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\)
.*:34: Warning: This is the location of the conflicting usage
.*:40: Warning: Use of 'fpcmp\.eq\.s2' .* RAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\)
.*:39: Warning: This is the location of the conflicting usage
.*:45: Warning: Use of 'fpcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
.*:44: Warning: This is the location of the conflicting usage
.*:50: Warning: Use of 'fchkf\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
.*:49: Warning: This is the location of the conflicting usage
.*:55: Warning: Use of 'fchkf\.s1' .* RAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
.*:54: Warning: This is the location of the conflicting usage
.*:60: Warning: Use of 'fchkf\.s2' .* RAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
.*:59: Warning: This is the location of the conflicting usage
.*:65: Warning: Use of 'fchkf\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
.*:64: Warning: This is the location of the conflicting usage
.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
.*:69: Warning: This is the location of the conflicting usage
.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.traps' \(impliedf\)
.*:69: Warning: This is the location of the conflicting usage
.*:70: Warning: Use of 'fcmp\.eq\.s3' .* RAW dependency 'AR\[FPSR\]\.rv' \(impliedf\)
.*:69: Warning: This is the location of the conflicting usage
.*:70: Warning: Use of 'fcmp\.eq\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
.*:69: Warning: This is the location of the conflicting usage
.*:75: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[ITC\]' \(impliedf\)
.*:74: Warning: This is the location of the conflicting usage
.*:80: Warning: Use of 'br\.ia\.sptk' .* RAW dependency 'AR\[K%\], % in 0 - 7' \(impliedf\), specific resource number is 1
.*:79: Warning: This is the location of the conflicting usage
.*:85: Warning: Use of 'mov\.i' .* RAW dependency 'AR\[LC\]' \(impliedf\)
.*:84: Warning: This is the location of the conflicting usage
.*:90: Warning: Use of 'epc' .* RAW dependency 'AR\[PFS\]' \(impliedf\)
.*:89: Warning: This is the location of the conflicting usage
.*:94: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[RNAT\]' \(impliedf\)
.*:93: Warning: This is the location of the conflicting usage
.*:94: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
.*:93: Warning: This is the location of the conflicting usage
.*:99: Warning: Use of 'mov\.m' .* RAW dependency 'AR\[RSC\]' \(impliedf\)
.*:98: Warning: This is the location of the conflicting usage
.*:104: Warning: Use of 'ld8\.fill' .* RAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\)
.*:103: Warning: This is the location of the conflicting usage
.*:111: Warning: Use of 'mov' .* RAW dependency 'BR%, % in 0 - 7' \(impliedf\)
.*:110: Warning: This is the location of the conflicting usage
.*:116: Warning: Use of 'fadd' .* RAW dependency 'CFM' \(impliedf\)
.*:115: Warning: This is the location of the conflicting usage
.*:121: Warning: Use of 'mov' .* RAW dependency 'CR\[CMCV\]' \(data\)
.*:120: Warning: This is the location of the conflicting usage
.*:126: Warning: Use of 'ld8\.s' .* RAW dependency 'CR\[DCR\]' \(data\)
.*:125: Warning: This is the location of the conflicting usage
.*:133: Warning: Use of 'thash' .* RAW dependency 'CR\[GPTA\]' \(data\)
.*:132: Warning: This is the location of the conflicting usage
.*:139: Warning: Use of 'itc\.i' .* RAW dependency 'CR\[IFA\]' \(implied\)
.*:138: Warning: This is the location of the conflicting usage
.*:144: Warning: Use of 'mov' .* RAW dependency 'CR\[IFS\]' \(data\)
.*:143: Warning: This is the location of the conflicting usage
.*:149: Warning: Use of 'mov' .* RAW dependency 'CR\[IHA\]' \(data\)
.*:148: Warning: This is the location of the conflicting usage
.*:154: Warning: Use of 'mov' .* RAW dependency 'CR\[IIM\]' \(data\)
.*:153: Warning: This is the location of the conflicting usage
.*:159: Warning: Use of 'rfi' .* RAW dependency 'CR\[IIP\]' \(implied\)
.*:158: Warning: This is the location of the conflicting usage
.*:164: Warning: Use of 'mov' .* RAW dependency 'CR\[IIPA\]' \(data\)
.*:163: Warning: This is the location of the conflicting usage
.*:169: Warning: Use of 'rfi' .* RAW dependency 'CR\[IPSR\]' \(implied\)
.*:168: Warning: This is the location of the conflicting usage
.*:174: Warning: Use of 'mov' .* RAW dependency 'CR\[IRR%\], % in 0 - 3' \(data\), specific resource number is 68
.*:173: Warning: This is the location of the conflicting usage
.*:179: Warning: Use of 'mov' .* RAW dependency 'CR\[ISR\]' \(data\)
.*:178: Warning: This is the location of the conflicting usage
.*:184: Warning: Use of 'itc\.d' .* RAW dependency 'CR\[ITIR\]' \(implied\)
.*:183: Warning: This is the location of the conflicting usage
.*:189: Warning: Use of 'mov' .* RAW dependency 'CR\[ITM\]' \(data\)
.*:188: Warning: This is the location of the conflicting usage
.*:194: Warning: Use of 'mov' .* RAW dependency 'CR\[ITV\]' \(data\)
.*:193: Warning: This is the location of the conflicting usage
.*:201: Warning: Use of 'mov' .* RAW dependency 'CR\[IVA\]' \(instr\)
.*:200: Warning: This is the location of the conflicting usage
.*:206: Warning: Use of 'mov' .* RAW dependency 'CR\[LID\]' \(other\)
.*:205: Warning: This is the location of the conflicting usage
.*:212: Warning: Use of 'mov' .* RAW dependency 'CR\[LRR%\], % in 0 - 1' \(data\), specific resource number is 80
.*:211: Warning: This is the location of the conflicting usage
.*:217: Warning: Use of 'mov' .* RAW dependency 'CR\[PMV\]' \(data\)
.*:216: Warning: This is the location of the conflicting usage
.*:222: Warning: Use of 'thash' .* RAW dependency 'CR\[PTA\]' \(data\)
.*:221: Warning: This is the location of the conflicting usage
.*:227: Warning: Use of 'mov' .* RAW dependency 'CR\[TPR\]' \(data\)
.*:226: Warning: This is the location of the conflicting usage
.*:231: Warning: Use of 'mov' .* RAW dependency 'CR\[TPR\]' \(other\)
.*:230: Warning: This is the location of the conflicting usage
.*:237: Warning: Use of 'mov' .* RAW dependency 'DBR#' \(impliedf\)
.*:236: Warning: This is the location of the conflicting usage
.*:241: Warning: Use of 'probe\.r' .* RAW dependency 'DBR#' \(data\)
.*:240: Warning: This is the location of the conflicting usage
.*:247: Warning: Use of 'fc' .* RAW dependency 'DTC' \(data\)
.*:246: Warning: This is the location of the conflicting usage
.*:251: Warning: Use of 'ptc\.e' .* RAW dependency 'DTC' \(impliedf\)
.*:250: Warning: This is the location of the conflicting usage
.*:251: Warning: Use of 'ptc\.e' .* WAW dependency 'DTC' \(impliedf\)
.*:250: Warning: This is the location of the conflicting usage
.*:251: Warning: Use of 'ptc\.e' .* WAW dependency 'ITC' \(impliedf\)
.*:250: Warning: This is the location of the conflicting usage
.*:262: Warning: Use of 'tak' .* RAW dependency 'DTC' \(data\)
.*:261: Warning: This is the location of the conflicting usage
.*:262: Warning: Use of 'tak' .* RAW dependency 'DTR' \(data\)
.*:261: Warning: This is the location of the conflicting usage
.*:266: Warning: Use of 'tpa' .* RAW dependency 'DTC' \(data\)
.*:265: Warning: This is the location of the conflicting usage
.*:266: Warning: Use of 'tpa' .* RAW dependency 'DTR' \(data\)
.*:265: Warning: This is the location of the conflicting usage
.*:275: Warning: Use of 'mov' .* RAW dependency 'FR%, % in 2 - 127' \(impliedf\), specific resource number is 4
.*:274: Warning: This is the location of the conflicting usage
.*:283: Warning: Use of 'mov' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 3
.*:282: Warning: This is the location of the conflicting usage
.*:288: Warning: Use of 'mov' .* RAW dependency 'IBR#' \(impliedf\)
.*:287: Warning: This is the location of the conflicting usage
.*:293: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(data\)
.*:292: Warning: This is the location of the conflicting usage
.*:293: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:292: Warning: This is the location of the conflicting usage
.*:297: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
.*:296: Warning: This is the location of the conflicting usage
.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 71
.*:296: Warning: This is the location of the conflicting usage
.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 70
.*:296: Warning: This is the location of the conflicting usage
.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 69
.*:296: Warning: This is the location of the conflicting usage
.*:297: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 68
.*:296: Warning: This is the location of the conflicting usage
.*:297: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:296: Warning: This is the location of the conflicting usage
.*:299: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:297: Warning: This is the location of the conflicting usage
.*:299: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:296: Warning: This is the location of the conflicting usage
.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:297: Warning: This is the location of the conflicting usage
.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:296: Warning: This is the location of the conflicting usage
.*:300: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
.*:299: Warning: This is the location of the conflicting usage
.*:300: Warning: Use of 'mov' .* WAW dependency 'CR\[EOI\]' \(other\)
.*:299: Warning: This is the location of the conflicting usage
.*:300: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:299: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'epc' .* RAW dependency 'ITC' \(instr\)
.*:304: Warning: This is the location of the conflicting usage
.*:314: Warning: Use of 'epc' .* RAW dependency 'ITC' \(instr\)
.*:313: Warning: This is the location of the conflicting usage
.*:314: Warning: Use of 'epc' .* RAW dependency 'ITR' \(instr\)
.*:313: Warning: This is the location of the conflicting usage
.*:321: Warning: Use of 'probe\.r' .* RAW dependency 'PKR#' \(data\)
.*:320: Warning: This is the location of the conflicting usage
.*:325: Warning: Use of 'mov' .* RAW dependency 'PKR#' \(data\)
.*:324: Warning: This is the location of the conflicting usage
.*:325: Warning: Use of 'mov' .* RAW dependency 'PKR#' \(impliedf\)
.*:324: Warning: This is the location of the conflicting usage
.*:331: Warning: Use of 'mov' .* RAW dependency 'PMC#' \(impliedf\)
.*:330: Warning: This is the location of the conflicting usage
.*:335: Warning: Use of 'mov' .* RAW dependency 'PMC#' \(other\)
.*:334: Warning: This is the location of the conflicting usage
.*:341: Warning: Use of 'mov' .* RAW dependency 'PMD#' \(impliedf\)
.*:340: Warning: This is the location of the conflicting usage
.*:346: Warning: Use of 'add' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:345: Warning: This is the location of the conflicting usage
.*:349: Warning: Use of 'add' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 2
.*:348: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.cond\.sptk' .* RAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 5
.*:351: Warning: This is the location of the conflicting usage
.*:360: Warning: Use of 'add' .* RAW dependency 'CFM' \(impliedf\)
.*:359: Warning: This is the location of the conflicting usage
.*:360: Warning: Use of 'add' .* RAW dependency 'PR63' \(impliedf\)
.*:359: Warning: This is the location of the conflicting usage
.*:363: Warning: Use of 'add' .* RAW dependency 'PR63' \(impliedf\)
.*:362: Warning: This is the location of the conflicting usage
.*:371: Warning: Use of 'ld8' .* RAW dependency 'PSR\.ac' \(implied\)
.*:370: Warning: This is the location of the conflicting usage
.*:376: Warning: Use of 'ld8' .* RAW dependency 'PSR\.be' \(implied\)
.*:375: Warning: This is the location of the conflicting usage
.*:389: Warning: Use of 'st8' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:388: Warning: This is the location of the conflicting usage
.*:392: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:391: Warning: This is the location of the conflicting usage
.*:395: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:394: Warning: This is the location of the conflicting usage
.*:398: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:397: Warning: This is the location of the conflicting usage
.*:401: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:400: Warning: This is the location of the conflicting usage
.*:404: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:403: Warning: This is the location of the conflicting usage
.*:413: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:412: Warning: This is the location of the conflicting usage
.*:416: Warning: Use of 'mov' .* RAW dependency 'PSR\.cpl' \(implied\)
.*:415: Warning: This is the location of the conflicting usage
.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.ac' \(data\)
.*:421: Warning: This is the location of the conflicting usage
.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.be' \(data\)
.*:421: Warning: This is the location of the conflicting usage
.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.db' \(data\)
.*:421: Warning: This is the location of the conflicting usage
.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.dt' \(data\)
.*:421: Warning: This is the location of the conflicting usage
.*:422: Warning: Use of 'ld8' .* RAW dependency 'PSR\.pk' \(data\)
.*:421: Warning: This is the location of the conflicting usage
.*:430: Warning: Use of 'mov' .* RAW dependency 'PSR\.dfh' \(data\)
.*:429: Warning: This is the location of the conflicting usage
.*:430: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:429: Warning: This is the location of the conflicting usage
.*:436: Warning: Use of 'mov' .* RAW dependency 'PSR\.dfl' \(data\)
.*:435: Warning: This is the location of the conflicting usage
.*:436: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:435: Warning: This is the location of the conflicting usage
.*:442: Warning: Use of 'mov' .* RAW dependency 'PSR\.di' \(impliedf\)
.*:441: Warning: This is the location of the conflicting usage
.*:447: Warning: Use of 'ld8' .* RAW dependency 'PSR\.dt' \(data\)
.*:446: Warning: This is the location of the conflicting usage
.*:453: Warning: Use of 'mov' .* RAW dependency 'PSR\.i' \(impliedf\)
.*:452: Warning: This is the location of the conflicting usage
.*:459: Warning: Use of 'mov' .* RAW dependency 'PSR\.ic' \(impliedf\)
.*:458: Warning: This is the location of the conflicting usage
.*:463: Warning: Use of 'mov' .* RAW dependency 'PSR\.ic' \(data\)
.*:462: Warning: This is the location of the conflicting usage
.*:476: Warning: Use of 'br\.ret\.sptk' .* RAW dependency 'PSR\.lp' \(data\)
.*:475: Warning: This is the location of the conflicting usage
.*:476: Warning: Use of 'br\.ret\.sptk' .* RAW dependency 'PSR\.tb' \(data\)
.*:475: Warning: This is the location of the conflicting usage
.*:482: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfh' \(impliedf\)
.*:481: Warning: This is the location of the conflicting usage
.*:487: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfl' \(impliedf\)
.*:486: Warning: This is the location of the conflicting usage
.*:492: Warning: Use of 'ld8' .* RAW dependency 'PSR\.pk' \(data\)
.*:491: Warning: This is the location of the conflicting usage
.*:495: Warning: Use of 'mov' .* RAW dependency 'PSR\.pk' \(impliedf\)
.*:494: Warning: This is the location of the conflicting usage
.*:500: Warning: Use of 'mov' .* RAW dependency 'PSR\.pp' \(impliedf\)
.*:499: Warning: This is the location of the conflicting usage
.*:506: Warning: Use of 'flushrs' .* RAW dependency 'PSR\.rt' \(data\)
.*:505: Warning: This is the location of the conflicting usage
.*:512: Warning: Use of 'mov\.m' .* RAW dependency 'PSR\.si' \(data\)
.*:511: Warning: This is the location of the conflicting usage
.*:520: Warning: Use of 'mov' .* RAW dependency 'PSR\.sp' \(data\)
.*:519: Warning: This is the location of the conflicting usage
.*:523: Warning: Use of 'rum' .* RAW dependency 'PSR\.sp' \(data\)
.*:519: Warning: This is the location of the conflicting usage
.*:523: Warning: Use of 'rum' .* RAW dependency 'PSR\.sp' \(data\)
.*:522: Warning: This is the location of the conflicting usage
.*:532: Warning: Use of 'chk\.s' .* RAW dependency 'PSR\.tb' \(data\)
.*:531: Warning: This is the location of the conflicting usage
.*:537: Warning: Use of 'mov' .* RAW dependency 'PSR\.up' \(impliedf\)
.*:536: Warning: This is the location of the conflicting usage
.*:543: Warning: Use of 'ld8' .* RAW dependency 'RR#' \(data\)
.*:542: Warning: This is the location of the conflicting usage
.*:546: Warning: Use of 'mov' .* RAW dependency 'RR#' \(impliedf\)
.*:545: Warning: This is the location of the conflicting usage

549
gas/testsuite/gas/ia64/dv-raw-err.s Normal file
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@ -0,0 +1,549 @@
//
// Detect RAW violations. Cases taken from DV tables.
// This test is by no means complete but tries to hit the things that are
// likely to be missed.
//
.text
.explicit
// AR[BSP]
mov ar.bspstore = r1
mov r0 = ar.bsp
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov r3 = ar.bspstore
;;
// AR[CCV]
mov ar.ccv = r4
cmpxchg8.acq r5 = [r6],r7,ar.ccv
;;
// AR[EC]
br.wtop.sptk L
mov r8 = ar.ec
;;
// AR[FPSR].sf0.controls
fsetc.s0 0x7f, 0x0f
fpcmp.eq.s0 f2 = f3, f4
;;
// AR[FPSR].sf1.controls
fsetc.s1 0x7f, 0x0f
fpcmp.eq.s1 f2 = f3, f4
;;
// AR[FPSR].sf2.controls
fsetc.s2 0x7f, 0x0f
fpcmp.eq.s2 f2 = f3, f4
;;
// AR[FPSR].sf3.controls
fsetc.s3 0x7f, 0x0f
fpcmp.eq.s3 f2 = f3, f4
;;
// AR[FPSR].sf0.flags
fpcmp.eq.s0 f2 = f3, f4
fchkf.s0 L
;;
// AR[FPSR].sf1.flags
fpcmp.eq.s1 f2 = f3, f4
fchkf.s1 L
;;
// AR[FPSR].sf2.flags
fpcmp.eq.s2 f2 = f3, f4
fchkf.s2 L
;;
// AR[FPSR].sf3.flags
fpcmp.eq.s3 f2 = f3, f4
fchkf.s3 L
;;
// AR[FPSR].traps/rv
mov ar.fpsr = r0
fcmp.eq.s3 p1, p2 = f5, f6
;;
// AR[ITC]
mov ar.itc = r1
mov r2 = ar.itc
;;
// AR[K]
mov ar.k1 = r3
br.ia.sptk b0
;;
// AR[LC]
br.cloop.sptk L
mov r4 = ar.lc
;;
// AR[PFS]
mov ar.pfs = r5
epc
// AR[RNAT]
mov ar.bspstore = r8
mov r9 = ar.rnat
;;
// AR[RSC]
mov ar.rsc = r10
mov r11 = ar.rnat
;;
// AR[UNAT]
mov ar.unat = r12
ld8.fill r13 = [r14]
;;
// AR%
// BR%
mov b0 = r0
mov r0 = b0
;;
// CFM
br.wtop.sptk L
fadd f0 = f1, f32 // read from rotating register region
;;
// CR[CMCV]
mov cr.cmcv = r1
mov r2 = cr.cmcv
;;
// CR[DCR]
mov cr.dcr = r3
ld8.s r4 = [r5]
;;
// CR[EOI]
// CR[GPTA]
mov cr.gpta = r6
thash r7 = r8
;;
srlz.d
// CR[IFA]
mov cr.ifa = r9
itc.i r10
;;
// CR[IFS]
mov cr.ifs = r11
mov r12 = cr.ifs
;;
// CR[IHA]
mov cr.iha = r13
mov r14 = cr.iha
;;
// CR[IIM]
mov cr.iim = r15
mov r16 = cr.iim
;;
// CR[IIP]
mov cr.iip = r17
rfi
;;
// CR[IIPA]
mov cr.iipa = r19
mov r20 = cr.iipa
;;
// CR[IPSR]
mov cr.ipsr = r21
rfi
;;
// CR[IRR%]
mov r22 = cr.ivr
mov r23 = cr.irr0
;;
// CR[ISR]
mov cr.isr = r24
mov r25 = cr.isr
;;
// CR[ITIR]
mov cr.itir = r26
itc.d r27
;;
// CR[ITM]
mov cr.itm = r28
mov r29 = cr.itm
;;
// CR[ITV]
mov cr.itv = r0
mov r1 = cr.itv
;;
// CR[IVR] (all writes are implicit in other resource usage)
// CR[IVA]
mov cr.iva = r0
mov r1 = cr.iva
;;
// CR[LID]
mov cr.lid = r0
mov r1 = cr.lid
;;
srlz.d
// CR[LRR%]
mov cr.lrr0 = r0
mov r1 = cr.lrr0
;;
// CR[PMV]
mov cr.pmv = r0
mov r1 = cr.pmv
;;
// CR[PTA]
mov cr.pta = r0
thash r1 = r2
;;
// CR[TPR]
mov cr.tpr = r0
mov r1 = cr.ivr // data
;;
srlz.d
mov cr.tpr = r2
mov psr.l = r3 // other
;;
srlz.d
// DBR#
mov dbr[r0] = r1
mov r2 = dbr[r3]
;;
srlz.d
mov dbr[r4] = r5
probe.r r6 = r7, r8
;;
srlz.d
// DTC
ptc.e r0
fc r1
;;
srlz.d
itr.i itr[r2] = r3
ptc.e r4
;;
// DTC_LIMIT/ITC_LIMIT
ptc.g r0, r1 // NOTE: GAS automatically emits stops after
ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
;; // longer possible in GAS-generated assembly
srlz.d
// DTR
itr.d dtr[r0] = r1
tak r2 = r3
;;
srlz.d
ptr.d r4, r5
tpa r6 = r7
;;
srlz.d
// FR%
ldfs.c.clr f2 = [r1]
mov f3 = f2 // no DV here
;;
mov f4 = f5
mov f6 = f4
;;
// GR%
ld8.c.clr r0 = [r1] // no DV here
mov r2 = r0
;;
mov r3 = r4
mov r5 = r3
;;
// IBR#
mov ibr[r0] = r1
mov r2 = ibr[r3]
;;
// InService
mov cr.eoi = r0
mov r1 = cr.ivr
;;
srlz.d
mov r2 = cr.ivr
mov r3 = cr.ivr // several DVs
;;
mov cr.eoi = r4
mov cr.eoi = r5
;;
// ITC
ptc.e r0
epc
;;
srlz.i
;;
// ITC_LIMIT (see DTC_LIMIT)
// ITR
itr.i itr[r0] = r1
epc
;;
srlz.i
;;
// PKR#
mov pkr[r0] = r1
probe.r r2 = r3, r4
;;
srlz.d
mov pkr[r5] = r6
mov r7 = pkr[r8]
;;
srlz.d
// PMC#
mov pmc[r0] = r1
mov r2 = pmc[r3]
;;
srlz.d
mov pmc[r4] = r5
mov r6 = pmd[r7]
;;
srlz.d
// PMD#
mov pmd[r0] = r1
mov r2 = pmd[r3]
;;
// PR%
cmp.eq p1, p2 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
(p1) add r2 = r3, r4
;;
mov pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p2) add r6 = r7, r8
;;
fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br
(p5) br.cond.sptk b0
;;
cmp.eq p7, p8 = r11, r12
(p7) br.cond.sptk b1 // no DV here
;;
// PR63
br.wtop.sptk L
(p63) add r0 = r1, r2
;;
fcmp.eq p62, p63 = f2, f3
(p63) add r3 = r4, r5
;;
cmp.eq p62, p63 = r6, r7 // no DV here
(p63) br.cond.sptk b0
;;
// PSR.ac
rum (1<<3)
ld8 r0 = [r1]
;;
// PSR.be
rum (1<<1)
ld8 r0 = [r1]
;;
// PSR.bn
bsw.0
mov r0 = r15 // no DV here, since gr < 16
;;
bsw.1 // GAS automatically emits a stop after bsw.n
mov r1 = r16 // so this conflict is avoided
;;
// PSR.cpl
epc
st8 [r0] = r1
;;
epc
mov r2 = ar.itc
;;
epc
mov ar.itc = r3
;;
epc
mov ar.rsc = r4
;;
epc
mov ar.k0 = r5
;;
epc
mov r6 = pmd[r7]
;;
epc
mov ar.bsp = r8 // no DV here
;;
epc
mov r9 = ar.bsp // no DV here
;;
epc
mov cr.ifa = r10 // any mov-to/from-cr is a DV
;;
epc
mov r11 = cr.eoi // any mov-to/from-cr is a DV
;;
// PSR.da (rfi is the only writer)
// PSR.db (also ac,be,dt,pk)
mov psr.l = r0
ld8 r1 = [r2]
;;
srlz.d
// PSR.dd (rfi is the only writer)
// PSR.dfh
mov psr.l = r0
mov f64 = f65
;;
srlz.d
// PSR.dfl
mov psr.l = r0
mov f3 = f4
;;
srlz.d
// PSR.di
rsm (1<<22)
mov r0 = psr
;;
// PSR.dt
rsm (1<<17)
ld8 r0 = [r1]
;;
// PSR.ed (rfi is the only writer)
// PSR.i
ssm (1<<14)
mov r0 = psr
;;
// PSR.ia (no DV semantics)
// PSR.ic
ssm (1<<13)
mov r0 = psr
;;
srlz.d
rsm (1<<13)
mov r1 = cr.itir
;;
srlz.d
rsm (1<<13)
mov r1 = cr.irr0 // no DV here
;;
srlz.d
// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp
mov psr.l = r0
br.ret.sptk b0
;;
// PSR.mc (rfi is the only writer)
// PSR.mfh
mov f32 = f33
mov r0 = psr
;;
// PSR.mfl
mov f2 = f3
mov r0 = psr
;;
// PSR.pk
rsm (1<<15)
ld8 r0 = [r1]
;;
rsm (1<<15)
mov r2 = psr
;;
// PSR.pp
rsm (1<<21)
mov r0 = psr
;;
// PSR.ri (no DV semantics)
// PSR.rt
mov psr.l = r0
flushrs
;;
srlz.d
// PSR.si
rsm (1<<23)
mov r0 = ar.itc
;;
ssm (1<<23)
mov r1 = ar.ec // no DV here
;;
// PSR.sp
ssm (1<<20)
mov r0 = pmd[r1]
;;
ssm (1<<20)
rum 0xff
;;
ssm (1<<20)
mov r0 = rr[r1]
;;
// PSR.ss (rfi is the only writer)
// PSR.tb
mov psr.l = r0
chk.s r0, L
;;
// PSR.up
rsm (1<<2)
mov r0 = psr.um
;;
srlz.d
// RR#
mov rr[r0] = r1
ld8 r2 = [r0] // data
;;
mov rr[r4] = r5
mov r6 = rr[r7] // impliedf
;;
// RSE
L:

21
gas/testsuite/gas/ia64/dv-safe.d Normal file
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@ -0,0 +1,21 @@
# as: -xexplicit
# objdump: -d
# name ia64 dv-safe
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <start>:
0: 02 08 04 04 02 38 \[MII\] cmp\.eq p1,p2=r1,r2
6: 30 18 10 08 70 00 cmp\.eq p3,p4=r3,r4;;
c: 00 00 04 00 nop\.i 0x0
10: 10 00 00 00 01 00 \[MIB\] nop\.m 0x0
16: 00 00 00 02 80 21 nop\.i 0x0
1c: 30 00 00 50 \(p03\) br\.call\.sptk\.few b1=40 <L>
20: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2
26: 40 28 00 00 c2 a1 \(p02\) mov r4=5
2c: 00 30 00 84 \(p03\) mov r5=r6
30: 81 28 00 0e 00 21 \[MII\] \(p04\) mov r5=r7
36: 00 00 00 02 00 00 nop\.i 0x0
3c: 00 00 04 00 nop\.i 0x0;;

19
gas/testsuite/gas/ia64/dv-safe.s Normal file
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@ -0,0 +1,19 @@
//
// Test predicate safety across calls
//
.text
start:
// user annotation
.pred.safe_across_calls p1-p4
.pred.safe_across_calls p1,p2,p3,p4
.pred.safe_across_calls p1-p2,p3-p4
.pred.safe_across_calls p1-p3,p4
cmp.eq p1, p2 = r1, r2
cmp.eq p3, p4 = r3, r4 ;;
(p3) br.call.sptk b1 = L
(p1) mov r4 = 2
(p2) mov r4 = 5
(p3) mov r5 = r6
(p4) mov r5 = r7
L:

24
gas/testsuite/gas/ia64/dv-srlz.d Normal file
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@ -0,0 +1,24 @@
# as: -xauto
# objdump: -d
# name ia64 dv-srlz
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <start>:
0: 0a 00 00 02 34 04 \[MMI\] ptc\.e r1;;
6: 00 00 00 60 00 00 srlz\.d
c: 00 00 04 00 nop\.i 0x0
10: 11 00 00 00 18 10 \[MIB\] ld8 r0=\[r0\]
16: 00 00 00 02 00 00 nop\.i 0x0
1c: 00 00 20 00 rfi;;
20: 0b 00 00 02 34 04 \[MMI\] ptc\.e r1;;
26: 00 00 00 62 00 00 srlz\.i
2c: 00 00 04 00 nop\.i 0x0;;
30: 13 00 00 00 01 00 \[MBB\] nop\.m 0x0
36: 00 00 00 20 00 00 epc
3c: 00 00 00 20 nop\.b 0x0;;
40: 11 00 00 00 01 00 \[MIB\] nop\.m 0x0
46: 00 00 00 02 00 00 nop\.i 0x0
4c: 00 00 20 00 rfi;;

13
gas/testsuite/gas/ia64/dv-srlz.s Normal file
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@ -0,0 +1,13 @@
//
// Auto-insertion of instruction and data serialization
//
.text
start:
// Requires data serialization
ptc.e r1
ld8 r1 = [r2]
rfi
// Requires instruction serialization
ptc.e r1
epc
rfi

3
gas/testsuite/gas/ia64/dv-war-err.l Normal file
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@ -0,0 +1,3 @@
.*: Assembler messages:
.*:8: Warning: Use of 'br.wtop.sptk' .* WAR dependency 'PR63' \(impliedf\)
.*:7: Warning: This is the location of the conflicting usage

9
gas/testsuite/gas/ia64/dv-war-err.s Normal file
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@ -0,0 +1,9 @@
//
// Detect WAR violations. Cases taken from DV tables.
//
.text
.explicit
// PR63
(p63) br.cond.sptk b0
br.wtop.sptk L
L:

353
gas/testsuite/gas/ia64/dv-waw-err.l Normal file
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.*: Assembler messages:
.*:8: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSP\]' \(impliedf\)
.*:7: Warning: This is the location of the conflicting usage
.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSP\]' \(impliedf\)
.*:11: Warning: This is the location of the conflicting usage
.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[BSPSTORE\]' \(impliedf\)
.*:11: Warning: This is the location of the conflicting usage
.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RNAT\]' \(impliedf\)
.*:11: Warning: This is the location of the conflicting usage
.*:12: Warning: Use of 'mov\.m' .* RAW dependency 'RSE' \(impliedf\)
.*:11: Warning: This is the location of the conflicting usage
.*:12: Warning: Use of 'mov\.m' .* WAW dependency 'RSE' \(impliedf\)
.*:11: Warning: This is the location of the conflicting usage
.*:17: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[CCV\]' \(impliedf\)
.*:16: Warning: This is the location of the conflicting usage
.*:22: Warning: Use of 'mov\.i' .* WAW dependency 'AR\[EC\]' \(impliedf\)
.*:21: Warning: This is the location of the conflicting usage
.*:27: Warning: Use of 'fsetc\.s0' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:26: Warning: This is the location of the conflicting usage
.*:27: Warning: Use of 'fsetc\.s0' .* WAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:26: Warning: This is the location of the conflicting usage
.*:32: Warning: Use of 'fsetc\.s1' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:31: Warning: This is the location of the conflicting usage
.*:32: Warning: Use of 'fsetc\.s1' .* WAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\)
.*:31: Warning: This is the location of the conflicting usage
.*:37: Warning: Use of 'fsetc\.s2' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:36: Warning: This is the location of the conflicting usage
.*:37: Warning: Use of 'fsetc\.s2' .* WAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\)
.*:36: Warning: This is the location of the conflicting usage
.*:42: Warning: Use of 'fsetc\.s3' .* RAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:41: Warning: This is the location of the conflicting usage
.*:42: Warning: Use of 'fsetc\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
.*:41: Warning: This is the location of the conflicting usage
.*:50: Warning: Use of 'fclrf\.s0' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
.*:49: Warning: This is the location of the conflicting usage
.*:58: Warning: Use of 'fclrf\.s1' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
.*:57: Warning: This is the location of the conflicting usage
.*:66: Warning: Use of 'fclrf\.s2' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
.*:65: Warning: This is the location of the conflicting usage
.*:74: Warning: Use of 'fclrf\.s3' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
.*:73: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.controls' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.controls' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.controls' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.controls' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf0\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf1\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf2\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.sf3\.flags' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.rv' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:79: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[FPSR\]\.traps' \(impliedf\)
.*:78: Warning: This is the location of the conflicting usage
.*:84: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[ITC\]' \(impliedf\)
.*:83: Warning: This is the location of the conflicting usage
.*:89: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[K%\], % in 0 - 7' \(impliedf\), specific resource number is 2
.*:88: Warning: This is the location of the conflicting usage
.*:94: Warning: Use of 'mov\.i' .* WAW dependency 'AR\[LC\]' \(impliedf\)
.*:93: Warning: This is the location of the conflicting usage
.*:99: Warning: Use of 'br\.call\.sptk' .* WAW dependency 'AR\[PFS\]' \(impliedf\)
.*:98: Warning: This is the location of the conflicting usage
.*:104: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RNAT\]' \(impliedf\)
.*:103: Warning: This is the location of the conflicting usage
.*:109: Warning: Use of 'mov\.m' .* WAW dependency 'AR\[RSC\]' \(impliedf\)
.*:108: Warning: This is the location of the conflicting usage
.*:114: Warning: Use of 'st8\.spill' .* WAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\)
.*:113: Warning: This is the location of the conflicting usage
.*:119: Warning: Use of 'mov\.m' .* WAW dependency 'AR%, % in 48 - 63, 112-127' \(impliedf\), specific resource number is 48
.*:118: Warning: This is the location of the conflicting usage
.*:124: Warning: Use of 'mov' .* WAW dependency 'BR%, % in 0 - 7' \(impliedf\), specific resource number is 1
.*:123: Warning: This is the location of the conflicting usage
.*:129: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'AR\[EC\]' \(impliedf\)
.*:128: Warning: This is the location of the conflicting usage
.*:129: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'CFM' \(impliedf\)
.*:128: Warning: This is the location of the conflicting usage
.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'AR\[EC\]' \(impliedf\)
.*:128: Warning: This is the location of the conflicting usage
.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'CFM' \(impliedf\)
.*:128: Warning: This is the location of the conflicting usage
.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
.*:128: Warning: This is the location of the conflicting usage
.*:129: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
.*:128: Warning: This is the location of the conflicting usage
.*:134: Warning: Use of 'mov' .* WAW dependency 'CR\[CMCV\]' \(impliedf\)
.*:133: Warning: This is the location of the conflicting usage
.*:139: Warning: Use of 'mov' .* WAW dependency 'CR\[DCR\]' \(impliedf\)
.*:138: Warning: This is the location of the conflicting usage
.*:144: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
.*:143: Warning: This is the location of the conflicting usage
.*:144: Warning: Use of 'mov' .* WAW dependency 'CR\[EOI\]' \(other\)
.*:143: Warning: This is the location of the conflicting usage
.*:144: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:143: Warning: This is the location of the conflicting usage
.*:150: Warning: Use of 'mov' .* WAW dependency 'CR\[GPTA\]' \(impliedf\)
.*:149: Warning: This is the location of the conflicting usage
.*:155: Warning: Use of 'mov' .* WAW dependency 'CR\[IFA\]' \(impliedf\)
.*:154: Warning: This is the location of the conflicting usage
.*:160: Warning: Use of 'cover' .* WAW dependency 'CR\[IFS\]' \(impliedf\)
.*:159: Warning: This is the location of the conflicting usage
.*:165: Warning: Use of 'mov' .* WAW dependency 'CR\[IHA\]' \(impliedf\)
.*:164: Warning: This is the location of the conflicting usage
.*:170: Warning: Use of 'mov' .* WAW dependency 'CR\[IIM\]' \(impliedf\)
.*:169: Warning: This is the location of the conflicting usage
.*:175: Warning: Use of 'mov' .* WAW dependency 'CR\[IIP\]' \(impliedf\)
.*:174: Warning: This is the location of the conflicting usage
.*:180: Warning: Use of 'mov' .* WAW dependency 'CR\[IIPA\]' \(impliedf\)
.*:179: Warning: This is the location of the conflicting usage
.*:185: Warning: Use of 'mov' .* WAW dependency 'CR\[IPSR\]' \(impliedf\)
.*:184: Warning: This is the location of the conflicting usage
.*:190: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(impliedf\)
.*:189: Warning: This is the location of the conflicting usage
.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 71
.*:189: Warning: This is the location of the conflicting usage
.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 70
.*:189: Warning: This is the location of the conflicting usage
.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 69
.*:189: Warning: This is the location of the conflicting usage
.*:190: Warning: Use of 'mov' .* WAW dependency 'CR\[IRR%\], % in 0 - 3' \(impliedf\), specific resource number is 68
.*:189: Warning: This is the location of the conflicting usage
.*:190: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:189: Warning: This is the location of the conflicting usage
.*:195: Warning: Use of 'mov' .* WAW dependency 'CR\[ISR\]' \(impliedf\)
.*:194: Warning: This is the location of the conflicting usage
.*:200: Warning: Use of 'mov' .* WAW dependency 'CR\[ITIR\]' \(impliedf\)
.*:199: Warning: This is the location of the conflicting usage
.*:205: Warning: Use of 'mov' .* WAW dependency 'CR\[ITM\]' \(impliedf\)
.*:204: Warning: This is the location of the conflicting usage
.*:210: Warning: Use of 'mov' .* WAW dependency 'CR\[ITV\]' \(impliedf\)
.*:209: Warning: This is the location of the conflicting usage
.*:215: Warning: Use of 'mov' .* WAW dependency 'CR\[IVA\]' \(impliedf\)
.*:214: Warning: This is the location of the conflicting usage
.*:222: Warning: Use of 'mov' .* WAW dependency 'CR\[LID\]' \(other\)
.*:221: Warning: This is the location of the conflicting usage
.*:230: Warning: Use of 'mov' .* WAW dependency 'CR\[LRR%\], % in 0 - 1' \(impliedf\), specific resource number is 80
.*:229: Warning: This is the location of the conflicting usage
.*:235: Warning: Use of 'mov' .* WAW dependency 'CR\[PMV\]' \(impliedf\)
.*:234: Warning: This is the location of the conflicting usage
.*:240: Warning: Use of 'mov' .* WAW dependency 'CR\[PTA\]' \(impliedf\)
.*:239: Warning: This is the location of the conflicting usage
.*:245: Warning: Use of 'mov' .* WAW dependency 'CR\[TPR\]' \(impliedf\)
.*:244: Warning: This is the location of the conflicting usage
.*:250: Warning: Use of 'mov' .* WAW dependency 'DBR#' \(impliedf\)
.*:249: Warning: This is the location of the conflicting usage
.*:259: Warning: Use of 'itc\.i' .* RAW dependency 'DTC' \(impliedf\)
.*:258: Warning: This is the location of the conflicting usage
.*:259: Warning: Use of 'itc\.i' .* RAW dependency 'ITC' \(impliedf\)
.*:258: Warning: This is the location of the conflicting usage
.*:259: Warning: Use of 'itc\.i' .* WAW dependency 'DTC' \(impliedf\)
.*:258: Warning: This is the location of the conflicting usage
.*:259: Warning: Use of 'itc\.i' .* WAW dependency 'ITC' \(impliedf\)
.*:258: Warning: This is the location of the conflicting usage
.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'DTC' \(impliedf\)
.*:270: Warning: This is the location of the conflicting usage
.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'DTR' \(impliedf\)
.*:270: Warning: This is the location of the conflicting usage
.*:271: Warning: Use of 'ptr\.d' .* RAW dependency 'ITC' \(impliedf\)
.*:270: Warning: This is the location of the conflicting usage
.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'DTC' \(impliedf\)
.*:270: Warning: This is the location of the conflicting usage
.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'DTR' \(impliedf\)
.*:270: Warning: This is the location of the conflicting usage
.*:271: Warning: Use of 'ptr\.d' .* WAW dependency 'ITC' \(impliedf\)
.*:270: Warning: This is the location of the conflicting usage
.*:277: Warning: Use of 'ldfs\.c\.clr' .* WAW dependency 'FR%, % in 2 - 127' \(impliedf\), specific resource number is 3
.*:276: Warning: This is the location of the conflicting usage
.*:282: Warning: Use of 'ld8\.c\.clr' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 2
.*:281: Warning: This is the location of the conflicting usage
.*:287: Warning: Use of 'mov' .* WAW dependency 'IBR#' \(impliedf\)
.*:286: Warning: This is the location of the conflicting usage
.*:292: Warning: Use of 'mov' .* RAW dependency 'InService\*' \(data\)
.*:291: Warning: This is the location of the conflicting usage
.*:292: Warning: Use of 'mov' .* WAW dependency 'InService\*' \(other\)
.*:291: Warning: This is the location of the conflicting usage
.*:298: Warning: Use of 'itc\.i' .* RAW dependency 'DTC' \(impliedf\)
.*:297: Warning: This is the location of the conflicting usage
.*:298: Warning: Use of 'itc\.i' .* RAW dependency 'ITC' \(impliedf\)
.*:297: Warning: This is the location of the conflicting usage
.*:298: Warning: Use of 'itc\.i' .* WAW dependency 'DTC' \(impliedf\)
.*:297: Warning: This is the location of the conflicting usage
.*:298: Warning: Use of 'itc\.i' .* WAW dependency 'ITC' \(impliedf\)
.*:297: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'DTC' \(impliedf\)
.*:304: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'ITC' \(impliedf\)
.*:304: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'ptr\.i' .* RAW dependency 'ITR' \(impliedf\)
.*:304: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'DTC' \(impliedf\)
.*:304: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'ITC' \(impliedf\)
.*:304: Warning: This is the location of the conflicting usage
.*:305: Warning: Use of 'ptr\.i' .* WAW dependency 'ITR' \(impliedf\)
.*:304: Warning: This is the location of the conflicting usage
.*:317: Warning: Use of 'mov' .* WAW dependency 'PKR#' \(impliedf\), specific resource number is 1
.*:316: Warning: This is the location of the conflicting usage
.*:322: Warning: Use of 'mov' .* WAW dependency 'PMC#' \(impliedf\)
.*:321: Warning: This is the location of the conflicting usage
.*:327: Warning: Use of 'mov' .* WAW dependency 'PMD#' \(impliedf\)
.*:326: Warning: This is the location of the conflicting usage
.*:332: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:331: Warning: This is the location of the conflicting usage
.*:332: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:331: Warning: This is the location of the conflicting usage
.*:335: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:334: Warning: This is the location of the conflicting usage
.*:335: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:334: Warning: This is the location of the conflicting usage
.*:338: Warning: Use of 'cmp\.eq\.or' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:337: Warning: This is the location of the conflicting usage
.*:341: Warning: Use of 'cmp\.eq\.and' .* WAW dependency 'PR%, % in 1 - 62' \(impliedf\), specific resource number is 1
.*:340: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'AR\[EC\]' \(impliedf\)
.*:351: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.wtop\.sptk' .* RAW dependency 'CFM' \(impliedf\)
.*:351: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'AR\[EC\]' \(impliedf\)
.*:351: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'CFM' \(impliedf\)
.*:351: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
.*:351: Warning: This is the location of the conflicting usage
.*:352: Warning: Use of 'br\.wtop\.sptk' .* WAW dependency 'PR63' \(impliedf\)
.*:351: Warning: This is the location of the conflicting usage
.*:355: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
.*:354: Warning: This is the location of the conflicting usage
.*:355: Warning: Use of 'cmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
.*:354: Warning: This is the location of the conflicting usage
.*:358: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
.*:357: Warning: This is the location of the conflicting usage
.*:358: Warning: Use of 'fcmp\.eq' .* WAW dependency 'PR63' \(impliedf\)
.*:357: Warning: This is the location of the conflicting usage
.*:361: Warning: Use of 'cmp\.eq\.or' .* WAW dependency 'PR63' \(impliedf\)
.*:360: Warning: This is the location of the conflicting usage
.*:364: Warning: Use of 'cmp\.eq\.and' .* WAW dependency 'PR63' \(impliedf\)
.*:363: Warning: This is the location of the conflicting usage
.*:375: Warning: Use of 'rum' .* WAW dependency 'PSR\.ac' \(impliedf\)
.*:374: Warning: This is the location of the conflicting usage
.*:380: Warning: Use of 'rum' .* WAW dependency 'PSR\.be' \(impliedf\)
.*:379: Warning: This is the location of the conflicting usage
.*:390: Warning: Use of 'br\.ret\.sptk' .* WAW dependency 'PSR\.cpl' \(impliedf\)
.*:389: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.ac' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.be' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.db' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dfh' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dfl' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.di' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.dt' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.i' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.ic' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.lp' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.pk' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.pp' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.rt' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.si' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.sp' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.tb' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:396: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\)
.*:395: Warning: This is the location of the conflicting usage
.*:404: Warning: Use of 'ssm' .* WAW dependency 'PSR\.dfh' \(impliedf\)
.*:403: Warning: This is the location of the conflicting usage
.*:410: Warning: Use of 'ssm' .* WAW dependency 'PSR\.dfl' \(impliedf\)
.*:409: Warning: This is the location of the conflicting usage
.*:416: Warning: Use of 'rsm' .* WAW dependency 'PSR\.di' \(impliedf\)
.*:415: Warning: This is the location of the conflicting usage
.*:421: Warning: Use of 'rsm' .* WAW dependency 'PSR\.dt' \(impliedf\)
.*:420: Warning: This is the location of the conflicting usage
.*:427: Warning: Use of 'ssm' .* WAW dependency 'PSR\.i' \(impliedf\)
.*:426: Warning: This is the location of the conflicting usage
.*:433: Warning: Use of 'ssm' .* WAW dependency 'PSR\.ic' \(impliedf\)
.*:432: Warning: This is the location of the conflicting usage
.*:444: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfh' \(impliedf\)
.*:443: Warning: This is the location of the conflicting usage
.*:447: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:446: Warning: This is the location of the conflicting usage
.*:447: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:446: Warning: This is the location of the conflicting usage
.*:450: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:449: Warning: This is the location of the conflicting usage
.*:450: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:449: Warning: This is the location of the conflicting usage
.*:453: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:452: Warning: This is the location of the conflicting usage
.*:453: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfh' \(impliedf\)
.*:452: Warning: This is the location of the conflicting usage
.*:461: Warning: Use of 'mov' .* RAW dependency 'PSR\.mfl' \(impliedf\)
.*:460: Warning: This is the location of the conflicting usage
.*:464: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:463: Warning: This is the location of the conflicting usage
.*:464: Warning: Use of 'ssm' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:463: Warning: This is the location of the conflicting usage
.*:467: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:466: Warning: This is the location of the conflicting usage
.*:467: Warning: Use of 'mov' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:466: Warning: This is the location of the conflicting usage
.*:470: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:469: Warning: This is the location of the conflicting usage
.*:470: Warning: Use of 'rum' .* WAW dependency 'PSR\.mfl' \(impliedf\)
.*:469: Warning: This is the location of the conflicting usage
.*:478: Warning: Use of 'rsm' .* WAW dependency 'PSR\.pk' \(impliedf\)
.*:477: Warning: This is the location of the conflicting usage
.*:483: Warning: Use of 'rsm' .* WAW dependency 'PSR\.pp' \(impliedf\)
.*:482: Warning: This is the location of the conflicting usage
.*:491: Warning: Use of 'ssm' .* WAW dependency 'PSR\.si' \(impliedf\)
.*:490: Warning: This is the location of the conflicting usage
.*:496: Warning: Use of 'rsm' .* WAW dependency 'PSR\.sp' \(impliedf\)
.*:495: Warning: This is the location of the conflicting usage
.*:505: Warning: Use of 'rsm' .* WAW dependency 'PSR\.up' \(impliedf\)
.*:504: Warning: This is the location of the conflicting usage
.*:508: Warning: Use of 'mov' .* WAW dependency 'PSR\.up' \(impliedf\)
.*:507: Warning: This is the location of the conflicting usage
.*:513: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\)
.*:512: Warning: This is the location of the conflicting usage

516
gas/testsuite/gas/ia64/dv-waw-err.s Normal file
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@ -0,0 +1,516 @@
//
// Detect WAW violations. Cases taken from DV tables.
//
.text
.explicit
// AR[BSP]
mov ar.bsp = r0
mov ar.bsp = r1
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov ar.bspstore = r3
;;
// AR[CCV]
mov ar.ccv = r4
mov ar.ccv = r4
;;
// AR[EC]
br.wtop.sptk L
mov ar.ec = r0
;;
// AR[FPSR].sf0.controls
mov ar.fpsr = r0
fsetc.s0 0x7f, 0x0f
;;
// AR[FPSR].sf1.controls
mov ar.fpsr = r0
fsetc.s1 0x7f, 0x0f
;;
// AR[FPSR].sf2.controls
mov ar.fpsr = r0
fsetc.s2 0x7f, 0x0f
;;
// AR[FPSR].sf3.controls
mov ar.fpsr = r0
fsetc.s3 0x7f, 0x0f
;;
// AR[FPSR].sf0.flags
fcmp.eq.s0 p1, p2 = f3, f4
fcmp.eq.s0 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s0 p1, p2 = f3, f4
fclrf.s0
;;
// AR[FPSR].sf1.flags
fcmp.eq.s1 p1, p2 = f3, f4
fcmp.eq.s1 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s1 p1, p2 = f3, f4
fclrf.s1
;;
// AR[FPSR].sf2.flags
fcmp.eq.s2 p1, p2 = f3, f4
fcmp.eq.s2 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s2 p1, p2 = f3, f4
fclrf.s2
;;
// AR[FPSR].sf3.flags
fcmp.eq.s3 p1, p2 = f3, f4
fcmp.eq.s3 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s3 p1, p2 = f3, f4
fclrf.s3
;;
// AR[FPSR].traps/rv plus all controls/flags
mov ar.fpsr = r0
mov ar.fpsr = r0
;;
// AR[ITC]
mov ar.itc = r1
mov ar.itc = r1
;;
// AR[K]
mov ar.k2 = r3
mov ar.k2 = r3
;;
// AR[LC]
br.cloop.sptk L
mov ar.lc = r0
;;
// AR[PFS]
mov ar.pfs = r0
br.call.sptk b0 = L
;;
// AR[RNAT] (see also AR[BSPSTORE])
mov ar.rnat = r8
mov ar.rnat = r8
;;
// AR[RSC]
mov ar.rsc = r10
mov ar.rsc = r10
;;
// AR[UNAT]
mov ar.unat = r12
st8.spill [r0] = r1
;;
// AR%
mov ar48 = r0
mov ar48 = r0
;;
// BR%
mov b1 = r0
mov b1 = r1
;;
// CFM (and others)
br.wtop.sptk L
br.wtop.sptk L
;;
// CR[CMCV]
mov cr.cmcv = r1
mov cr.cmcv = r2
;;
// CR[DCR]
mov cr.dcr = r3
mov cr.dcr = r3
;;
// CR[EOI] (and InService)
mov cr.eoi = r0
mov cr.eoi = r0
;;
srlz.d
// CR[GPTA]
mov cr.gpta = r6
mov cr.gpta = r7
;;
// CR[IFA]
mov cr.ifa = r9
mov cr.ifa = r10
;;
// CR[IFS]
mov cr.ifs = r11
cover
;;
// CR[IHA]
mov cr.iha = r13
mov cr.iha = r14
;;
// CR[IIM]
mov cr.iim = r15
mov cr.iim = r16
;;
// CR[IIP]
mov cr.iip = r17
mov cr.iip = r17
;;
// CR[IIPA]
mov cr.iipa = r19
mov cr.iipa = r20
;;
// CR[IPSR]
mov cr.ipsr = r21
mov cr.ipsr = r22
;;
// CR[IRR%] (and others)
mov r0 = cr.ivr
mov r1 = cr.ivr
;;
// CR[ISR]
mov cr.isr = r24
mov cr.isr = r25
;;
// CR[ITIR]
mov cr.itir = r26
mov cr.itir = r27
;;
// CR[ITM]
mov cr.itm = r28
mov cr.itm = r29
;;
// CR[ITV]
mov cr.itv = r0
mov cr.itv = r1
;;
// CR[IVA]
mov cr.iva = r0
mov cr.iva = r1
;;
// CR[IVR] (no explicit writers)
// CR[LID]
mov cr.lid = r0
mov cr.lid = r1
;;
// CR[LRR%]
mov cr.lrr0 = r0
mov cr.lrr1 = r0 // no DV here
;;
mov cr.lrr0 = r0
mov cr.lrr0 = r0
;;
// CR[PMV]
mov cr.pmv = r0
mov cr.pmv = r1
;;
// CR[PTA]
mov cr.pta = r0
mov cr.pta = r1
;;
// CR[TPR]
mov cr.tpr = r0
mov cr.tpr = r1
;;
// DBR#
mov dbr[r1] = r1
mov dbr[r1] = r2
;;
srlz.d
// DTC
ptc.e r0
ptc.e r1 // no DVs here
;;
ptc.e r0 // (and others)
itc.i r0
;;
srlz.d
// DTC_LIMIT
ptc.g r0, r1 // NOTE: GAS automatically emits stops after
ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
;; // longer possible in GAS-generated assembly
srlz.d
// DTR
itr.d dtr[r0] = r1 // (and others)
ptr.d r2, r3
;;
srlz.d
// FR%
mov f3 = f2
ldfs.c.clr f3 = [r1]
;;
// GR%
mov r2 = r0
ld8.c.clr r2 = [r1]
;;
// IBR#
mov ibr[r0] = r2
mov ibr[r1] = r2
;;
// InService
mov cr.eoi = r0
mov r1 = cr.ivr
;;
srlz.d
// ITC
ptc.e r0
itc.i r1
;;
srlz.i
;;
// ITR
itr.i itr[r0] = r1
ptr.i r2, r3
;;
srlz.i
;;
// PKR#
.reg.val r1, 0x1
.reg.val r2, ~0x1
mov pkr[r1] = r1
mov pkr[r2] = r1 // no DV here
;;
mov pkr[r1] = r1
mov pkr[r1] = r1
;;
// PMC#
mov pmc[r3] = r1
mov pmc[r4] = r1
;;
// PMD#
mov pmd[r3] = r1
mov pmd[r4] = r1
;;
// PR%
cmp.eq p1, p0 = r0, r1
cmp.eq p1, p0 = r2, r3
;;
fcmp.eq p1, p2 = f2, f3
fcmp.eq p1, p3 = f2, f3
;;
cmp.eq.and p1, p2 = r0, r1
cmp.eq.or p1, p3 = r2, r3
;;
cmp.eq.or p1, p3 = r2, r3
cmp.eq.and p1, p2 = r0, r1
;;
cmp.eq.and p1, p2 = r0, r1
cmp.eq.and p1, p3 = r2, r3 // no DV here
;;
cmp.eq.or p1, p2 = r0, r1
cmp.eq.or p1, p3 = r2, r3 // no DV here
;;
// PR63
br.wtop.sptk L
br.wtop.sptk L
;;
cmp.eq p63, p0 = r0, r1
cmp.eq p63, p0 = r2, r3
;;
fcmp.eq p63, p2 = f2, f3
fcmp.eq p63, p3 = f2, f3
;;
cmp.eq.and p63, p2 = r0, r1
cmp.eq.or p63, p3 = r2, r3
;;
cmp.eq.or p63, p3 = r2, r3
cmp.eq.and p63, p2 = r0, r1
;;
cmp.eq.and p63, p2 = r0, r1
cmp.eq.and p63, p3 = r2, r3 // no DV here
;;
cmp.eq.or p63, p2 = r0, r1
cmp.eq.or p63, p3 = r2, r3 // no DV here
;;
// PSR.ac
rum (1<<3)
rum (1<<3)
;;
// PSR.be
rum (1<<1)
rum (1<<1)
;;
// PSR.bn
bsw.0 // GAS automatically emits a stop after bsw.n
bsw.0 // so this conflict is avoided
;;
// PSR.cpl
epc
br.ret.sptk b0
;;
// PSR.da (rfi is the only writer)
// PSR.db (and others)
mov psr.l = r0
mov psr.l = r1
;;
srlz.d
// PSR.dd (rfi is the only writer)
// PSR.dfh
ssm (1<<19)
ssm (1<<19)
;;
srlz.d
// PSR.dfl
ssm (1<<18)
ssm (1<<18)
;;
srlz.d
// PSR.di
rsm (1<<22)
rsm (1<<22)
;;
// PSR.dt
rsm (1<<17)
rsm (1<<17)
;;
// PSR.ed (rfi is the only writer)
// PSR.i
ssm (1<<14)
ssm (1<<14)
;;
// PSR.ia (no DV semantics)
// PSR.ic
ssm (1<<13)
ssm (1<<13)
;;
// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp (see PSR.db)
// PSR.mc (rfi is the only writer)
// PSR.mfh
mov f32 = f33
mov r0 = psr
;;
ssm (1<<5)
ssm (1<<5)
;;
ssm (1<<5)
mov psr.um = r0
;;
rum (1<<5)
rum (1<<5)
;;
mov f32 = f33
mov f34 = f35 // no DV here
;;
// PSR.mfl
mov f2 = f3
mov r0 = psr
;;
ssm (1<<4)
ssm (1<<4)
;;
ssm (1<<4)
mov psr.um = r0
;;
rum (1<<4)
rum (1<<4)
;;
mov f2 = f3
mov f4 = f5 // no DV here
;;
// PSR.pk
rsm (1<<15)
rsm (1<<15)
;;
// PSR.pp
rsm (1<<21)
rsm (1<<21)
;;
// PSR.ri (no DV semantics)
// PSR.rt (see PSR.db)
// PSR.si
rsm (1<<23)
ssm (1<<23)
;;
// PSR.sp
ssm (1<<20)
rsm (1<<20)
;;
srlz.d
// PSR.ss (rfi is the only writer)
// PSR.tb (see PSR.db)
// PSR.up
rsm (1<<2)
rsm (1<<2)
;;
rum (1<<2)
mov psr.um = r0
;;
// RR#
mov rr[r2] = r1
mov rr[r2] = r3
;;
// RSE
L:

12
gas/testsuite/gas/ia64/fixup-dump.pl Normal file
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@ -0,0 +1,12 @@
print "# objdump: -d\n";
print "# name: ia64 $ARGV[0]\n";
shift;
while (<>) {
if (/.*file format.*/) {
$_ = ".*: +file format .*\n";
} else {
s/([][().])/\\$1/g;
}
print;
}

38
gas/testsuite/gas/ia64/ia64.exp Normal file
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@ -0,0 +1,38 @@
#
# ia64 tests
#
proc run_list_test { name opts } {
global srcdir subdir
set testname "ia64 $name"
set file $srcdir/$subdir/$name
gas_run ${name}.s $opts ">&dump.out"
if { [regexp_diff "dump.out" "${file}.l"] } then {
fail $testname
verbose "output is [file_contents "dump.out"]" 2
return
}
pass $testname
}
if [istarget "ia64-*"] then {
run_dump_test "regs"
run_dump_test "opc-a"
run_list_test "opc-a-err" ""
run_dump_test "opc-b"
run_dump_test "opc-f"
run_dump_test "opc-i"
run_dump_test "opc-m"
run_dump_test "opc-x"
run_list_test "dv-raw-err" ""
run_list_test "dv-waw-err" ""
run_list_test "dv-war-err" ""
run_list_test "dv-entry-err" ""
run_list_test "dv-mutex-err" ""
run_dump_test "dv-branch"
run_dump_test "dv-imply"
run_dump_test "dv-mutex"
run_dump_test "dv-safe"
run_dump_test "dv-srlz"
}

18
gas/testsuite/gas/ia64/opc-a-err.l Normal file
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.*: Assembler messages:
.*:1: Error: Operand 2 of `adds' should be a 14-bit .*
.*:2: Error: Operand 2 of `adds' should be a 14-bit .*
.*:4: Error: Operand 2 of `addl' should be a 22-bit .*
.*:5: Error: Operand 2 of `addl' should be a 22-bit .*
.*:6: Error: Operand 3 of `addl' should be a general register r0-r3
.*:8: Error: Operand 2 of `sub' should be .*
.*:9: Error: Operand 2 of `sub' should be .*
.*:11: Error: Operand 2 of `and' should be .*
.*:12: Error: Operand 2 of `and' should be .*
.*:14: Error: Operand 2 of `or' should be .*
.*:15: Error: Operand 2 of `or' should be .*
.*:17: Error: Operand 2 of `xor' should be .*
.*:18: Error: Operand 2 of `xor' should be .*
.*:20: Error: Operand 2 of `andcm' should be .*
.*:21: Error: Operand 2 of `andcm' should be .*
.*:23: Error: Operand 3 of `cmp4.lt.or' should be r0
.*:24: Error: Operand 3 of `cmp4.lt.or' should be r0

24
gas/testsuite/gas/ia64/opc-a-err.s Normal file
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@ -0,0 +1,24 @@
adds r25 = -0x2001, r10
adds r26 = 0x2000, r10
addl r37 = -0x200001, r1
addl r38 = 0x200000, r1
addl r30 = 0, r10
sub r2 = 128, r3
sub r3 = -129, r4
and r8 = 129, r9
and r3 = -129, r4
or r8 = 129, r9
or r3 = -129, r4
xor r8 = 129, r9
xor r3 = -129, r4
andcm r8 = 129, r9
andcm r3 = -129, r4
cmp4.lt.or p2, p3 = r1, r4
cmp4.lt.or p2, p3 = 1, r4

290
gas/testsuite/gas/ia64/opc-a.d Normal file
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# objdump: -d
# name: ia64 opc-a
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <_start>:
0: 00 28 9b cf 00 60 \[MII\] add r101=r102,r103
6: 80 4e ab 01 40 60 \(p01\) add r104=r105,r106
c: cd 6e 07 80 add r107=r108,r109,1
10: 40 70 bf e1 01 20 \[MII\] \(p02\) add r110=r111,r112,1
16: 40 01 28 00 c2 a0 mov r20=r10
1c: 12 50 00 84 \(p01\) adds r21=1,r10
20: 00 b0 fc 15 3f 23 \[MII\] adds r22=-1,r10
26: 70 01 28 00 46 01 adds r23=-8192,r10
2c: f3 57 fc 84 \(p02\) adds r24=8191,r10
30: 00 f0 00 02 00 24 \[MII\] addl r30=0,r1
36: f0 09 04 00 c8 00 addl r31=1,r1
3c: f4 ef ff 9f \(p01\) addl r32=-1,r1
40: 00 08 01 fa c0 27 \[MII\] addl r33=-8192,r1
46: 20 fa 07 7e 48 60 addl r34=8191,r1
4c: 04 08 00 98 addl r35=-2097152,r1
50: 00 20 fd fb ff 25 \[MII\] addl r36=2097151,r1
56: b0 00 28 00 42 80 mov r11=r10
5c: 41 53 90 84 adds r12=4660,r10
60: 00 68 d0 02 24 24 \[MII\] addl r13=4660,r1
66: e0 28 16 8c 48 80 addl r14=74565,r1
6c: 32 50 20 80 addp4 r20=r3,r10
70: 20 a8 04 14 80 21 \[MII\] \(p01\) addp4 r21=1,r10
76: 60 f9 2b 7e 47 a0 addp4 r22=-1,r10
7c: 6c 3e 17 80 sub r101=r102,r103
80: 40 70 bf e1 04 20 \[MII\] \(p02\) sub r110=r111,r112,1
86: 80 07 0c 4a 40 20 sub r120=0,r3
8c: 1f 18 94 80 sub r121=1,r3
90: 00 d0 ff 07 25 22 \[MII\] sub r122=-1,r3
96: b0 07 0c 4a 44 80 sub r123=-128,r3
9c: ff 1f 94 80 sub r124=127,r3
a0: 00 40 24 14 0c e0 \[MII\] and r8=r9,r10
a6: b0 00 30 58 44 02 \(p03\) and r11=-128,r12
ac: 91 50 38 80 \(p04\) or r8=r9,r10
b0: 00 58 00 18 2e 22 \[MII\] or r11=-128,r12
b6: 80 48 28 1e 40 60 xor r8=r9,r10
bc: 01 60 bc 88 xor r11=-128,r12
c0: 00 40 24 14 0d 20 \[MII\] andcm r8=r9,r10
c6: b0 00 30 5a 44 00 andcm r11=-128,r12
cc: e1 f9 40 80 shladd r8=r30,1,r31
d0: 00 48 78 3e 11 20 \[MII\] shladd r9=r30,2,r31
d6: a0 f0 7c 24 40 60 shladd r10=r30,3,r31
dc: e1 f9 4c 80 shladd r11=r30,4,r31
e0: 00 40 78 3e 18 20 \[MII\] shladdp4 r8=r30,1,r31
e6: 90 f0 7c 32 40 40 shladdp4 r9=r30,2,r31
ec: e1 f9 68 80 shladdp4 r10=r30,3,r31
f0: 00 58 78 3e 1b 20 \[MII\] shladdp4 r11=r30,4,r31
f6: a0 f0 7c 00 41 60 padd1 r10=r30,r31
fc: e1 f9 04 82 padd1\.sss r11=r30,r31
100: 00 60 78 3e 83 20 \[MII\] padd1\.uus r12=r30,r31
106: d0 f0 7c 04 41 c0 padd1\.uuu r13=r30,r31
10c: e1 f9 00 83 padd2 r14=r30,r31
110: 00 78 78 3e c1 20 \[MII\] padd2\.sss r15=r30,r31
116: 00 f1 7c 86 41 20 padd2\.uus r16=r30,r31
11c: e2 f9 08 83 padd2\.uuu r17=r30,r31
120: 00 90 78 3e 80 22 \[MII\] padd4 r18=r30,r31
126: a0 f0 7c 08 41 60 psub1 r10=r30,r31
12c: e1 f9 14 82 psub1\.sss r11=r30,r31
130: 00 60 78 3e 87 20 \[MII\] psub1\.uus r12=r30,r31
136: d0 f0 7c 0c 41 c0 psub1\.uuu r13=r30,r31
13c: e1 f9 10 83 psub2 r14=r30,r31
140: 00 78 78 3e c5 20 \[MII\] psub2\.sss r15=r30,r31
146: 00 f1 7c 8e 41 20 psub2\.uus r16=r30,r31
14c: e2 f9 18 83 psub2\.uuu r17=r30,r31
150: 00 90 78 3e 84 22 \[MII\] psub4 r18=r30,r31
156: a0 f0 7c 14 41 40 pavg1 r10=r30,r31
15c: e1 f9 2c 82 pavg1\.raz r10=r30,r31
160: 00 50 78 3e ca 20 \[MII\] pavg2 r10=r30,r31
166: a0 f0 7c 96 41 40 pavg2\.raz r10=r30,r31
16c: e1 f9 38 82 pavgsub1 r10=r30,r31
170: 00 50 78 3e ce 20 \[MII\] pavgsub2 r10=r30,r31
176: a0 f0 7c 48 41 40 pcmp1\.eq r10=r30,r31
17c: e1 f9 90 83 pcmp2\.eq r10=r30,r31
180: 00 50 78 3e a4 22 \[MII\] pcmp4\.eq r10=r30,r31
186: a0 f0 7c 4a 41 40 pcmp1\.gt r10=r30,r31
18c: e1 f9 94 83 pcmp2\.gt r10=r30,r31
190: 00 50 78 3e a5 22 \[MII\] pcmp4\.gt r10=r30,r31
196: a0 58 30 a0 41 40 pshladd2 r10=r11,1,r12
19c: b1 60 48 83 pshladd2 r10=r11,3,r12
1a0: 00 50 2c 18 d8 20 \[MII\] pshradd2 r10=r11,1,r12
1a6: a0 58 30 b2 41 40 pshradd2 r10=r11,2,r12
1ac: 30 20 0c e0 cmp\.eq p2,p3=r3,r4
1b0: 00 10 0c 08 03 39 \[MII\] cmp\.eq p2,p3=3,r4
1b6: 30 18 10 04 70 60 cmp\.eq p3,p2=r3,r4
1bc: 30 20 08 e4 cmp\.eq p3,p2=3,r4
1c0: 00 10 0c 08 03 30 \[MII\] cmp\.lt p2,p3=r3,r4
1c6: 20 18 10 06 62 60 cmp\.lt p2,p3=3,r4
1cc: 40 18 08 c0 cmp\.lt p3,p2=r4,r3
1d0: 00 10 08 08 03 31 \[MII\] cmp\.lt p2,p3=2,r4
1d6: 20 20 0c 06 60 60 cmp\.lt p2,p3=r4,r3
1dc: 20 20 08 c4 cmp\.lt p3,p2=2,r4
1e0: 00 18 0c 08 02 30 \[MII\] cmp\.lt p3,p2=r3,r4
1e6: 30 18 10 04 62 40 cmp\.lt p3,p2=3,r4
1ec: 30 20 0c d0 cmp\.ltu p2,p3=r3,r4
1f0: 00 10 0c 08 03 35 \[MII\] cmp\.ltu p2,p3=3,r4
1f6: 30 20 0c 04 68 40 cmp\.ltu p3,p2=r4,r3
1fc: 20 20 0c d4 cmp\.ltu p2,p3=2,r4
200: 00 10 10 06 03 34 \[MII\] cmp\.ltu p2,p3=r4,r3
206: 30 10 10 04 6a 60 cmp\.ltu p3,p2=2,r4
20c: 30 20 08 d0 cmp\.ltu p3,p2=r3,r4
210: 00 18 0c 08 02 35 \[MII\] cmp\.ltu p3,p2=3,r4
216: 20 1c 10 06 70 40 cmp\.eq\.unc p2,p3=r3,r4
21c: 38 20 0c e4 cmp\.eq\.unc p2,p3=3,r4
220: 00 18 0e 08 02 38 \[MII\] cmp\.eq\.unc p3,p2=r3,r4
226: 30 1c 10 04 72 40 cmp\.eq\.unc p3,p2=3,r4
22c: 38 20 0c c0 cmp\.lt\.unc p2,p3=r3,r4
230: 00 10 0e 08 03 31 \[MII\] cmp\.lt\.unc p2,p3=3,r4
236: 30 24 0c 04 60 40 cmp\.lt\.unc p3,p2=r4,r3
23c: 28 20 0c c4 cmp\.lt\.unc p2,p3=2,r4
240: 00 10 12 06 03 30 \[MII\] cmp\.lt\.unc p2,p3=r4,r3
246: 30 14 10 04 62 60 cmp\.lt\.unc p3,p2=2,r4
24c: 38 20 08 c0 cmp\.lt\.unc p3,p2=r3,r4
250: 00 18 0e 08 02 31 \[MII\] cmp\.lt\.unc p3,p2=3,r4
256: 20 1c 10 06 68 40 cmp\.ltu\.unc p2,p3=r3,r4
25c: 38 20 0c d4 cmp\.ltu\.unc p2,p3=3,r4
260: 00 18 12 06 02 34 \[MII\] cmp\.ltu\.unc p3,p2=r4,r3
266: 20 14 10 06 6a 40 cmp\.ltu\.unc p2,p3=2,r4
26c: 48 18 0c d0 cmp\.ltu\.unc p2,p3=r4,r3
270: 00 18 0a 08 02 35 \[MII\] cmp\.ltu\.unc p3,p2=2,r4
276: 30 1c 10 04 68 60 cmp\.ltu\.unc p3,p2=r3,r4
27c: 38 20 08 d4 cmp\.ltu\.unc p3,p2=3,r4
280: 00 10 0c 08 43 30 \[MII\] cmp\.eq\.and p2,p3=r3,r4
286: 20 18 10 86 62 40 cmp\.eq\.and p2,p3=3,r4
28c: 30 20 0c d1 cmp\.eq\.or p2,p3=r3,r4
290: 00 10 0c 08 43 35 \[MII\] cmp\.eq\.or p2,p3=3,r4
296: 20 18 10 86 70 40 cmp\.eq\.or\.andcm p2,p3=r3,r4
29c: 30 20 0c e5 cmp\.eq\.or\.andcm p2,p3=3,r4
2a0: 00 10 0e 08 43 34 \[MII\] cmp\.ne\.or p2,p3=r3,r4
2a6: 20 1c 10 86 6a 40 cmp\.ne\.or p2,p3=3,r4
2ac: 38 20 0c c1 cmp\.ne\.and p2,p3=r3,r4
2b0: 00 10 0e 08 43 31 \[MII\] cmp\.ne\.and p2,p3=3,r4
2b6: 30 1c 10 84 70 60 cmp\.ne\.or\.andcm p3,p2=r3,r4
2bc: 38 20 08 e5 cmp\.ne\.or\.andcm p3,p2=3,r4
2c0: 00 10 0e 08 43 30 \[MII\] cmp\.ne\.and p2,p3=r3,r4
2c6: 20 1c 10 86 62 40 cmp\.ne\.and p2,p3=3,r4
2cc: 38 20 0c d1 cmp\.ne\.or p2,p3=r3,r4
2d0: 00 10 0e 08 43 35 \[MII\] cmp\.ne\.or p2,p3=3,r4
2d6: 20 1c 10 86 70 40 cmp\.ne\.or\.andcm p2,p3=r3,r4
2dc: 38 20 0c e5 cmp\.ne\.or\.andcm p2,p3=3,r4
2e0: 00 10 0c 08 43 34 \[MII\] cmp\.eq\.or p2,p3=r3,r4
2e6: 20 18 10 86 6a 40 cmp\.eq\.or p2,p3=3,r4
2ec: 30 20 0c c1 cmp\.eq\.and p2,p3=r3,r4
2f0: 00 10 0c 08 43 31 \[MII\] cmp\.eq\.and p2,p3=3,r4
2f6: 30 18 10 84 70 60 cmp\.eq\.or\.andcm p3,p2=r3,r4
2fc: 30 20 08 e5 cmp\.eq\.or\.andcm p3,p2=3,r4
300: 00 10 00 08 43 30 \[MII\] cmp\.eq\.and p2,p3=r0,r4
306: 20 00 10 86 68 40 cmp\.eq\.or p2,p3=r0,r4
30c: 00 20 0c e1 cmp\.eq\.or\.andcm p2,p3=r0,r4
310: 00 10 02 08 43 34 \[MII\] cmp\.ne\.or p2,p3=r0,r4
316: 20 04 10 86 60 60 cmp\.ne\.and p2,p3=r0,r4
31c: 08 20 08 e1 cmp\.ne\.or\.andcm p3,p2=r0,r4
320: 00 10 02 08 43 30 \[MII\] cmp\.ne\.and p2,p3=r0,r4
326: 20 04 10 86 68 40 cmp\.ne\.or p2,p3=r0,r4
32c: 08 20 0c e1 cmp\.ne\.or\.andcm p2,p3=r0,r4
330: 00 10 00 08 43 34 \[MII\] cmp\.eq\.or p2,p3=r0,r4
336: 20 00 10 86 60 60 cmp\.eq\.and p2,p3=r0,r4
33c: 00 20 08 e1 cmp\.eq\.or\.andcm p3,p2=r0,r4
340: 00 10 02 08 43 32 \[MII\] cmp\.lt\.and p2,p3=r0,r4
346: 20 04 10 86 6c 40 cmp\.lt\.or p2,p3=r0,r4
34c: 08 20 0c e9 cmp\.lt\.or\.andcm p2,p3=r0,r4
350: 00 10 00 08 43 36 \[MII\] cmp\.ge\.or p2,p3=r0,r4
356: 20 00 10 86 64 60 cmp\.ge\.and p2,p3=r0,r4
35c: 00 20 08 e9 cmp\.ge\.or\.andcm p3,p2=r0,r4
360: 00 10 02 08 03 32 \[MII\] cmp\.le\.and p2,p3=r0,r4
366: 20 04 10 06 6c 40 cmp\.le\.or p2,p3=r0,r4
36c: 08 20 0c e8 cmp\.le\.or\.andcm p2,p3=r0,r4
370: 00 10 00 08 03 36 \[MII\] cmp\.gt\.or p2,p3=r0,r4
376: 20 00 10 06 64 60 cmp\.gt\.and p2,p3=r0,r4
37c: 00 20 08 e8 cmp\.gt\.or\.andcm p3,p2=r0,r4
380: 00 10 00 08 03 32 \[MII\] cmp\.gt\.and p2,p3=r0,r4
386: 20 00 10 06 6c 40 cmp\.gt\.or p2,p3=r0,r4
38c: 00 20 0c e8 cmp\.gt\.or\.andcm p2,p3=r0,r4
390: 00 10 02 08 03 36 \[MII\] cmp\.le\.or p2,p3=r0,r4
396: 20 04 10 06 64 60 cmp\.le\.and p2,p3=r0,r4
39c: 08 20 08 e8 cmp\.le\.or\.andcm p3,p2=r0,r4
3a0: 00 10 00 08 43 32 \[MII\] cmp\.ge\.and p2,p3=r0,r4
3a6: 20 00 10 86 6c 40 cmp\.ge\.or p2,p3=r0,r4
3ac: 00 20 0c e9 cmp\.ge\.or\.andcm p2,p3=r0,r4
3b0: 00 10 02 08 43 36 \[MII\] cmp\.lt\.or p2,p3=r0,r4
3b6: 20 04 10 86 64 60 cmp\.lt\.and p2,p3=r0,r4
3bc: 08 20 08 e9 cmp\.lt\.or\.andcm p3,p2=r0,r4
3c0: 00 10 0c 08 83 38 \[MII\] cmp4\.eq p2,p3=r3,r4
3c6: 20 18 10 06 73 60 cmp4\.eq p2,p3=3,r4
3cc: 30 20 08 e2 cmp4\.eq p3,p2=r3,r4
3d0: 00 18 0c 08 82 39 \[MII\] cmp4\.eq p3,p2=3,r4
3d6: 20 18 10 06 61 40 cmp4\.lt p2,p3=r3,r4
3dc: 30 20 0c c6 cmp4\.lt p2,p3=3,r4
3e0: 00 18 10 06 82 30 \[MII\] cmp4\.lt p3,p2=r4,r3
3e6: 20 10 10 06 63 40 cmp4\.lt p2,p3=2,r4
3ec: 40 18 0c c2 cmp4\.lt p2,p3=r4,r3
3f0: 00 18 08 08 82 31 \[MII\] cmp4\.lt p3,p2=2,r4
3f6: 30 18 10 04 61 60 cmp4\.lt p3,p2=r3,r4
3fc: 30 20 08 c6 cmp4\.lt p3,p2=3,r4
400: 00 10 0c 08 83 34 \[MII\] cmp4\.ltu p2,p3=r3,r4
406: 20 18 10 06 6b 60 cmp4\.ltu p2,p3=3,r4
40c: 40 18 08 d2 cmp4\.ltu p3,p2=r4,r3
410: 00 10 08 08 83 35 \[MII\] cmp4\.ltu p2,p3=2,r4
416: 20 20 0c 06 69 60 cmp4\.ltu p2,p3=r4,r3
41c: 20 20 08 d6 cmp4\.ltu p3,p2=2,r4
420: 00 18 0c 08 82 34 \[MII\] cmp4\.ltu p3,p2=r3,r4
426: 30 18 10 04 6b 40 cmp4\.ltu p3,p2=3,r4
42c: 38 20 0c e2 cmp4\.eq\.unc p2,p3=r3,r4
430: 00 10 0e 08 83 39 \[MII\] cmp4\.eq\.unc p2,p3=3,r4
436: 30 1c 10 04 71 60 cmp4\.eq\.unc p3,p2=r3,r4
43c: 38 20 08 e6 cmp4\.eq\.unc p3,p2=3,r4
440: 00 10 0e 08 83 30 \[MII\] cmp4\.lt\.unc p2,p3=r3,r4
446: 20 1c 10 06 63 60 cmp4\.lt\.unc p2,p3=3,r4
44c: 48 18 08 c2 cmp4\.lt\.unc p3,p2=r4,r3
450: 00 10 0a 08 83 31 \[MII\] cmp4\.lt\.unc p2,p3=2,r4
456: 20 24 0c 06 61 60 cmp4\.lt\.unc p2,p3=r4,r3
45c: 28 20 08 c6 cmp4\.lt\.unc p3,p2=2,r4
460: 00 18 0e 08 82 30 \[MII\] cmp4\.lt\.unc p3,p2=r3,r4
466: 30 1c 10 04 63 40 cmp4\.lt\.unc p3,p2=3,r4
46c: 38 20 0c d2 cmp4\.ltu\.unc p2,p3=r3,r4
470: 00 10 0e 08 83 35 \[MII\] cmp4\.ltu\.unc p2,p3=3,r4
476: 30 24 0c 04 69 40 cmp4\.ltu\.unc p3,p2=r4,r3
47c: 28 20 0c d6 cmp4\.ltu\.unc p2,p3=2,r4
480: 00 10 12 06 83 34 \[MII\] cmp4\.ltu\.unc p2,p3=r4,r3
486: 30 14 10 04 6b 60 cmp4\.ltu\.unc p3,p2=2,r4
48c: 38 20 08 d2 cmp4\.ltu\.unc p3,p2=r3,r4
490: 00 18 0e 08 82 35 \[MII\] cmp4\.ltu\.unc p3,p2=3,r4
496: 20 18 10 86 61 40 cmp4\.eq\.and p2,p3=r3,r4
49c: 30 20 0c c7 cmp4\.eq\.and p2,p3=3,r4
4a0: 00 10 0c 08 c3 34 \[MII\] cmp4\.eq\.or p2,p3=r3,r4
4a6: 20 18 10 86 6b 40 cmp4\.eq\.or p2,p3=3,r4
4ac: 30 20 0c e3 cmp4\.eq\.or\.andcm p2,p3=r3,r4
4b0: 00 10 0c 08 c3 39 \[MII\] cmp4\.eq\.or\.andcm p2,p3=3,r4
4b6: 20 1c 10 86 69 40 cmp4\.ne\.or p2,p3=r3,r4
4bc: 38 20 0c d7 cmp4\.ne\.or p2,p3=3,r4
4c0: 00 10 0e 08 c3 30 \[MII\] cmp4\.ne\.and p2,p3=r3,r4
4c6: 20 1c 10 86 63 60 cmp4\.ne\.and p2,p3=3,r4
4cc: 38 20 08 e3 cmp4\.ne\.or\.andcm p3,p2=r3,r4
4d0: 00 18 0e 08 c2 39 \[MII\] cmp4\.ne\.or\.andcm p3,p2=3,r4
4d6: 20 1c 10 86 61 40 cmp4\.ne\.and p2,p3=r3,r4
4dc: 38 20 0c c7 cmp4\.ne\.and p2,p3=3,r4
4e0: 00 10 0e 08 c3 34 \[MII\] cmp4\.ne\.or p2,p3=r3,r4
4e6: 20 1c 10 86 6b 40 cmp4\.ne\.or p2,p3=3,r4
4ec: 38 20 0c e3 cmp4\.ne\.or\.andcm p2,p3=r3,r4
4f0: 00 10 0e 08 c3 39 \[MII\] cmp4\.ne\.or\.andcm p2,p3=3,r4
4f6: 20 18 10 86 69 40 cmp4\.eq\.or p2,p3=r3,r4
4fc: 30 20 0c d7 cmp4\.eq\.or p2,p3=3,r4
500: 00 10 0c 08 c3 30 \[MII\] cmp4\.eq\.and p2,p3=r3,r4
506: 20 18 10 86 63 60 cmp4\.eq\.and p2,p3=3,r4
50c: 30 20 08 e3 cmp4\.eq\.or\.andcm p3,p2=r3,r4
510: 00 18 0c 08 c2 39 \[MII\] cmp4\.eq\.or\.andcm p3,p2=3,r4
516: 20 00 10 86 61 40 cmp4\.eq\.and p2,p3=r0,r4
51c: 00 20 0c d3 cmp4\.eq\.or p2,p3=r0,r4
520: 00 10 00 08 c3 38 \[MII\] cmp4\.eq\.or\.andcm p2,p3=r0,r4
526: 20 04 10 86 69 40 cmp4\.ne\.or p2,p3=r0,r4
52c: 08 20 0c c3 cmp4\.ne\.and p2,p3=r0,r4
530: 00 18 02 08 c2 38 \[MII\] cmp4\.ne\.or\.andcm p3,p2=r0,r4
536: 20 04 10 86 61 40 cmp4\.ne\.and p2,p3=r0,r4
53c: 08 20 0c d3 cmp4\.ne\.or p2,p3=r0,r4
540: 00 10 02 08 c3 38 \[MII\] cmp4\.ne\.or\.andcm p2,p3=r0,r4
546: 20 00 10 86 69 40 cmp4\.eq\.or p2,p3=r0,r4
54c: 00 20 0c c3 cmp4\.eq\.and p2,p3=r0,r4
550: 00 18 00 08 c2 38 \[MII\] cmp4\.eq\.or\.andcm p3,p2=r0,r4
556: 20 04 10 86 65 40 cmp4\.lt\.and p2,p3=r0,r4
55c: 08 20 0c db cmp4\.lt\.or p2,p3=r0,r4
560: 00 10 02 08 c3 3a \[MII\] cmp4\.lt\.or\.andcm p2,p3=r0,r4
566: 20 00 10 86 6d 40 cmp4\.ge\.or p2,p3=r0,r4
56c: 00 20 0c cb cmp4\.ge\.and p2,p3=r0,r4
570: 00 18 00 08 c2 3a \[MII\] cmp4\.ge\.or\.andcm p3,p2=r0,r4
576: 20 04 10 06 65 40 cmp4\.le\.and p2,p3=r0,r4
57c: 08 20 0c da cmp4\.le\.or p2,p3=r0,r4
580: 00 10 02 08 83 3a \[MII\] cmp4\.le\.or\.andcm p2,p3=r0,r4
586: 20 00 10 06 6d 40 cmp4\.gt\.or p2,p3=r0,r4
58c: 00 20 0c ca cmp4\.gt\.and p2,p3=r0,r4
590: 00 18 00 08 82 3a \[MII\] cmp4\.gt\.or\.andcm p3,p2=r0,r4
596: 20 00 10 06 65 40 cmp4\.gt\.and p2,p3=r0,r4
59c: 00 20 0c da cmp4\.gt\.or p2,p3=r0,r4
5a0: 00 10 00 08 83 3a \[MII\] cmp4\.gt\.or\.andcm p2,p3=r0,r4
5a6: 20 04 10 06 6d 40 cmp4\.le\.or p2,p3=r0,r4
5ac: 08 20 0c ca cmp4\.le\.and p2,p3=r0,r4
5b0: 00 18 02 08 82 3a \[MII\] cmp4\.le\.or\.andcm p3,p2=r0,r4
5b6: 20 00 10 86 65 40 cmp4\.ge\.and p2,p3=r0,r4
5bc: 00 20 0c db cmp4\.ge\.or p2,p3=r0,r4
5c0: 00 10 00 08 c3 3a \[MII\] cmp4\.ge\.or\.andcm p2,p3=r0,r4
5c6: 20 04 10 86 6d 40 cmp4\.lt\.or p2,p3=r0,r4
5cc: 08 20 0c cb cmp4\.lt\.and p2,p3=r0,r4
5d0: 01 18 02 08 c2 3a \[MII\] cmp4\.lt\.or\.andcm p3,p2=r0,r4
5d6: 00 00 00 02 00 00 nop\.i 0x0
5dc: 00 00 04 00 nop\.i 0x0;;

141
gas/testsuite/gas/ia64/opc-a.pl Normal file
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$AT = '@';
print <<END
.text
.type _start,${AT}function
_start:
add r101 = r102, r103
(p1) add r104 = r105, r106
add r107 = r108, r109, 1
(p2) add r110 = r111, r112, 1
adds r20 = 0, r10
(p1) adds r21 = 1, r10
adds r22 = -1, r10
adds r23 = -0x2000, r10
(p2) adds r24 = 0x1FFF, r10
addl r30 = 0, r1
addl r31 = 1, r1
(p1) addl r32 = -1, r1
addl r33 = -0x2000, r1
addl r34 = 0x1FFF, r1
addl r35 = -0x200000, r1
addl r36 = 0x1FFFFF, r1
add r11 = 0, r10
add r12 = 0x1234, r10
add r13 = 0x1234, r1
add r14 = 0x12345, r1
addp4 r20 = r3, r10
(p1) addp4 r21 = 1, r10
addp4 r22 = -1, r10
sub r101 = r102, r103
(p2) sub r110 = r111, r112, 1
sub r120 = 0, r3
sub r121 = 1, r3
sub r122 = -1, r3
sub r123 = -128, r3
sub r124 = 127, r3
and r8 = r9, r10
(p3) and r11 = -128, r12
(p4) or r8 = r9, r10
or r11 = -128, r12
xor r8 = r9, r10
xor r11 = -128, r12
andcm r8 = r9, r10
andcm r11 = -128, r12
shladd r8 = r30, 1, r31
shladd r9 = r30, 2, r31
shladd r10 = r30, 3, r31
shladd r11 = r30, 4, r31
shladdp4 r8 = r30, 1, r31
shladdp4 r9 = r30, 2, r31
shladdp4 r10 = r30, 3, r31
shladdp4 r11 = r30, 4, r31
padd1 r10 = r30, r31
padd1.sss r11 = r30, r31
padd1.uus r12 = r30, r31
padd1.uuu r13 = r30, r31
padd2 r14 = r30, r31
padd2.sss r15 = r30, r31
padd2.uus r16 = r30, r31
padd2.uuu r17 = r30, r31
padd4 r18 = r30, r31
psub1 r10 = r30, r31
psub1.sss r11 = r30, r31
psub1.uus r12 = r30, r31
psub1.uuu r13 = r30, r31
psub2 r14 = r30, r31
psub2.sss r15 = r30, r31
psub2.uus r16 = r30, r31
psub2.uuu r17 = r30, r31
psub4 r18 = r30, r31
pavg1 r10 = r30, r31
pavg1.raz r10 = r30, r31
pavg2 r10 = r30, r31
pavg2.raz r10 = r30, r31
pavgsub1 r10 = r30, r31
pavgsub2 r10 = r30, r31
pcmp1.eq r10 = r30, r31
pcmp2.eq r10 = r30, r31
pcmp4.eq r10 = r30, r31
pcmp1.gt r10 = r30, r31
pcmp2.gt r10 = r30, r31
pcmp4.gt r10 = r30, r31
pshladd2 r10 = r11, 1, r12
pshladd2 r10 = r11, 3, r12
pshradd2 r10 = r11, 1, r12
pshradd2 r10 = r11, 2, r12
END
;
@cmp2 = ( ".eq", ".ne" );
@cmp6 = ( @cmp2, ".lt", ".le", ".gt", ".ge" );
@cmp10 = ( @cmp6, ".ltu", ".leu", ".gtu", ".geu" );
@ctype = ( ".and", ".or", ".or.andcm", ".orcm", ".andcm", ".and.orcm" );
foreach $C ( "cmp", "cmp4" ) {
foreach $u ( "", ".unc" ) {
foreach $i (@cmp10) {
print "\t${C}${i}${u} p2, p3 = r3, r4\n";
print "\t${C}${i}${u} p2, p3 = 3, r4\n";
}
print "\n";
}
foreach $i (@cmp2) {
foreach $c (@ctype) {
print "\t${C}${i}${c} p2, p3 = r3, r4\n";
print "\t${C}${i}${c} p2, p3 = 3, r4\n";
}
print "\n";
}
foreach $i (@cmp6) {
foreach $c (@ctype) {
print "\t${C}${i}${c} p2, p3 = r0, r4\n";
}
print "\n";
}
}
# Pad to a bundle boundary with known nops.
print "nop.i 0; nop.i 0\n";

324
gas/testsuite/gas/ia64/opc-a.s Normal file
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.text
.type _start,@function
_start:
add r101 = r102, r103
(p1) add r104 = r105, r106
add r107 = r108, r109, 1
(p2) add r110 = r111, r112, 1
adds r20 = 0, r10
(p1) adds r21 = 1, r10
adds r22 = -1, r10
adds r23 = -0x2000, r10
(p2) adds r24 = 0x1FFF, r10
addl r30 = 0, r1
addl r31 = 1, r1
(p1) addl r32 = -1, r1
addl r33 = -0x2000, r1
addl r34 = 0x1FFF, r1
addl r35 = -0x200000, r1
addl r36 = 0x1FFFFF, r1
add r11 = 0, r10
add r12 = 0x1234, r10
add r13 = 0x1234, r1
add r14 = 0x12345, r1
addp4 r20 = r3, r10
(p1) addp4 r21 = 1, r10
addp4 r22 = -1, r10
sub r101 = r102, r103
(p2) sub r110 = r111, r112, 1
sub r120 = 0, r3
sub r121 = 1, r3
sub r122 = -1, r3
sub r123 = -128, r3
sub r124 = 127, r3
and r8 = r9, r10
(p3) and r11 = -128, r12
(p4) or r8 = r9, r10
or r11 = -128, r12
xor r8 = r9, r10
xor r11 = -128, r12
andcm r8 = r9, r10
andcm r11 = -128, r12
shladd r8 = r30, 1, r31
shladd r9 = r30, 2, r31
shladd r10 = r30, 3, r31
shladd r11 = r30, 4, r31
shladdp4 r8 = r30, 1, r31
shladdp4 r9 = r30, 2, r31
shladdp4 r10 = r30, 3, r31
shladdp4 r11 = r30, 4, r31
padd1 r10 = r30, r31
padd1.sss r11 = r30, r31
padd1.uus r12 = r30, r31
padd1.uuu r13 = r30, r31
padd2 r14 = r30, r31
padd2.sss r15 = r30, r31
padd2.uus r16 = r30, r31
padd2.uuu r17 = r30, r31
padd4 r18 = r30, r31
psub1 r10 = r30, r31
psub1.sss r11 = r30, r31
psub1.uus r12 = r30, r31
psub1.uuu r13 = r30, r31
psub2 r14 = r30, r31
psub2.sss r15 = r30, r31
psub2.uus r16 = r30, r31
psub2.uuu r17 = r30, r31
psub4 r18 = r30, r31
pavg1 r10 = r30, r31
pavg1.raz r10 = r30, r31
pavg2 r10 = r30, r31
pavg2.raz r10 = r30, r31
pavgsub1 r10 = r30, r31
pavgsub2 r10 = r30, r31
pcmp1.eq r10 = r30, r31
pcmp2.eq r10 = r30, r31
pcmp4.eq r10 = r30, r31
pcmp1.gt r10 = r30, r31
pcmp2.gt r10 = r30, r31
pcmp4.gt r10 = r30, r31
pshladd2 r10 = r11, 1, r12
pshladd2 r10 = r11, 3, r12
pshradd2 r10 = r11, 1, r12
pshradd2 r10 = r11, 2, r12
cmp.eq p2, p3 = r3, r4
cmp.eq p2, p3 = 3, r4
cmp.ne p2, p3 = r3, r4
cmp.ne p2, p3 = 3, r4
cmp.lt p2, p3 = r3, r4
cmp.lt p2, p3 = 3, r4
cmp.le p2, p3 = r3, r4
cmp.le p2, p3 = 3, r4
cmp.gt p2, p3 = r3, r4
cmp.gt p2, p3 = 3, r4
cmp.ge p2, p3 = r3, r4
cmp.ge p2, p3 = 3, r4
cmp.ltu p2, p3 = r3, r4
cmp.ltu p2, p3 = 3, r4
cmp.leu p2, p3 = r3, r4
cmp.leu p2, p3 = 3, r4
cmp.gtu p2, p3 = r3, r4
cmp.gtu p2, p3 = 3, r4
cmp.geu p2, p3 = r3, r4
cmp.geu p2, p3 = 3, r4
cmp.eq.unc p2, p3 = r3, r4
cmp.eq.unc p2, p3 = 3, r4
cmp.ne.unc p2, p3 = r3, r4
cmp.ne.unc p2, p3 = 3, r4
cmp.lt.unc p2, p3 = r3, r4
cmp.lt.unc p2, p3 = 3, r4
cmp.le.unc p2, p3 = r3, r4
cmp.le.unc p2, p3 = 3, r4
cmp.gt.unc p2, p3 = r3, r4
cmp.gt.unc p2, p3 = 3, r4
cmp.ge.unc p2, p3 = r3, r4
cmp.ge.unc p2, p3 = 3, r4
cmp.ltu.unc p2, p3 = r3, r4
cmp.ltu.unc p2, p3 = 3, r4
cmp.leu.unc p2, p3 = r3, r4
cmp.leu.unc p2, p3 = 3, r4
cmp.gtu.unc p2, p3 = r3, r4
cmp.gtu.unc p2, p3 = 3, r4
cmp.geu.unc p2, p3 = r3, r4
cmp.geu.unc p2, p3 = 3, r4
cmp.eq.and p2, p3 = r3, r4
cmp.eq.and p2, p3 = 3, r4
cmp.eq.or p2, p3 = r3, r4
cmp.eq.or p2, p3 = 3, r4
cmp.eq.or.andcm p2, p3 = r3, r4
cmp.eq.or.andcm p2, p3 = 3, r4
cmp.eq.orcm p2, p3 = r3, r4
cmp.eq.orcm p2, p3 = 3, r4
cmp.eq.andcm p2, p3 = r3, r4
cmp.eq.andcm p2, p3 = 3, r4
cmp.eq.and.orcm p2, p3 = r3, r4
cmp.eq.and.orcm p2, p3 = 3, r4
cmp.ne.and p2, p3 = r3, r4
cmp.ne.and p2, p3 = 3, r4
cmp.ne.or p2, p3 = r3, r4
cmp.ne.or p2, p3 = 3, r4
cmp.ne.or.andcm p2, p3 = r3, r4
cmp.ne.or.andcm p2, p3 = 3, r4
cmp.ne.orcm p2, p3 = r3, r4
cmp.ne.orcm p2, p3 = 3, r4
cmp.ne.andcm p2, p3 = r3, r4
cmp.ne.andcm p2, p3 = 3, r4
cmp.ne.and.orcm p2, p3 = r3, r4
cmp.ne.and.orcm p2, p3 = 3, r4
cmp.eq.and p2, p3 = r0, r4
cmp.eq.or p2, p3 = r0, r4
cmp.eq.or.andcm p2, p3 = r0, r4
cmp.eq.orcm p2, p3 = r0, r4
cmp.eq.andcm p2, p3 = r0, r4
cmp.eq.and.orcm p2, p3 = r0, r4
cmp.ne.and p2, p3 = r0, r4
cmp.ne.or p2, p3 = r0, r4
cmp.ne.or.andcm p2, p3 = r0, r4
cmp.ne.orcm p2, p3 = r0, r4
cmp.ne.andcm p2, p3 = r0, r4
cmp.ne.and.orcm p2, p3 = r0, r4
cmp.lt.and p2, p3 = r0, r4
cmp.lt.or p2, p3 = r0, r4
cmp.lt.or.andcm p2, p3 = r0, r4
cmp.lt.orcm p2, p3 = r0, r4
cmp.lt.andcm p2, p3 = r0, r4
cmp.lt.and.orcm p2, p3 = r0, r4
cmp.le.and p2, p3 = r0, r4
cmp.le.or p2, p3 = r0, r4
cmp.le.or.andcm p2, p3 = r0, r4
cmp.le.orcm p2, p3 = r0, r4
cmp.le.andcm p2, p3 = r0, r4
cmp.le.and.orcm p2, p3 = r0, r4
cmp.gt.and p2, p3 = r0, r4
cmp.gt.or p2, p3 = r0, r4
cmp.gt.or.andcm p2, p3 = r0, r4
cmp.gt.orcm p2, p3 = r0, r4
cmp.gt.andcm p2, p3 = r0, r4
cmp.gt.and.orcm p2, p3 = r0, r4
cmp.ge.and p2, p3 = r0, r4
cmp.ge.or p2, p3 = r0, r4
cmp.ge.or.andcm p2, p3 = r0, r4
cmp.ge.orcm p2, p3 = r0, r4
cmp.ge.andcm p2, p3 = r0, r4
cmp.ge.and.orcm p2, p3 = r0, r4
cmp4.eq p2, p3 = r3, r4
cmp4.eq p2, p3 = 3, r4
cmp4.ne p2, p3 = r3, r4
cmp4.ne p2, p3 = 3, r4
cmp4.lt p2, p3 = r3, r4
cmp4.lt p2, p3 = 3, r4
cmp4.le p2, p3 = r3, r4
cmp4.le p2, p3 = 3, r4
cmp4.gt p2, p3 = r3, r4
cmp4.gt p2, p3 = 3, r4
cmp4.ge p2, p3 = r3, r4
cmp4.ge p2, p3 = 3, r4
cmp4.ltu p2, p3 = r3, r4
cmp4.ltu p2, p3 = 3, r4
cmp4.leu p2, p3 = r3, r4
cmp4.leu p2, p3 = 3, r4
cmp4.gtu p2, p3 = r3, r4
cmp4.gtu p2, p3 = 3, r4
cmp4.geu p2, p3 = r3, r4
cmp4.geu p2, p3 = 3, r4
cmp4.eq.unc p2, p3 = r3, r4
cmp4.eq.unc p2, p3 = 3, r4
cmp4.ne.unc p2, p3 = r3, r4
cmp4.ne.unc p2, p3 = 3, r4
cmp4.lt.unc p2, p3 = r3, r4
cmp4.lt.unc p2, p3 = 3, r4
cmp4.le.unc p2, p3 = r3, r4
cmp4.le.unc p2, p3 = 3, r4
cmp4.gt.unc p2, p3 = r3, r4
cmp4.gt.unc p2, p3 = 3, r4
cmp4.ge.unc p2, p3 = r3, r4
cmp4.ge.unc p2, p3 = 3, r4
cmp4.ltu.unc p2, p3 = r3, r4
cmp4.ltu.unc p2, p3 = 3, r4
cmp4.leu.unc p2, p3 = r3, r4
cmp4.leu.unc p2, p3 = 3, r4
cmp4.gtu.unc p2, p3 = r3, r4
cmp4.gtu.unc p2, p3 = 3, r4
cmp4.geu.unc p2, p3 = r3, r4
cmp4.geu.unc p2, p3 = 3, r4
cmp4.eq.and p2, p3 = r3, r4
cmp4.eq.and p2, p3 = 3, r4
cmp4.eq.or p2, p3 = r3, r4
cmp4.eq.or p2, p3 = 3, r4
cmp4.eq.or.andcm p2, p3 = r3, r4
cmp4.eq.or.andcm p2, p3 = 3, r4
cmp4.eq.orcm p2, p3 = r3, r4
cmp4.eq.orcm p2, p3 = 3, r4
cmp4.eq.andcm p2, p3 = r3, r4
cmp4.eq.andcm p2, p3 = 3, r4
cmp4.eq.and.orcm p2, p3 = r3, r4
cmp4.eq.and.orcm p2, p3 = 3, r4
cmp4.ne.and p2, p3 = r3, r4
cmp4.ne.and p2, p3 = 3, r4
cmp4.ne.or p2, p3 = r3, r4
cmp4.ne.or p2, p3 = 3, r4
cmp4.ne.or.andcm p2, p3 = r3, r4
cmp4.ne.or.andcm p2, p3 = 3, r4
cmp4.ne.orcm p2, p3 = r3, r4
cmp4.ne.orcm p2, p3 = 3, r4
cmp4.ne.andcm p2, p3 = r3, r4
cmp4.ne.andcm p2, p3 = 3, r4
cmp4.ne.and.orcm p2, p3 = r3, r4
cmp4.ne.and.orcm p2, p3 = 3, r4
cmp4.eq.and p2, p3 = r0, r4
cmp4.eq.or p2, p3 = r0, r4
cmp4.eq.or.andcm p2, p3 = r0, r4
cmp4.eq.orcm p2, p3 = r0, r4
cmp4.eq.andcm p2, p3 = r0, r4
cmp4.eq.and.orcm p2, p3 = r0, r4
cmp4.ne.and p2, p3 = r0, r4
cmp4.ne.or p2, p3 = r0, r4
cmp4.ne.or.andcm p2, p3 = r0, r4
cmp4.ne.orcm p2, p3 = r0, r4
cmp4.ne.andcm p2, p3 = r0, r4
cmp4.ne.and.orcm p2, p3 = r0, r4
cmp4.lt.and p2, p3 = r0, r4
cmp4.lt.or p2, p3 = r0, r4
cmp4.lt.or.andcm p2, p3 = r0, r4
cmp4.lt.orcm p2, p3 = r0, r4
cmp4.lt.andcm p2, p3 = r0, r4
cmp4.lt.and.orcm p2, p3 = r0, r4
cmp4.le.and p2, p3 = r0, r4
cmp4.le.or p2, p3 = r0, r4
cmp4.le.or.andcm p2, p3 = r0, r4
cmp4.le.orcm p2, p3 = r0, r4
cmp4.le.andcm p2, p3 = r0, r4
cmp4.le.and.orcm p2, p3 = r0, r4
cmp4.gt.and p2, p3 = r0, r4
cmp4.gt.or p2, p3 = r0, r4
cmp4.gt.or.andcm p2, p3 = r0, r4
cmp4.gt.orcm p2, p3 = r0, r4
cmp4.gt.andcm p2, p3 = r0, r4
cmp4.gt.and.orcm p2, p3 = r0, r4
cmp4.ge.and p2, p3 = r0, r4
cmp4.ge.or p2, p3 = r0, r4
cmp4.ge.or.andcm p2, p3 = r0, r4
cmp4.ge.orcm p2, p3 = r0, r4
cmp4.ge.andcm p2, p3 = r0, r4
cmp4.ge.and.orcm p2, p3 = r0, r4
nop.i 0; nop.i 0

1014
gas/testsuite/gas/ia64/opc-b.d Normal file
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95
gas/testsuite/gas/ia64/opc-b.pl Normal file
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@ph = ( "", ".few", ".many" );
@bwh = ( ".sptk", ".spnt", ".dptk", ".dpnt" );
@dh = ( "", ".clr" );
@iprel = ( ".cond", ".wexit", ".wtop", ".cloop", ".cexit", ".ctop", ".call" );
@indir = ( ".cond", ".ia", ".ret", ".call" );
%noqual = ( ".ia", 1, ".cloop", 1, ".ctop", 1, ".cexit", 1 );
%slottwo = ( ".cloop", 1, ".ctop", 1, ".cexit", 1, ".wtop", 1, ".wexit", 1 );
print ".L0:\n\n";
foreach $i (@iprel) {
$call = ($i eq ".call" ? "b0 = " : "");
foreach $b (@bwh) {
foreach $p (@ph) {
foreach $d (@dh) {
if ($slottwo{$i}) {
if (!$noqual{$i}) {
print ("\t{ .bbb; (p2) br${i}${b}${p}${d} ${call}.L1 ;; }\n");
}
print ("\t{ .bbb; br${i}${b}${p}${d} ${call}.L1 ;; }\n");
} else {
print ("\t{ .bbb; nop.b 0\n");
if (!$noqual{$i}) {
print ("(p2)\tbr${i}${b}${p}${d} ${call}.L1\n");
} else {
print ("\tnop.b 0\n");
}
print ("\tbr${i}${b}${p}${d} ${call}.L0\n");
print ("\t;; }\n");
}
}
}
}
print "\n";
}
foreach $i (@indir) {
$call = ($i eq ".call" ? "b0 = " : "");
foreach $b (@bwh) {
foreach $p (@ph) {
foreach $d (@dh) {
print ("\t{ .bbb; nop.b 0;\n");
if (!$noqual{$i}) {
print ("(p2)\tbr${i}${b}${p}${d} ${call}b2\n");
} else {
print ("\tnop.b 0\n");
}
print ("\tbr${i}${b}${p}${d} ${call}b2\n");
print ("\t;; }\n");
}
}
}
print "\n";
}
@ih = ( "", ".imp" );
@ipwh = ( ".sptk", ".loop", ".dptk", ".exit" );
@indwh = ( ".sptk", ".dptk" );
$CTR = 2;
foreach $w (@ipwh) {
foreach $i (@ih) {
print ("\t{ .bbb; break.b 0; nop.b 0\n");
print ("\tbrp${w}${i} .L0, .L${CTR}\n");
print ("\t;; }\n");
}
print (".L${CTR}:\n");
++$CTR;
}
print "\n";
foreach $b ("", ".ret") {
foreach $w (@indwh) {
foreach $i (@ih) {
print ("\t{ .bbb; break.b 0; nop.b 0\n");
print ("\tbrp${b}${w}${i} b3, .L${CTR}\n");
print ("\t;; }\n");
}
print (".L${CTR}:\n");
++$CTR;
}
print "\n";
}
print ".space 5888\n";
@last = ( "cover", "clrrrb", "clrrrb.pr", "rfi", "bsw.0", "bsw.1", "epc" );
foreach $i (@last) {
print "\t{ .bbb; nop.b 0; nop.b 0; $i ;; }\n";
}
print "\n.L1:\n";

826
gas/testsuite/gas/ia64/opc-b.s Normal file
View File

@ -0,0 +1,826 @@
.L0:
{ .bbb; nop.b 0
(p2) br.cond.sptk .L1
br.cond.sptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.clr .L1
br.cond.sptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few .L1
br.cond.sptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few.clr .L1
br.cond.sptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.many .L1
br.cond.sptk.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.many.clr .L1
br.cond.sptk.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt .L1
br.cond.spnt .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.clr .L1
br.cond.spnt.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.few .L1
br.cond.spnt.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.few.clr .L1
br.cond.spnt.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.many .L1
br.cond.spnt.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.many.clr .L1
br.cond.spnt.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk .L1
br.cond.dptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.clr .L1
br.cond.dptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.few .L1
br.cond.dptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.few.clr .L1
br.cond.dptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.many .L1
br.cond.dptk.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.many.clr .L1
br.cond.dptk.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt .L1
br.cond.dpnt .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.clr .L1
br.cond.dpnt.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.few .L1
br.cond.dpnt.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.few.clr .L1
br.cond.dpnt.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.many .L1
br.cond.dpnt.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.many.clr .L1
br.cond.dpnt.many.clr .L0
;; }
{ .bbb; (p2) br.wexit.sptk .L1 ;; }
{ .bbb; br.wexit.sptk .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.clr .L1 ;; }
{ .bbb; br.wexit.sptk.clr .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.few .L1 ;; }
{ .bbb; br.wexit.sptk.few .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.few.clr .L1 ;; }
{ .bbb; br.wexit.sptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.many .L1 ;; }
{ .bbb; br.wexit.sptk.many .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.many.clr .L1 ;; }
{ .bbb; br.wexit.sptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt .L1 ;; }
{ .bbb; br.wexit.spnt .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.clr .L1 ;; }
{ .bbb; br.wexit.spnt.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.few .L1 ;; }
{ .bbb; br.wexit.spnt.few .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.few.clr .L1 ;; }
{ .bbb; br.wexit.spnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.many .L1 ;; }
{ .bbb; br.wexit.spnt.many .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.many.clr .L1 ;; }
{ .bbb; br.wexit.spnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk .L1 ;; }
{ .bbb; br.wexit.dptk .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.clr .L1 ;; }
{ .bbb; br.wexit.dptk.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.few .L1 ;; }
{ .bbb; br.wexit.dptk.few .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.few.clr .L1 ;; }
{ .bbb; br.wexit.dptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.many .L1 ;; }
{ .bbb; br.wexit.dptk.many .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.many.clr .L1 ;; }
{ .bbb; br.wexit.dptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt .L1 ;; }
{ .bbb; br.wexit.dpnt .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.few .L1 ;; }
{ .bbb; br.wexit.dpnt.few .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.few.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.many .L1 ;; }
{ .bbb; br.wexit.dpnt.many .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.many.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk .L1 ;; }
{ .bbb; br.wtop.sptk .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.clr .L1 ;; }
{ .bbb; br.wtop.sptk.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.few .L1 ;; }
{ .bbb; br.wtop.sptk.few .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.few.clr .L1 ;; }
{ .bbb; br.wtop.sptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.many .L1 ;; }
{ .bbb; br.wtop.sptk.many .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.many.clr .L1 ;; }
{ .bbb; br.wtop.sptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt .L1 ;; }
{ .bbb; br.wtop.spnt .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.clr .L1 ;; }
{ .bbb; br.wtop.spnt.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.few .L1 ;; }
{ .bbb; br.wtop.spnt.few .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.few.clr .L1 ;; }
{ .bbb; br.wtop.spnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.many .L1 ;; }
{ .bbb; br.wtop.spnt.many .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.many.clr .L1 ;; }
{ .bbb; br.wtop.spnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk .L1 ;; }
{ .bbb; br.wtop.dptk .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.clr .L1 ;; }
{ .bbb; br.wtop.dptk.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.few .L1 ;; }
{ .bbb; br.wtop.dptk.few .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.few.clr .L1 ;; }
{ .bbb; br.wtop.dptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.many .L1 ;; }
{ .bbb; br.wtop.dptk.many .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.many.clr .L1 ;; }
{ .bbb; br.wtop.dptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt .L1 ;; }
{ .bbb; br.wtop.dpnt .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.few .L1 ;; }
{ .bbb; br.wtop.dpnt.few .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.few.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.many .L1 ;; }
{ .bbb; br.wtop.dpnt.many .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.many.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.many.clr .L1 ;; }
{ .bbb; br.cloop.sptk .L1 ;; }
{ .bbb; br.cloop.sptk.clr .L1 ;; }
{ .bbb; br.cloop.sptk.few .L1 ;; }
{ .bbb; br.cloop.sptk.few.clr .L1 ;; }
{ .bbb; br.cloop.sptk.many .L1 ;; }
{ .bbb; br.cloop.sptk.many.clr .L1 ;; }
{ .bbb; br.cloop.spnt .L1 ;; }
{ .bbb; br.cloop.spnt.clr .L1 ;; }
{ .bbb; br.cloop.spnt.few .L1 ;; }
{ .bbb; br.cloop.spnt.few.clr .L1 ;; }
{ .bbb; br.cloop.spnt.many .L1 ;; }
{ .bbb; br.cloop.spnt.many.clr .L1 ;; }
{ .bbb; br.cloop.dptk .L1 ;; }
{ .bbb; br.cloop.dptk.clr .L1 ;; }
{ .bbb; br.cloop.dptk.few .L1 ;; }
{ .bbb; br.cloop.dptk.few.clr .L1 ;; }
{ .bbb; br.cloop.dptk.many .L1 ;; }
{ .bbb; br.cloop.dptk.many.clr .L1 ;; }
{ .bbb; br.cloop.dpnt .L1 ;; }
{ .bbb; br.cloop.dpnt.clr .L1 ;; }
{ .bbb; br.cloop.dpnt.few .L1 ;; }
{ .bbb; br.cloop.dpnt.few.clr .L1 ;; }
{ .bbb; br.cloop.dpnt.many .L1 ;; }
{ .bbb; br.cloop.dpnt.many.clr .L1 ;; }
{ .bbb; br.cexit.sptk .L1 ;; }
{ .bbb; br.cexit.sptk.clr .L1 ;; }
{ .bbb; br.cexit.sptk.few .L1 ;; }
{ .bbb; br.cexit.sptk.few.clr .L1 ;; }
{ .bbb; br.cexit.sptk.many .L1 ;; }
{ .bbb; br.cexit.sptk.many.clr .L1 ;; }
{ .bbb; br.cexit.spnt .L1 ;; }
{ .bbb; br.cexit.spnt.clr .L1 ;; }
{ .bbb; br.cexit.spnt.few .L1 ;; }
{ .bbb; br.cexit.spnt.few.clr .L1 ;; }
{ .bbb; br.cexit.spnt.many .L1 ;; }
{ .bbb; br.cexit.spnt.many.clr .L1 ;; }
{ .bbb; br.cexit.dptk .L1 ;; }
{ .bbb; br.cexit.dptk.clr .L1 ;; }
{ .bbb; br.cexit.dptk.few .L1 ;; }
{ .bbb; br.cexit.dptk.few.clr .L1 ;; }
{ .bbb; br.cexit.dptk.many .L1 ;; }
{ .bbb; br.cexit.dptk.many.clr .L1 ;; }
{ .bbb; br.cexit.dpnt .L1 ;; }
{ .bbb; br.cexit.dpnt.clr .L1 ;; }
{ .bbb; br.cexit.dpnt.few .L1 ;; }
{ .bbb; br.cexit.dpnt.few.clr .L1 ;; }
{ .bbb; br.cexit.dpnt.many .L1 ;; }
{ .bbb; br.cexit.dpnt.many.clr .L1 ;; }
{ .bbb; br.ctop.sptk .L1 ;; }
{ .bbb; br.ctop.sptk.clr .L1 ;; }
{ .bbb; br.ctop.sptk.few .L1 ;; }
{ .bbb; br.ctop.sptk.few.clr .L1 ;; }
{ .bbb; br.ctop.sptk.many .L1 ;; }
{ .bbb; br.ctop.sptk.many.clr .L1 ;; }
{ .bbb; br.ctop.spnt .L1 ;; }
{ .bbb; br.ctop.spnt.clr .L1 ;; }
{ .bbb; br.ctop.spnt.few .L1 ;; }
{ .bbb; br.ctop.spnt.few.clr .L1 ;; }
{ .bbb; br.ctop.spnt.many .L1 ;; }
{ .bbb; br.ctop.spnt.many.clr .L1 ;; }
{ .bbb; br.ctop.dptk .L1 ;; }
{ .bbb; br.ctop.dptk.clr .L1 ;; }
{ .bbb; br.ctop.dptk.few .L1 ;; }
{ .bbb; br.ctop.dptk.few.clr .L1 ;; }
{ .bbb; br.ctop.dptk.many .L1 ;; }
{ .bbb; br.ctop.dptk.many.clr .L1 ;; }
{ .bbb; br.ctop.dpnt .L1 ;; }
{ .bbb; br.ctop.dpnt.clr .L1 ;; }
{ .bbb; br.ctop.dpnt.few .L1 ;; }
{ .bbb; br.ctop.dpnt.few.clr .L1 ;; }
{ .bbb; br.ctop.dpnt.many .L1 ;; }
{ .bbb; br.ctop.dpnt.many.clr .L1 ;; }
{ .bbb; nop.b 0
(p2) br.call.sptk b0 = .L1
br.call.sptk b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.clr b0 = .L1
br.call.sptk.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.few b0 = .L1
br.call.sptk.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.few.clr b0 = .L1
br.call.sptk.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.many b0 = .L1
br.call.sptk.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.many.clr b0 = .L1
br.call.sptk.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt b0 = .L1
br.call.spnt b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.clr b0 = .L1
br.call.spnt.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.few b0 = .L1
br.call.spnt.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.few.clr b0 = .L1
br.call.spnt.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.many b0 = .L1
br.call.spnt.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.many.clr b0 = .L1
br.call.spnt.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk b0 = .L1
br.call.dptk b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.clr b0 = .L1
br.call.dptk.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.few b0 = .L1
br.call.dptk.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.few.clr b0 = .L1
br.call.dptk.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.many b0 = .L1
br.call.dptk.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.many.clr b0 = .L1
br.call.dptk.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt b0 = .L1
br.call.dpnt b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.clr b0 = .L1
br.call.dpnt.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.few b0 = .L1
br.call.dpnt.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.few.clr b0 = .L1
br.call.dpnt.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.many b0 = .L1
br.call.dpnt.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.many.clr b0 = .L1
br.call.dpnt.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk b2
br.cond.sptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.clr b2
br.cond.sptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.few b2
br.cond.sptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.few.clr b2
br.cond.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.many b2
br.cond.sptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.many.clr b2
br.cond.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt b2
br.cond.spnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.clr b2
br.cond.spnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.few b2
br.cond.spnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.few.clr b2
br.cond.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.many b2
br.cond.spnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.many.clr b2
br.cond.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk b2
br.cond.dptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.clr b2
br.cond.dptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.few b2
br.cond.dptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.few.clr b2
br.cond.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.many b2
br.cond.dptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.many.clr b2
br.cond.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt b2
br.cond.dpnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.clr b2
br.cond.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.few b2
br.cond.dpnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.few.clr b2
br.cond.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.many b2
br.cond.dpnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.many.clr b2
br.cond.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk b2
br.ret.sptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.clr b2
br.ret.sptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.few b2
br.ret.sptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.few.clr b2
br.ret.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.many b2
br.ret.sptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.many.clr b2
br.ret.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt b2
br.ret.spnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.clr b2
br.ret.spnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.few b2
br.ret.spnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.few.clr b2
br.ret.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.many b2
br.ret.spnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.many.clr b2
br.ret.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk b2
br.ret.dptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.clr b2
br.ret.dptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.few b2
br.ret.dptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.few.clr b2
br.ret.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.many b2
br.ret.dptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.many.clr b2
br.ret.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt b2
br.ret.dpnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.clr b2
br.ret.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.few b2
br.ret.dpnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.few.clr b2
br.ret.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.many b2
br.ret.dpnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.many.clr b2
br.ret.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk b0 = b2
br.call.sptk b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.clr b0 = b2
br.call.sptk.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.few b0 = b2
br.call.sptk.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.few.clr b0 = b2
br.call.sptk.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.many b0 = b2
br.call.sptk.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.many.clr b0 = b2
br.call.sptk.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt b0 = b2
br.call.spnt b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.clr b0 = b2
br.call.spnt.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.few b0 = b2
br.call.spnt.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.few.clr b0 = b2
br.call.spnt.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.many b0 = b2
br.call.spnt.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.many.clr b0 = b2
br.call.spnt.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk b0 = b2
br.call.dptk b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.clr b0 = b2
br.call.dptk.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.few b0 = b2
br.call.dptk.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.few.clr b0 = b2
br.call.dptk.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.many b0 = b2
br.call.dptk.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.many.clr b0 = b2
br.call.dptk.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt b0 = b2
br.call.dpnt b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.clr b0 = b2
br.call.dpnt.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.few b0 = b2
br.call.dpnt.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.few.clr b0 = b2
br.call.dpnt.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.many b0 = b2
br.call.dpnt.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.many.clr b0 = b2
br.call.dpnt.many.clr b0 = b2
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk .L0, .L2
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk.imp .L0, .L2
;; }
.L2:
{ .bbb; break.b 0; nop.b 0
brp.loop .L0, .L3
;; }
{ .bbb; break.b 0; nop.b 0
brp.loop.imp .L0, .L3
;; }
.L3:
{ .bbb; break.b 0; nop.b 0
brp.dptk .L0, .L4
;; }
{ .bbb; break.b 0; nop.b 0
brp.dptk.imp .L0, .L4
;; }
.L4:
{ .bbb; break.b 0; nop.b 0
brp.exit .L0, .L5
;; }
{ .bbb; break.b 0; nop.b 0
brp.exit.imp .L0, .L5
;; }
.L5:
{ .bbb; break.b 0; nop.b 0
brp.sptk b3, .L6
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk.imp b3, .L6
;; }
.L6:
{ .bbb; break.b 0; nop.b 0
brp.dptk b3, .L7
;; }
{ .bbb; break.b 0; nop.b 0
brp.dptk.imp b3, .L7
;; }
.L7:
{ .bbb; break.b 0; nop.b 0
brp.ret.sptk b3, .L8
;; }
{ .bbb; break.b 0; nop.b 0
brp.ret.sptk.imp b3, .L8
;; }
.L8:
{ .bbb; break.b 0; nop.b 0
brp.ret.dptk b3, .L9
;; }
{ .bbb; break.b 0; nop.b 0
brp.ret.dptk.imp b3, .L9
;; }
.L9:
.space 5888
{ .bbb; nop.b 0; nop.b 0; cover ;; }
{ .bbb; nop.b 0; nop.b 0; clrrrb ;; }
{ .bbb; nop.b 0; nop.b 0; clrrrb.pr ;; }
{ .bbb; nop.b 0; nop.b 0; rfi ;; }
{ .bbb; nop.b 0; nop.b 0; bsw.0 ;; }
{ .bbb; nop.b 0; nop.b 0; bsw.1 ;; }
{ .bbb; nop.b 0; nop.b 0; epc ;; }
.L1:

1217
gas/testsuite/gas/ia64/opc-f.d Normal file
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File diff suppressed because it is too large Load Diff

163
gas/testsuite/gas/ia64/opc-f.pl Normal file
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@ -0,0 +1,163 @@
print ".text\n\t.type _start,@", "function\n_start:\n\n";
@sf = ( "", ".s0", ".s1", ".s2", ".s3" );
# Arithmetic
foreach $i ( "fma", "fma.s", "fma.d", "fpma",
"fms", "fms.s", "fms.d", "fpms",
"fnma", "fnma.s", "fnma.d", "fpnma" ) {
foreach $s (@sf) {
print "\t${i}${s} f4 = f5, f6, f7\n";
}
print "\n";
}
foreach $i ( "fmpy", "fmpy.s", "fmpy.d", "fpmpy",
"fadd", "fadd.s", "fadd.d", #"fpadd", ??? ias doesn't eat it
"fsub", "fsub.s", "fsub.d", "fpsub",
"fnmpy", "fnmpy.s", "fnmpy.d", "fpnmpy" ) {
foreach $s (@sf) {
print "\t${i}${s} f4 = f5, f6\n";
}
print "\n";
}
foreach $i ( "fnorm", "fnorm.s", "fnorm.d" ) {
foreach $s (@sf) {
print "\t${i}${s} f4 = f5\n";
}
print "\n";
}
# Fixed Point Multiply Add
foreach $s ( ".l", ".lu", ".h", ".hu" ) {
print "\txma${s} f4 = f5, f6, f7\n";
}
print "\n";
foreach $s ( ".l", ".lu", ".h", ".hu" ) {
print "\txmpy${s} f4 = f5, f6\n";
}
print "\n";
# Parallel Floating Point Select
print "\tfselect f4 = f5, f6, f7\n\n";
# Floating Point Compare
@cmp = ( ".eq", ".lt", ".le", ".unord", ".gt", ".ge", ".neq", ".nlt",
".nle", ".ngt", ".nge", ".ord" );
# Floating Point Class
foreach $u ( "", ".unc" ) {
foreach $c ( '@nat', '@qnan', '@snan', '@pos', '@neg', '@unorm',
'@norm', '@inf', '0x1ff' ) {
foreach $m ( ".m", ".nm" ) {
print "\tfclass${m}${u} p3, p4 = f4, $c\n";
}
}
print "\n";
}
# Approximation
foreach $i ( "frcpa", "fprcpa" ) {
foreach $s (@sf) {
print "\t${i}${s} f4, p5 = f6, f7\n";
}
print "\n";
}
foreach $i ( "frsqrta", "fprsqrta" ) {
foreach $s (@sf) {
print "\t${i}${s} f4, p5 = f6\n";
}
print "\n";
}
# Min/Max
foreach $i ( "fmin", "fmax", "famin", "famax",
"fpmin", "fpmax", "fpamin", "fpamax" ) {
foreach $s (@sf) {
print "\t${i}${s} f4 = f5, f6\n";
}
print "\n";
}
# Parallel Compare
foreach $c (@cmp) {
foreach $s (@sf) {
print "\tfcmp${c}${u}${s} p3, p4 = f4, f5\n";
}
print "\n";
}
# Merge and Logical
foreach $i ( "fmerge.s", "fmerge.ns", "fmerge.se", "fmix.lr", "fmix.r",
"fmix.l", "fsxt.l", "fpack", "fswap", "fswap.nl", "fswap.nr",
"fand", "fandcm", "for", "fxor", "fpmerge.s", "fpmerge.ns",
"fpmerge.se" ) {
print "\t$i f4 = f5, f6\n";
}
print "\n";
foreach $i ( "fabs", "fneg", "fnegabs", "fpabs", "fpneg", "fpnegabs" ) {
print "\t$i f4 = f5\n";
}
print "\n";
# Convert Floating to Fixed
foreach $b ( "fcvt", "fpcvt" ) {
foreach $f ( ".fx", ".fxu" ) {
foreach $t ( "", ".trunc" ) {
foreach $s (@sf) {
print "\t${b}${f}${t}${s} f4 = f5\n";
}
print "\n";
}
}
}
# Convert Fixed to Floating
foreach $e ( ".xf", ".xuf" ) {
print "\tfcvt$e f4 = f5\n";
}
print "\n";
# Set Controls
foreach $s (@sf) {
print "\tfsetc$s 0, 0\n";
print "\tfsetc$s 0x3f, 0x3f\n";
}
print "\n";
# Clear flags
foreach $s (@sf) {
print "\tfclrf$s\n";
}
print "\n";
# Check flags
foreach $s (@sf) {
print "\tfchkf$s _start\n";
}
print "\n";
# Misc
print "\tbreak.f 0\n";
print "\tnop.f 0\n";
print "\n";

481
gas/testsuite/gas/ia64/opc-f.s Normal file
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@ -0,0 +1,481 @@
.text
.type _start,@function
_start:
fma f4 = f5, f6, f7
fma.s0 f4 = f5, f6, f7
fma.s1 f4 = f5, f6, f7
fma.s2 f4 = f5, f6, f7
fma.s3 f4 = f5, f6, f7
fma.s f4 = f5, f6, f7
fma.s.s0 f4 = f5, f6, f7
fma.s.s1 f4 = f5, f6, f7
fma.s.s2 f4 = f5, f6, f7
fma.s.s3 f4 = f5, f6, f7
fma.d f4 = f5, f6, f7
fma.d.s0 f4 = f5, f6, f7
fma.d.s1 f4 = f5, f6, f7
fma.d.s2 f4 = f5, f6, f7
fma.d.s3 f4 = f5, f6, f7
fpma f4 = f5, f6, f7
fpma.s0 f4 = f5, f6, f7
fpma.s1 f4 = f5, f6, f7
fpma.s2 f4 = f5, f6, f7
fpma.s3 f4 = f5, f6, f7
fms f4 = f5, f6, f7
fms.s0 f4 = f5, f6, f7
fms.s1 f4 = f5, f6, f7
fms.s2 f4 = f5, f6, f7
fms.s3 f4 = f5, f6, f7
fms.s f4 = f5, f6, f7
fms.s.s0 f4 = f5, f6, f7
fms.s.s1 f4 = f5, f6, f7
fms.s.s2 f4 = f5, f6, f7
fms.s.s3 f4 = f5, f6, f7
fms.d f4 = f5, f6, f7
fms.d.s0 f4 = f5, f6, f7
fms.d.s1 f4 = f5, f6, f7
fms.d.s2 f4 = f5, f6, f7
fms.d.s3 f4 = f5, f6, f7
fpms f4 = f5, f6, f7
fpms.s0 f4 = f5, f6, f7
fpms.s1 f4 = f5, f6, f7
fpms.s2 f4 = f5, f6, f7
fpms.s3 f4 = f5, f6, f7
fnma f4 = f5, f6, f7
fnma.s0 f4 = f5, f6, f7
fnma.s1 f4 = f5, f6, f7
fnma.s2 f4 = f5, f6, f7
fnma.s3 f4 = f5, f6, f7
fnma.s f4 = f5, f6, f7
fnma.s.s0 f4 = f5, f6, f7
fnma.s.s1 f4 = f5, f6, f7
fnma.s.s2 f4 = f5, f6, f7
fnma.s.s3 f4 = f5, f6, f7
fnma.d f4 = f5, f6, f7
fnma.d.s0 f4 = f5, f6, f7
fnma.d.s1 f4 = f5, f6, f7
fnma.d.s2 f4 = f5, f6, f7
fnma.d.s3 f4 = f5, f6, f7
fpnma f4 = f5, f6, f7
fpnma.s0 f4 = f5, f6, f7
fpnma.s1 f4 = f5, f6, f7
fpnma.s2 f4 = f5, f6, f7
fpnma.s3 f4 = f5, f6, f7
fmpy f4 = f5, f6
fmpy.s0 f4 = f5, f6
fmpy.s1 f4 = f5, f6
fmpy.s2 f4 = f5, f6
fmpy.s3 f4 = f5, f6
fmpy.s f4 = f5, f6
fmpy.s.s0 f4 = f5, f6
fmpy.s.s1 f4 = f5, f6
fmpy.s.s2 f4 = f5, f6
fmpy.s.s3 f4 = f5, f6
fmpy.d f4 = f5, f6
fmpy.d.s0 f4 = f5, f6
fmpy.d.s1 f4 = f5, f6
fmpy.d.s2 f4 = f5, f6
fmpy.d.s3 f4 = f5, f6
fpmpy f4 = f5, f6
fpmpy.s0 f4 = f5, f6
fpmpy.s1 f4 = f5, f6
fpmpy.s2 f4 = f5, f6
fpmpy.s3 f4 = f5, f6
fadd f4 = f5, f6
fadd.s0 f4 = f5, f6
fadd.s1 f4 = f5, f6
fadd.s2 f4 = f5, f6
fadd.s3 f4 = f5, f6
fadd.s f4 = f5, f6
fadd.s.s0 f4 = f5, f6
fadd.s.s1 f4 = f5, f6
fadd.s.s2 f4 = f5, f6
fadd.s.s3 f4 = f5, f6
fadd.d f4 = f5, f6
fadd.d.s0 f4 = f5, f6
fadd.d.s1 f4 = f5, f6
fadd.d.s2 f4 = f5, f6
fadd.d.s3 f4 = f5, f6
fsub f4 = f5, f6
fsub.s0 f4 = f5, f6
fsub.s1 f4 = f5, f6
fsub.s2 f4 = f5, f6
fsub.s3 f4 = f5, f6
fsub.s f4 = f5, f6
fsub.s.s0 f4 = f5, f6
fsub.s.s1 f4 = f5, f6
fsub.s.s2 f4 = f5, f6
fsub.s.s3 f4 = f5, f6
fsub.d f4 = f5, f6
fsub.d.s0 f4 = f5, f6
fsub.d.s1 f4 = f5, f6
fsub.d.s2 f4 = f5, f6
fsub.d.s3 f4 = f5, f6
fpsub f4 = f5, f6
fpsub.s0 f4 = f5, f6
fpsub.s1 f4 = f5, f6
fpsub.s2 f4 = f5, f6
fpsub.s3 f4 = f5, f6
fnmpy f4 = f5, f6
fnmpy.s0 f4 = f5, f6
fnmpy.s1 f4 = f5, f6
fnmpy.s2 f4 = f5, f6
fnmpy.s3 f4 = f5, f6
fnmpy.s f4 = f5, f6
fnmpy.s.s0 f4 = f5, f6
fnmpy.s.s1 f4 = f5, f6
fnmpy.s.s2 f4 = f5, f6
fnmpy.s.s3 f4 = f5, f6
fnmpy.d f4 = f5, f6
fnmpy.d.s0 f4 = f5, f6
fnmpy.d.s1 f4 = f5, f6
fnmpy.d.s2 f4 = f5, f6
fnmpy.d.s3 f4 = f5, f6
fpnmpy f4 = f5, f6
fpnmpy.s0 f4 = f5, f6
fpnmpy.s1 f4 = f5, f6
fpnmpy.s2 f4 = f5, f6
fpnmpy.s3 f4 = f5, f6
fnorm f4 = f5
fnorm.s0 f4 = f5
fnorm.s1 f4 = f5
fnorm.s2 f4 = f5
fnorm.s3 f4 = f5
fnorm.s f4 = f5
fnorm.s.s0 f4 = f5
fnorm.s.s1 f4 = f5
fnorm.s.s2 f4 = f5
fnorm.s.s3 f4 = f5
fnorm.d f4 = f5
fnorm.d.s0 f4 = f5
fnorm.d.s1 f4 = f5
fnorm.d.s2 f4 = f5
fnorm.d.s3 f4 = f5
xma.l f4 = f5, f6, f7
xma.lu f4 = f5, f6, f7
xma.h f4 = f5, f6, f7
xma.hu f4 = f5, f6, f7
xmpy.l f4 = f5, f6
xmpy.lu f4 = f5, f6
xmpy.h f4 = f5, f6
xmpy.hu f4 = f5, f6
fselect f4 = f5, f6, f7
fclass.m p3, p4 = f4, @nat
fclass.nm p3, p4 = f4, @nat
fclass.m p3, p4 = f4, @qnan
fclass.nm p3, p4 = f4, @qnan
fclass.m p3, p4 = f4, @snan
fclass.nm p3, p4 = f4, @snan
fclass.m p3, p4 = f4, @pos
fclass.nm p3, p4 = f4, @pos
fclass.m p3, p4 = f4, @neg
fclass.nm p3, p4 = f4, @neg
fclass.m p3, p4 = f4, @unorm
fclass.nm p3, p4 = f4, @unorm
fclass.m p3, p4 = f4, @norm
fclass.nm p3, p4 = f4, @norm
fclass.m p3, p4 = f4, @inf
fclass.nm p3, p4 = f4, @inf
fclass.m p3, p4 = f4, 0x1ff
fclass.nm p3, p4 = f4, 0x1ff
fclass.m.unc p3, p4 = f4, @nat
fclass.nm.unc p3, p4 = f4, @nat
fclass.m.unc p3, p4 = f4, @qnan
fclass.nm.unc p3, p4 = f4, @qnan
fclass.m.unc p3, p4 = f4, @snan
fclass.nm.unc p3, p4 = f4, @snan
fclass.m.unc p3, p4 = f4, @pos
fclass.nm.unc p3, p4 = f4, @pos
fclass.m.unc p3, p4 = f4, @neg
fclass.nm.unc p3, p4 = f4, @neg
fclass.m.unc p3, p4 = f4, @unorm
fclass.nm.unc p3, p4 = f4, @unorm
fclass.m.unc p3, p4 = f4, @norm
fclass.nm.unc p3, p4 = f4, @norm
fclass.m.unc p3, p4 = f4, @inf
fclass.nm.unc p3, p4 = f4, @inf
fclass.m.unc p3, p4 = f4, 0x1ff
fclass.nm.unc p3, p4 = f4, 0x1ff
frcpa f4, p5 = f6, f7
frcpa.s0 f4, p5 = f6, f7
frcpa.s1 f4, p5 = f6, f7
frcpa.s2 f4, p5 = f6, f7
frcpa.s3 f4, p5 = f6, f7
fprcpa f4, p5 = f6, f7
fprcpa.s0 f4, p5 = f6, f7
fprcpa.s1 f4, p5 = f6, f7
fprcpa.s2 f4, p5 = f6, f7
fprcpa.s3 f4, p5 = f6, f7
frsqrta f4, p5 = f6
frsqrta.s0 f4, p5 = f6
frsqrta.s1 f4, p5 = f6
frsqrta.s2 f4, p5 = f6
frsqrta.s3 f4, p5 = f6
fprsqrta f4, p5 = f6
fprsqrta.s0 f4, p5 = f6
fprsqrta.s1 f4, p5 = f6
fprsqrta.s2 f4, p5 = f6
fprsqrta.s3 f4, p5 = f6
fmin f4 = f5, f6
fmin.s0 f4 = f5, f6
fmin.s1 f4 = f5, f6
fmin.s2 f4 = f5, f6
fmin.s3 f4 = f5, f6
fmax f4 = f5, f6
fmax.s0 f4 = f5, f6
fmax.s1 f4 = f5, f6
fmax.s2 f4 = f5, f6
fmax.s3 f4 = f5, f6
famin f4 = f5, f6
famin.s0 f4 = f5, f6
famin.s1 f4 = f5, f6
famin.s2 f4 = f5, f6
famin.s3 f4 = f5, f6
famax f4 = f5, f6
famax.s0 f4 = f5, f6
famax.s1 f4 = f5, f6
famax.s2 f4 = f5, f6
famax.s3 f4 = f5, f6
fpmin f4 = f5, f6
fpmin.s0 f4 = f5, f6
fpmin.s1 f4 = f5, f6
fpmin.s2 f4 = f5, f6
fpmin.s3 f4 = f5, f6
fpmax f4 = f5, f6
fpmax.s0 f4 = f5, f6
fpmax.s1 f4 = f5, f6
fpmax.s2 f4 = f5, f6
fpmax.s3 f4 = f5, f6
fpamin f4 = f5, f6
fpamin.s0 f4 = f5, f6
fpamin.s1 f4 = f5, f6
fpamin.s2 f4 = f5, f6
fpamin.s3 f4 = f5, f6
fpamax f4 = f5, f6
fpamax.s0 f4 = f5, f6
fpamax.s1 f4 = f5, f6
fpamax.s2 f4 = f5, f6
fpamax.s3 f4 = f5, f6
fcmp.eq p3, p4 = f4, f5
fcmp.eq.s0 p3, p4 = f4, f5
fcmp.eq.s1 p3, p4 = f4, f5
fcmp.eq.s2 p3, p4 = f4, f5
fcmp.eq.s3 p3, p4 = f4, f5
fcmp.lt p3, p4 = f4, f5
fcmp.lt.s0 p3, p4 = f4, f5
fcmp.lt.s1 p3, p4 = f4, f5
fcmp.lt.s2 p3, p4 = f4, f5
fcmp.lt.s3 p3, p4 = f4, f5
fcmp.le p3, p4 = f4, f5
fcmp.le.s0 p3, p4 = f4, f5
fcmp.le.s1 p3, p4 = f4, f5
fcmp.le.s2 p3, p4 = f4, f5
fcmp.le.s3 p3, p4 = f4, f5
fcmp.unord p3, p4 = f4, f5
fcmp.unord.s0 p3, p4 = f4, f5
fcmp.unord.s1 p3, p4 = f4, f5
fcmp.unord.s2 p3, p4 = f4, f5
fcmp.unord.s3 p3, p4 = f4, f5
fcmp.gt p3, p4 = f4, f5
fcmp.gt.s0 p3, p4 = f4, f5
fcmp.gt.s1 p3, p4 = f4, f5
fcmp.gt.s2 p3, p4 = f4, f5
fcmp.gt.s3 p3, p4 = f4, f5
fcmp.ge p3, p4 = f4, f5
fcmp.ge.s0 p3, p4 = f4, f5
fcmp.ge.s1 p3, p4 = f4, f5
fcmp.ge.s2 p3, p4 = f4, f5
fcmp.ge.s3 p3, p4 = f4, f5
fcmp.neq p3, p4 = f4, f5
fcmp.neq.s0 p3, p4 = f4, f5
fcmp.neq.s1 p3, p4 = f4, f5
fcmp.neq.s2 p3, p4 = f4, f5
fcmp.neq.s3 p3, p4 = f4, f5
fcmp.nlt p3, p4 = f4, f5
fcmp.nlt.s0 p3, p4 = f4, f5
fcmp.nlt.s1 p3, p4 = f4, f5
fcmp.nlt.s2 p3, p4 = f4, f5
fcmp.nlt.s3 p3, p4 = f4, f5
fcmp.nle p3, p4 = f4, f5
fcmp.nle.s0 p3, p4 = f4, f5
fcmp.nle.s1 p3, p4 = f4, f5
fcmp.nle.s2 p3, p4 = f4, f5
fcmp.nle.s3 p3, p4 = f4, f5
fcmp.ngt p3, p4 = f4, f5
fcmp.ngt.s0 p3, p4 = f4, f5
fcmp.ngt.s1 p3, p4 = f4, f5
fcmp.ngt.s2 p3, p4 = f4, f5
fcmp.ngt.s3 p3, p4 = f4, f5
fcmp.nge p3, p4 = f4, f5
fcmp.nge.s0 p3, p4 = f4, f5
fcmp.nge.s1 p3, p4 = f4, f5
fcmp.nge.s2 p3, p4 = f4, f5
fcmp.nge.s3 p3, p4 = f4, f5
fcmp.ord p3, p4 = f4, f5
fcmp.ord.s0 p3, p4 = f4, f5
fcmp.ord.s1 p3, p4 = f4, f5
fcmp.ord.s2 p3, p4 = f4, f5
fcmp.ord.s3 p3, p4 = f4, f5
fmerge.s f4 = f5, f6
fmerge.ns f4 = f5, f6
fmerge.se f4 = f5, f6
fmix.lr f4 = f5, f6
fmix.r f4 = f5, f6
fmix.l f4 = f5, f6
fsxt.l f4 = f5, f6
fpack f4 = f5, f6
fswap f4 = f5, f6
fswap.nl f4 = f5, f6
fswap.nr f4 = f5, f6
fand f4 = f5, f6
fandcm f4 = f5, f6
for f4 = f5, f6
fxor f4 = f5, f6
fpmerge.s f4 = f5, f6
fpmerge.ns f4 = f5, f6
fpmerge.se f4 = f5, f6
fabs f4 = f5
fneg f4 = f5
fnegabs f4 = f5
fpabs f4 = f5
fpneg f4 = f5
fpnegabs f4 = f5
fcvt.fx f4 = f5
fcvt.fx.s0 f4 = f5
fcvt.fx.s1 f4 = f5
fcvt.fx.s2 f4 = f5
fcvt.fx.s3 f4 = f5
fcvt.fx.trunc f4 = f5
fcvt.fx.trunc.s0 f4 = f5
fcvt.fx.trunc.s1 f4 = f5
fcvt.fx.trunc.s2 f4 = f5
fcvt.fx.trunc.s3 f4 = f5
fcvt.fxu f4 = f5
fcvt.fxu.s0 f4 = f5
fcvt.fxu.s1 f4 = f5
fcvt.fxu.s2 f4 = f5
fcvt.fxu.s3 f4 = f5
fcvt.fxu.trunc f4 = f5
fcvt.fxu.trunc.s0 f4 = f5
fcvt.fxu.trunc.s1 f4 = f5
fcvt.fxu.trunc.s2 f4 = f5
fcvt.fxu.trunc.s3 f4 = f5
fpcvt.fx f4 = f5
fpcvt.fx.s0 f4 = f5
fpcvt.fx.s1 f4 = f5
fpcvt.fx.s2 f4 = f5
fpcvt.fx.s3 f4 = f5
fpcvt.fx.trunc f4 = f5
fpcvt.fx.trunc.s0 f4 = f5
fpcvt.fx.trunc.s1 f4 = f5
fpcvt.fx.trunc.s2 f4 = f5
fpcvt.fx.trunc.s3 f4 = f5
fpcvt.fxu f4 = f5
fpcvt.fxu.s0 f4 = f5
fpcvt.fxu.s1 f4 = f5
fpcvt.fxu.s2 f4 = f5
fpcvt.fxu.s3 f4 = f5
fpcvt.fxu.trunc f4 = f5
fpcvt.fxu.trunc.s0 f4 = f5
fpcvt.fxu.trunc.s1 f4 = f5
fpcvt.fxu.trunc.s2 f4 = f5
fpcvt.fxu.trunc.s3 f4 = f5
fcvt.xf f4 = f5
fcvt.xuf f4 = f5
fsetc 0, 0
fsetc 0x3f, 0x3f
fsetc.s0 0, 0
fsetc.s0 0x3f, 0x3f
fsetc.s1 0, 0
fsetc.s1 0x3f, 0x3f
fsetc.s2 0, 0
fsetc.s2 0x3f, 0x3f
fsetc.s3 0, 0
fsetc.s3 0x3f, 0x3f
fclrf
fclrf.s0
fclrf.s1
fclrf.s2
fclrf.s3
fchkf _start
fchkf.s0 _start
fchkf.s1 _start
fchkf.s2 _start
fchkf.s3 _start
break.f 0
nop.f 0

245
gas/testsuite/gas/ia64/opc-i.d Normal file
View File

@ -0,0 +1,245 @@
# objdump: -d
# name: ia64 opc-i
.*: +file format .*
Disassembly of section \.text:
0000000000000000 <_start>:
0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
6: 40 28 18 8c 38 80 pmpyshr2 r4=r5,r6,0
c: 50 30 68 71 pmpyshr2\.u r4=r5,r6,16
10: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
16: 40 28 18 b4 3a 80 pmpy2\.r r4=r5,r6
1c: 50 30 78 75 pmpy2\.l r4=r5,r6
20: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
26: 40 28 18 20 3a 80 mix1\.r r4=r5,r6
2c: 50 30 40 75 mix2\.r r4=r5,r6
30: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
36: 40 28 18 20 3e 80 mix4\.r r4=r5,r6
3c: 50 30 50 74 mix1\.l r4=r5,r6
40: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
46: 40 28 18 a8 3a 80 mix2\.l r4=r5,r6
4c: 50 30 50 7c mix4\.l r4=r5,r6
50: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
56: 40 28 18 80 3a 80 pack2\.uss r4=r5,r6
5c: 50 30 10 75 pack2\.sss r4=r5,r6
60: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
66: 40 28 18 08 3e 80 pack4\.sss r4=r5,r6
6c: 50 30 20 74 unpack1\.h r4=r5,r6
70: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
76: 40 28 18 90 3a 80 unpack2\.h r4=r5,r6
7c: 50 30 20 7c unpack4\.h r4=r5,r6
80: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
86: 40 28 18 18 3a 80 unpack1\.l r4=r5,r6
8c: 50 30 30 75 unpack2\.l r4=r5,r6
90: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
96: 40 28 18 18 3e 80 unpack4\.l r4=r5,r6
9c: 50 30 08 74 pmin1\.u r4=r5,r6
a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
a6: 40 28 18 14 3a 80 pmax1\.u r4=r5,r6
ac: 50 30 18 75 pmin2\.u r4=r5,r6
b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
b6: 40 28 18 9c 3a 80 pmax2\.u r4=r5,r6
bc: 50 30 58 74 psad1 r4=r5,r6
c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
c6: 40 28 2c 28 3b 80 mux1 r4=r5,@rev
cc: 50 40 50 76 mux1 r4=r5,@mix
d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
d6: 40 28 24 28 3b 80 mux1 r4=r5,@shuf
dc: 50 50 50 76 mux1 r4=r5,@alt
e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
e6: 40 28 00 28 3b 80 mux1 r4=r5,@brcst
ec: 50 00 50 77 mux2 r4=r5,0x0
f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
f6: 40 28 fc ab 3b 80 mux2 r4=r5,0xff
fc: 50 50 55 77 mux2 r4=r5,0xaa
100: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
106: 40 30 14 88 38 80 pshr2 r4=r5,r6
10c: 00 28 18 73 pshr2 r4=r5,0
110: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
116: 40 80 14 8c 39 80 pshr2 r4=r5,8
11c: e0 2b 18 73 pshr2 r4=r5,31
120: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
126: 40 30 14 08 3c 80 pshr4 r4=r5,r6
12c: 00 28 18 7a pshr4 r4=r5,0
130: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
136: 40 80 14 0c 3d 80 pshr4 r4=r5,8
13c: e0 2b 18 7a pshr4 r4=r5,31
140: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
146: 40 30 14 80 38 80 pshr2\.u r4=r5,r6
14c: 00 28 08 73 pshr2\.u r4=r5,0
150: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
156: 40 80 14 84 39 80 pshr2\.u r4=r5,8
15c: e0 2b 08 73 pshr2\.u r4=r5,31
160: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
166: 40 30 14 00 3c 80 pshr4\.u r4=r5,r6
16c: 00 28 08 7a pshr4\.u r4=r5,0
170: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
176: 40 80 14 04 3d 80 pshr4\.u r4=r5,8
17c: e0 2b 08 7a pshr4\.u r4=r5,31
180: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
186: 40 30 14 88 3c 80 shr r4=r5,r6
18c: 60 28 00 79 shr\.u r4=r5,r6
190: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
196: 40 28 18 90 38 80 pshl2 r4=r5,r6
19c: 50 f8 28 77 pshl2 r4=r5,0
1a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
1a6: 40 28 5c 94 3b 80 pshl2 r4=r5,8
1ac: 50 00 28 77 pshl2 r4=r5,31
1b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
1b6: 40 28 18 10 3c 80 pshl4 r4=r5,r6
1bc: 50 f8 28 7e pshl4 r4=r5,0
1c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
1c6: 40 28 5c 14 3f 80 pshl4 r4=r5,8
1cc: 50 00 28 7e pshl4 r4=r5,31
1d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
1d6: 40 28 18 90 3c 80 shl r4=r5,r6
1dc: 00 28 48 73 popcnt r4=r5
1e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
1e6: 40 28 18 00 2b 80 shrp r4=r5,r6,0
1ec: 50 30 30 56 shrp r4=r5,r6,12
1f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
1f6: 40 28 18 7e 2b 80 shrp r4=r5,r6,63
1fc: 10 28 3c 52 extr r4=r5,0,16
200: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
206: 40 08 14 7c 29 80 extr r4=r5,0,63
20c: 50 29 9c 52 extr r4=r5,10,40
210: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
216: 40 00 14 1e 29 80 extr\.u r4=r5,0,16
21c: 00 28 f8 52 extr\.u r4=r5,0,63
220: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
226: 40 a0 14 4e 29 80 extr\.u r4=r5,10,40
22c: 50 f8 3d 53 dep\.z r4=r5,0,16
230: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
236: 40 28 fc fc 29 80 dep\.z r4=r5,0,63
23c: 50 a8 9d 53 dep\.z r4=r5,10,40
240: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
246: 40 00 fc 9f 29 80 dep\.z r4=0,0,16
24c: f0 ff fb 53 dep\.z r4=127,0,63
250: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
256: 40 00 e8 e3 2d 80 dep\.z r4=-128,5,50
25c: 50 ad 9f 53 dep\.z r4=85,10,40
260: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
266: 40 f0 17 9e 2b 80 dep r4=0,r5,0,16
26c: e0 2f f8 5f dep r4=-1,r5,0,63
270: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0
276: 00 00 00 02 00 80 nop\.f 0x0
27c: 50 30 58 4d dep r4=r5,r6,10,7
280: 04 00 00 00 01 00 \[MLI\] nop\.m 0x0
286: 00 00 00 00 00 80 movl r4=0x0
28c: 00 00 00 60
290: 04 00 00 00 01 c0 \[MLI\] nop\.m 0x0
296: ff ff ff ff 7f 80 movl r4=0xffffffffffffffff
29c: f0 f7 ff 6f
2a0: 04 00 00 00 01 80 \[MLI\] nop\.m 0x0
2a6: 90 78 56 34 12 80 movl r4=0x1234567890abcdef
2ac: f0 76 6d 66
2b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
2b6: 00 00 00 00 00 e0 break\.i 0x0
2bc: ff ff 01 08 break\.i 0x1fffff
2c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
2c6: 00 00 00 02 00 e0 nop\.i 0x0
2cc: ff ff 05 08 nop\.i 0x1fffff
2d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
2d6: 30 25 fc ff 04 80 chk\.s\.i r4,0 <_start>
2dc: 00 00 c4 00 mov r4=b0
2e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
2e6: 00 20 04 80 03 00 mov b0=r4
2ec: 40 00 00 03 mov pr=r4,0x0
2f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
2f6: a0 21 80 84 01 e0 mov pr=r4,0x1234
2fc: 4f 80 7f 0b mov pr=r4,0xfffffffffffffffe
300: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
306: 00 00 00 00 01 e0 mov pr\.rot=0x0
30c: 7f 00 00 02 mov pr\.rot=0x3ff0000
310: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
316: 00 c0 ff 7f 05 80 mov pr\.rot=0xfffffffffc000000
31c: 00 28 40 00 zxt1 r4=r5
320: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
326: 40 00 14 22 00 80 zxt2 r4=r5
32c: 00 28 48 00 zxt4 r4=r5
330: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
336: 40 00 14 28 00 80 sxt1 r4=r5
33c: 00 28 54 00 sxt2 r4=r5
340: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
346: 40 00 14 2c 00 80 sxt4 r4=r5
34c: 00 28 60 00 czx1\.l r4=r5
350: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
356: 40 00 14 32 00 80 czx2\.l r4=r5
35c: 00 28 70 00 czx1\.r r4=r5
360: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
366: 40 00 14 3a 00 40 czx2\.r r4=r5
36c: 00 20 0c 50 tbit\.z p2,p3=r4,0
370: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
376: 20 14 10 06 28 40 tbit\.z\.unc p2,p3=r4,1
37c: 40 20 0c 58 tbit\.z\.and p2,p3=r4,2
380: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
386: 20 30 10 86 28 40 tbit\.z\.or p2,p3=r4,3
38c: 80 20 0c 59 tbit\.z\.or\.andcm p2,p3=r4,4
390: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
396: 20 54 10 86 28 40 tbit\.nz\.or p2,p3=r4,5
39c: c8 20 0c 58 tbit\.nz\.and p2,p3=r4,6
3a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
3a6: 30 74 10 84 2c 60 tbit\.nz\.or\.andcm p3,p2=r4,7
3ac: 00 21 08 50 tbit\.z p3,p2=r4,8
3b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
3b6: 30 94 10 04 28 40 tbit\.z\.unc p3,p2=r4,9
3bc: 48 21 0c 58 tbit\.nz\.and p2,p3=r4,10
3c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
3c6: 20 b4 10 86 28 40 tbit\.nz\.or p2,p3=r4,11
3cc: 88 21 0c 59 tbit\.nz\.or\.andcm p2,p3=r4,12
3d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
3d6: 20 d0 10 86 28 40 tbit\.z\.or p2,p3=r4,13
3dc: c0 21 0c 58 tbit\.z\.and p2,p3=r4,14
3e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
3e6: 30 f0 10 84 2c 40 tbit\.z\.or\.andcm p3,p2=r4,15
3ec: 10 20 0c 50 tnat\.z p2,p3=r4
3f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
3f6: 20 0c 10 06 28 40 tnat\.z\.unc p2,p3=r4
3fc: 10 20 0c 58 tnat\.z\.and p2,p3=r4
400: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
406: 20 08 10 86 28 40 tnat\.z\.or p2,p3=r4
40c: 10 20 0c 59 tnat\.z\.or\.andcm p2,p3=r4
410: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
416: 20 0c 10 86 28 40 tnat\.nz\.or p2,p3=r4
41c: 18 20 0c 58 tnat\.nz\.and p2,p3=r4
420: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
426: 30 0c 10 84 2c 60 tnat\.nz\.or\.andcm p3,p2=r4
42c: 10 20 08 50 tnat\.z p3,p2=r4
430: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
436: 30 0c 10 04 28 40 tnat\.z\.unc p3,p2=r4
43c: 18 20 0c 58 tnat\.nz\.and p2,p3=r4
440: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
446: 20 0c 10 86 28 40 tnat\.nz\.or p2,p3=r4
44c: 18 20 0c 59 tnat\.nz\.or\.andcm p2,p3=r4
450: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
456: 20 08 10 86 28 40 tnat\.z\.or p2,p3=r4
45c: 10 20 0c 58 tnat\.z\.and p2,p3=r4
460: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
466: 30 08 10 84 2c 60 tnat\.z\.or\.andcm p3,p2=r4
46c: 40 88 04 07 mov b3=r4
470: 01 00 00 00 01 00 \[MII\] nop\.m 0x0
476: 30 20 24 84 03 00 mov\.imp b3=r4,570 <_start\+0x570>
47c: 00 00 04 00 nop\.i 0x0;;
\.\.\.
570: 01 00 00 00 01 00 \[MII\] nop\.m 0x0
576: 30 20 00 84 03 60 mov\.sptk b3=r4,670 <_start\+0x670>
57c: 40 40 08 07 mov\.sptk\.imp b3=r4,670 <_start\+0x670>;;
\.\.\.
670: 01 00 00 00 01 00 \[MII\] nop\.m 0x0
676: 30 20 08 84 03 60 mov\.dptk b3=r4,770 <_start\+0x770>
67c: 40 50 08 07 mov\.dptk\.imp b3=r4,770 <_start\+0x770>;;
\.\.\.
770: 01 00 00 00 01 00 \[MII\] nop\.m 0x0
776: 30 20 14 84 03 60 mov\.ret b3=r4,870 <_start\+0x870>
77c: 40 68 08 07 mov\.ret\.imp b3=r4,870 <_start\+0x870>;;
\.\.\.
870: 01 00 00 00 01 00 \[MII\] nop\.m 0x0
876: 30 20 10 84 03 60 mov\.ret\.sptk b3=r4,970 <_start\+0x970>
87c: 40 60 08 07 mov\.ret\.sptk\.imp b3=r4,970 <_start\+0x970>;;
\.\.\.
970: 01 00 00 00 01 00 \[MII\] nop\.m 0x0
976: 30 20 18 84 03 60 mov\.ret\.dptk b3=r4,a70 <_start\+0xa70>
97c: 40 70 08 07 mov\.ret\.dptk\.imp b3=r4,a70 <_start\+0xa70>;;
\.\.\.

186
gas/testsuite/gas/ia64/opc-i.pl Normal file
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$AT = '@';
print <<END
.text
.type _start,${AT}function
_start:
pmpyshr2 r4 = r5, r6, 0
pmpyshr2.u r4 = r5, r6, 16
pmpy2.r r4 = r5, r6
pmpy2.l r4 = r5, r6
mix1.r r4 = r5, r6
mix2.r r4 = r5, r6
mix4.r r4 = r5, r6
mix1.l r4 = r5, r6
mix2.l r4 = r5, r6
mix4.l r4 = r5, r6
pack2.uss r4 = r5, r6
pack2.sss r4 = r5, r6
pack4.sss r4 = r5, r6
unpack1.h r4 = r5, r6
unpack2.h r4 = r5, r6
unpack4.h r4 = r5, r6
unpack1.l r4 = r5, r6
unpack2.l r4 = r5, r6
unpack4.l r4 = r5, r6
pmin1.u r4 = r5, r6
pmax1.u r4 = r5, r6
pmin2 r4 = r5, r6
pmax2 r4 = r5, r6
psad1 r4 = r5, r6
mux1 r4 = r5, ${AT}rev
mux1 r4 = r5, ${AT}mix
mux1 r4 = r5, ${AT}shuf
mux1 r4 = r5, ${AT}alt
mux1 r4 = r5, ${AT}brcst
mux2 r4 = r5, 0
mux2 r4 = r5, 0xff
mux2 r4 = r5, 0xaa
pshr2 r4 = r5, r6
pshr2 r4 = r5, 0
pshr2 r4 = r5, 8
pshr2 r4 = r5, 31
pshr4 r4 = r5, r6
pshr4 r4 = r5, 0
pshr4 r4 = r5, 8
pshr4 r4 = r5, 31
pshr2.u r4 = r5, r6
pshr2.u r4 = r5, 0
pshr2.u r4 = r5, 8
pshr2.u r4 = r5, 31
pshr4.u r4 = r5, r6
pshr4.u r4 = r5, 0
pshr4.u r4 = r5, 8
pshr4.u r4 = r5, 31
shr r4 = r5, r6
shr.u r4 = r5, r6
pshl2 r4 = r5, r6
pshl2 r4 = r5, 0
pshl2 r4 = r5, 8
pshl2 r4 = r5, 31
pshl4 r4 = r5, r6
pshl4 r4 = r5, 0
pshl4 r4 = r5, 8
pshl4 r4 = r5, 31
shl r4 = r5, r6
popcnt r4 = r5
shrp r4 = r5, r6, 0
shrp r4 = r5, r6, 12
shrp r4 = r5, r6, 63
extr r4 = r5, 0, 16
extr r4 = r5, 0, 63
extr r4 = r5, 10, 40
extr.u r4 = r5, 0, 16
extr.u r4 = r5, 0, 63
extr.u r4 = r5, 10, 40
dep.z r4 = r5, 0, 16
dep.z r4 = r5, 0, 63
dep.z r4 = r5, 10, 40
dep.z r4 = 0, 0, 16
dep.z r4 = 127, 0, 63
dep.z r4 = -128, 5, 50
dep.z r4 = 0x55, 10, 40
dep r4 = 0, r5, 0, 16
dep r4 = -1, r5, 0, 63
dep r4 = r5, r6, 10, 7
movl r4 = 0
movl r4 = 0xffffffffffffffff
movl r4 = 0x1234567890abcdef
break.i 0
break.i 0x1fffff
nop.i 0
nop.i 0x1fffff
chk.s.i r4, _start
mov r4 = b0
mov b0 = r4
mov pr = r4, 0
mov pr = r4, 0x1234
mov pr = r4, 0x1ffff
mov pr.rot = 0
// ??? This was originally 0x3ffffff, but that generates an assembler warning
// that the testsuite infrastructure isn't set up to ignore.
mov pr.rot = 0x3ff0000
mov pr.rot = -0x4000000
zxt1 r4 = r5
zxt2 r4 = r5
zxt4 r4 = r5
sxt1 r4 = r5
sxt2 r4 = r5
sxt4 r4 = r5
czx1.l r4 = r5
czx2.l r4 = r5
czx1.r r4 = r5
czx2.r r4 = r5
END
;
@ctype = ( "", ".unc", ".and", ".or", ".or.andcm", ".orcm",
".andcm", ".and.orcm" );
$i = 0;
foreach $z ( ".z", ".nz" ) {
foreach $c (@ctype) {
print "\ttbit${z}${c} p2, p3 = r4, $i\n";
++$i;
}
}
print "\n";
foreach $z ( ".z", ".nz" ) {
foreach $c (@ctype) {
print "\ttnat${z}${c} p2, p3 = r4\n";
}
}
print "\n";
@mwh = ( "", ".sptk", ".dptk" );
@ih = ( "", ".imp" );
$LAB = 1;
foreach $b ("", ".ret") {
foreach $w (@mwh) {
foreach $i (@ih) {
print "\tmov${b}${w}${i} b3 = r4, .L${LAB}\n";
}
print ".space 240\n";
print ".L${LAB}:\n";
++$LAB;
}
print "\n";
}

383
gas/testsuite/gas/ia64/opc-i.s Normal file
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@ -0,0 +1,383 @@
.text
.type _start,@function
_start:
pmpyshr2 r4 = r5, r6, 0
pmpyshr2.u r4 = r5, r6, 16
pmpy2.r r4 = r5, r6
pmpy2.l r4 = r5, r6
mix1.r r4 = r5, r6
mix2.r r4 = r5, r6
mix4.r r4 = r5, r6
mix1.l r4 = r5, r6
mix2.l r4 = r5, r6
mix4.l r4 = r5, r6
pack2.uss r4 = r5, r6
pack2.sss r4 = r5, r6
pack4.sss r4 = r5, r6
unpack1.h r4 = r5, r6
unpack2.h r4 = r5, r6
unpack4.h r4 = r5, r6
unpack1.l r4 = r5, r6
unpack2.l r4 = r5, r6
unpack4.l r4 = r5, r6
pmin1.u r4 = r5, r6
pmax1.u r4 = r5, r6
pmin2 r4 = r5, r6
pmax2 r4 = r5, r6
psad1 r4 = r5, r6
mux1 r4 = r5, @rev
mux1 r4 = r5, @mix
mux1 r4 = r5, @shuf
mux1 r4 = r5, @alt
mux1 r4 = r5, @brcst
mux2 r4 = r5, 0
mux2 r4 = r5, 0xff
mux2 r4 = r5, 0xaa
pshr2 r4 = r5, r6
pshr2 r4 = r5, 0
pshr2 r4 = r5, 8
pshr2 r4 = r5, 31
pshr4 r4 = r5, r6
pshr4 r4 = r5, 0
pshr4 r4 = r5, 8
pshr4 r4 = r5, 31
pshr2.u r4 = r5, r6
pshr2.u r4 = r5, 0
pshr2.u r4 = r5, 8
pshr2.u r4 = r5, 31
pshr4.u r4 = r5, r6
pshr4.u r4 = r5, 0
pshr4.u r4 = r5, 8
pshr4.u r4 = r5, 31
shr r4 = r5, r6
shr.u r4 = r5, r6
pshl2 r4 = r5, r6
pshl2 r4 = r5, 0
pshl2 r4 = r5, 8
pshl2 r4 = r5, 31
pshl4 r4 = r5, r6
pshl4 r4 = r5, 0
pshl4 r4 = r5, 8
pshl4 r4 = r5, 31
shl r4 = r5, r6
popcnt r4 = r5
shrp r4 = r5, r6, 0
shrp r4 = r5, r6, 12
shrp r4 = r5, r6, 63
extr r4 = r5, 0, 16
extr r4 = r5, 0, 63
extr r4 = r5, 10, 40
extr.u r4 = r5, 0, 16
extr.u r4 = r5, 0, 63
extr.u r4 = r5, 10, 40
dep.z r4 = r5, 0, 16
dep.z r4 = r5, 0, 63
dep.z r4 = r5, 10, 40
dep.z r4 = 0, 0, 16
dep.z r4 = 127, 0, 63
dep.z r4 = -128, 5, 50
dep.z r4 = 0x55, 10, 40
dep r4 = 0, r5, 0, 16
dep r4 = -1, r5, 0, 63
dep r4 = r5, r6, 10, 7
movl r4 = 0
movl r4 = 0xffffffffffffffff
movl r4 = 0x1234567890abcdef
break.i 0
break.i 0x1fffff
nop.i 0
nop.i 0x1fffff
chk.s.i r4, _start
mov r4 = b0
mov b0 = r4
mov pr = r4, 0
mov pr = r4, 0x1234
mov pr = r4, 0x1ffff
mov pr.rot = 0
mov pr.rot = 0x3ff0000
mov pr.rot = -0x4000000
zxt1 r4 = r5
zxt2 r4 = r5
zxt4 r4 = r5
sxt1 r4 = r5
sxt2 r4 = r5
sxt4 r4 = r5
czx1.l r4 = r5
czx2.l r4 = r5
czx1.r r4 = r5
czx2.r r4 = r5
tbit.z p2, p3 = r4, 0
tbit.z.unc p2, p3 = r4, 1
tbit.z.and p2, p3 = r4, 2
tbit.z.or p2, p3 = r4, 3
tbit.z.or.andcm p2, p3 = r4, 4
tbit.z.orcm p2, p3 = r4, 5
tbit.z.andcm p2, p3 = r4, 6
tbit.z.and.orcm p2, p3 = r4, 7
tbit.nz p2, p3 = r4, 8
tbit.nz.unc p2, p3 = r4, 9
tbit.nz.and p2, p3 = r4, 10
tbit.nz.or p2, p3 = r4, 11
tbit.nz.or.andcm p2, p3 = r4, 12
tbit.nz.orcm p2, p3 = r4, 13
tbit.nz.andcm p2, p3 = r4, 14
tbit.nz.and.orcm p2, p3 = r4, 15
tnat.z p2, p3 = r4
tnat.z.unc p2, p3 = r4
tnat.z.and p2, p3 = r4
tnat.z.or p2, p3 = r4
tnat.z.or.andcm p2, p3 = r4
tnat.z.orcm p2, p3 = r4
tnat.z.andcm p2, p3 = r4
tnat.z.and.orcm p2, p3 = r4
tnat.nz p2, p3 = r4
tnat.nz.unc p2, p3 = r4
tnat.nz.and p2, p3 = r4
tnat.nz.or p2, p3 = r4
tnat.nz.or.andcm p2, p3 = r4
tnat.nz.orcm p2, p3 = r4
tnat.nz.andcm p2, p3 = r4
tnat.nz.and.orcm p2, p3 = r4
mov.few.dc.dc b3 = r4, .L1
mov.few.dc.dc.imp b3 = r4, .L1
mov.few.dc.nt b3 = r4, .L1
mov.few.dc.nt.imp b3 = r4, .L1
mov.few.tk.dc b3 = r4, .L1
mov.few.tk.dc.imp b3 = r4, .L1
mov.few.tk.tk b3 = r4, .L1
mov.few.tk.tk.imp b3 = r4, .L1
mov.few.tk.nt b3 = r4, .L1
mov.few.tk.nt.imp b3 = r4, .L1
mov.few.nt.dc b3 = r4, .L1
mov.few.nt.dc.imp b3 = r4, .L1
mov.few.nt.tk b3 = r4, .L1
mov.few.nt.tk.imp b3 = r4, .L1
mov.few.nt.nt b3 = r4, .L1
mov.few.nt.nt.imp b3 = r4, .L1
.L1:
mov.many.dc.dc b3 = r4, .L2
mov.many.dc.dc.imp b3 = r4, .L2
mov.many.dc.nt b3 = r4, .L2
mov.many.dc.nt.imp b3 = r4, .L2
mov.many.tk.dc b3 = r4, .L2
mov.many.tk.dc.imp b3 = r4, .L2
mov.many.tk.tk b3 = r4, .L2
mov.many.tk.tk.imp b3 = r4, .L2
mov.many.tk.nt b3 = r4, .L2
mov.many.tk.nt.imp b3 = r4, .L2
mov.many.nt.dc b3 = r4, .L2
mov.many.nt.dc.imp b3 = r4, .L2
mov.many.nt.tk b3 = r4, .L2
mov.many.nt.tk.imp b3 = r4, .L2
mov.many.nt.nt b3 = r4, .L2
mov.many.nt.nt.imp b3 = r4, .L2
.L2:
mov.sptk.few.dc.dc b3 = r4, .L3
mov.sptk.few.dc.dc.imp b3 = r4, .L3
mov.sptk.few.dc.nt b3 = r4, .L3
mov.sptk.few.dc.nt.imp b3 = r4, .L3
mov.sptk.few.tk.dc b3 = r4, .L3
mov.sptk.few.tk.dc.imp b3 = r4, .L3
mov.sptk.few.tk.tk b3 = r4, .L3
mov.sptk.few.tk.tk.imp b3 = r4, .L3
mov.sptk.few.tk.nt b3 = r4, .L3
mov.sptk.few.tk.nt.imp b3 = r4, .L3
mov.sptk.few.nt.dc b3 = r4, .L3
mov.sptk.few.nt.dc.imp b3 = r4, .L3
mov.sptk.few.nt.tk b3 = r4, .L3
mov.sptk.few.nt.tk.imp b3 = r4, .L3
mov.sptk.few.nt.nt b3 = r4, .L3
mov.sptk.few.nt.nt.imp b3 = r4, .L3
.L3:
mov.sptk.many.dc.dc b3 = r4, .L4
mov.sptk.many.dc.dc.imp b3 = r4, .L4
mov.sptk.many.dc.nt b3 = r4, .L4
mov.sptk.many.dc.nt.imp b3 = r4, .L4
mov.sptk.many.tk.dc b3 = r4, .L4
mov.sptk.many.tk.dc.imp b3 = r4, .L4
mov.sptk.many.tk.tk b3 = r4, .L4
mov.sptk.many.tk.tk.imp b3 = r4, .L4
mov.sptk.many.tk.nt b3 = r4, .L4
mov.sptk.many.tk.nt.imp b3 = r4, .L4
mov.sptk.many.nt.dc b3 = r4, .L4
mov.sptk.many.nt.dc.imp b3 = r4, .L4
mov.sptk.many.nt.tk b3 = r4, .L4
mov.sptk.many.nt.tk.imp b3 = r4, .L4
mov.sptk.many.nt.nt b3 = r4, .L4
mov.sptk.many.nt.nt.imp b3 = r4, .L4
.L4:
mov.dptk.few.dc.dc b3 = r4, .L5
mov.dptk.few.dc.dc.imp b3 = r4, .L5
mov.dptk.few.dc.nt b3 = r4, .L5
mov.dptk.few.dc.nt.imp b3 = r4, .L5
mov.dptk.few.tk.dc b3 = r4, .L5
mov.dptk.few.tk.dc.imp b3 = r4, .L5
mov.dptk.few.tk.tk b3 = r4, .L5
mov.dptk.few.tk.tk.imp b3 = r4, .L5
mov.dptk.few.tk.nt b3 = r4, .L5
mov.dptk.few.tk.nt.imp b3 = r4, .L5
mov.dptk.few.nt.dc b3 = r4, .L5
mov.dptk.few.nt.dc.imp b3 = r4, .L5
mov.dptk.few.nt.tk b3 = r4, .L5
mov.dptk.few.nt.tk.imp b3 = r4, .L5
mov.dptk.few.nt.nt b3 = r4, .L5
mov.dptk.few.nt.nt.imp b3 = r4, .L5
.L5:
mov.dptk.many.dc.dc b3 = r4, .L6
mov.dptk.many.dc.dc.imp b3 = r4, .L6
mov.dptk.many.dc.nt b3 = r4, .L6
mov.dptk.many.dc.nt.imp b3 = r4, .L6
mov.dptk.many.tk.dc b3 = r4, .L6
mov.dptk.many.tk.dc.imp b3 = r4, .L6
mov.dptk.many.tk.tk b3 = r4, .L6
mov.dptk.many.tk.tk.imp b3 = r4, .L6
mov.dptk.many.tk.nt b3 = r4, .L6
mov.dptk.many.tk.nt.imp b3 = r4, .L6
mov.dptk.many.nt.dc b3 = r4, .L6
mov.dptk.many.nt.dc.imp b3 = r4, .L6
mov.dptk.many.nt.tk b3 = r4, .L6
mov.dptk.many.nt.tk.imp b3 = r4, .L6
mov.dptk.many.nt.nt b3 = r4, .L6
mov.dptk.many.nt.nt.imp b3 = r4, .L6
.L6:
mov.ret.few.dc.dc b3 = r4, .L7
mov.ret.few.dc.dc.imp b3 = r4, .L7
mov.ret.few.dc.nt b3 = r4, .L7
mov.ret.few.dc.nt.imp b3 = r4, .L7
mov.ret.few.tk.dc b3 = r4, .L7
mov.ret.few.tk.dc.imp b3 = r4, .L7
mov.ret.few.tk.tk b3 = r4, .L7
mov.ret.few.tk.tk.imp b3 = r4, .L7
mov.ret.few.tk.nt b3 = r4, .L7
mov.ret.few.tk.nt.imp b3 = r4, .L7
mov.ret.few.nt.dc b3 = r4, .L7
mov.ret.few.nt.dc.imp b3 = r4, .L7
mov.ret.few.nt.tk b3 = r4, .L7
mov.ret.few.nt.tk.imp b3 = r4, .L7
mov.ret.few.nt.nt b3 = r4, .L7
mov.ret.few.nt.nt.imp b3 = r4, .L7
.L7:
mov.ret.many.dc.dc b3 = r4, .L8
mov.ret.many.dc.dc.imp b3 = r4, .L8
mov.ret.many.dc.nt b3 = r4, .L8
mov.ret.many.dc.nt.imp b3 = r4, .L8
mov.ret.many.tk.dc b3 = r4, .L8
mov.ret.many.tk.dc.imp b3 = r4, .L8
mov.ret.many.tk.tk b3 = r4, .L8
mov.ret.many.tk.tk.imp b3 = r4, .L8
mov.ret.many.tk.nt b3 = r4, .L8
mov.ret.many.tk.nt.imp b3 = r4, .L8
mov.ret.many.nt.dc b3 = r4, .L8
mov.ret.many.nt.dc.imp b3 = r4, .L8
mov.ret.many.nt.tk b3 = r4, .L8
mov.ret.many.nt.tk.imp b3 = r4, .L8
mov.ret.many.nt.nt b3 = r4, .L8
mov.ret.many.nt.nt.imp b3 = r4, .L8
.L8:
mov.ret.sptk.few.dc.dc b3 = r4, .L9
mov.ret.sptk.few.dc.dc.imp b3 = r4, .L9
mov.ret.sptk.few.dc.nt b3 = r4, .L9
mov.ret.sptk.few.dc.nt.imp b3 = r4, .L9
mov.ret.sptk.few.tk.dc b3 = r4, .L9
mov.ret.sptk.few.tk.dc.imp b3 = r4, .L9
mov.ret.sptk.few.tk.tk b3 = r4, .L9
mov.ret.sptk.few.tk.tk.imp b3 = r4, .L9
mov.ret.sptk.few.tk.nt b3 = r4, .L9
mov.ret.sptk.few.tk.nt.imp b3 = r4, .L9
mov.ret.sptk.few.nt.dc b3 = r4, .L9
mov.ret.sptk.few.nt.dc.imp b3 = r4, .L9
mov.ret.sptk.few.nt.tk b3 = r4, .L9
mov.ret.sptk.few.nt.tk.imp b3 = r4, .L9
mov.ret.sptk.few.nt.nt b3 = r4, .L9
mov.ret.sptk.few.nt.nt.imp b3 = r4, .L9
.L9:
mov.ret.sptk.many.dc.dc b3 = r4, .L10
mov.ret.sptk.many.dc.dc.imp b3 = r4, .L10
mov.ret.sptk.many.dc.nt b3 = r4, .L10
mov.ret.sptk.many.dc.nt.imp b3 = r4, .L10
mov.ret.sptk.many.tk.dc b3 = r4, .L10
mov.ret.sptk.many.tk.dc.imp b3 = r4, .L10
mov.ret.sptk.many.tk.tk b3 = r4, .L10
mov.ret.sptk.many.tk.tk.imp b3 = r4, .L10
mov.ret.sptk.many.tk.nt b3 = r4, .L10
mov.ret.sptk.many.tk.nt.imp b3 = r4, .L10
mov.ret.sptk.many.nt.dc b3 = r4, .L10
mov.ret.sptk.many.nt.dc.imp b3 = r4, .L10
mov.ret.sptk.many.nt.tk b3 = r4, .L10
mov.ret.sptk.many.nt.tk.imp b3 = r4, .L10
mov.ret.sptk.many.nt.nt b3 = r4, .L10
mov.ret.sptk.many.nt.nt.imp b3 = r4, .L10
.L10:
mov.ret.dptk.few.dc.dc b3 = r4, .L11
mov.ret.dptk.few.dc.dc.imp b3 = r4, .L11
mov.ret.dptk.few.dc.nt b3 = r4, .L11
mov.ret.dptk.few.dc.nt.imp b3 = r4, .L11
mov.ret.dptk.few.tk.dc b3 = r4, .L11
mov.ret.dptk.few.tk.dc.imp b3 = r4, .L11
mov.ret.dptk.few.tk.tk b3 = r4, .L11
mov.ret.dptk.few.tk.tk.imp b3 = r4, .L11
mov.ret.dptk.few.tk.nt b3 = r4, .L11
mov.ret.dptk.few.tk.nt.imp b3 = r4, .L11
mov.ret.dptk.few.nt.dc b3 = r4, .L11
mov.ret.dptk.few.nt.dc.imp b3 = r4, .L11
mov.ret.dptk.few.nt.tk b3 = r4, .L11
mov.ret.dptk.few.nt.tk.imp b3 = r4, .L11
mov.ret.dptk.few.nt.nt b3 = r4, .L11
mov.ret.dptk.few.nt.nt.imp b3 = r4, .L11
.L11:
mov.ret.dptk.many.dc.dc b3 = r4, .L12
mov.ret.dptk.many.dc.dc.imp b3 = r4, .L12
mov.ret.dptk.many.dc.nt b3 = r4, .L12
mov.ret.dptk.many.dc.nt.imp b3 = r4, .L12
mov.ret.dptk.many.tk.dc b3 = r4, .L12
mov.ret.dptk.many.tk.dc.imp b3 = r4, .L12
mov.ret.dptk.many.tk.tk b3 = r4, .L12
mov.ret.dptk.many.tk.tk.imp b3 = r4, .L12
mov.ret.dptk.many.tk.nt b3 = r4, .L12
mov.ret.dptk.many.tk.nt.imp b3 = r4, .L12
mov.ret.dptk.many.nt.dc b3 = r4, .L12
mov.ret.dptk.many.nt.dc.imp b3 = r4, .L12
mov.ret.dptk.many.nt.tk b3 = r4, .L12
mov.ret.dptk.many.nt.tk.imp b3 = r4, .L12
mov.ret.dptk.many.nt.nt b3 = r4, .L12
mov.ret.dptk.many.nt.nt.imp b3 = r4, .L12
.L12:

1328
gas/testsuite/gas/ia64/opc-m.d Normal file
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218
gas/testsuite/gas/ia64/opc-m.pl Normal file
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@ -0,0 +1,218 @@
print ".text\n\t.type _start,@", "function\n_start:\n\n";
@ldhint = ( "", ".nt1", ".nta" );
@ldspec = ( "", ".s", ".a", ".sa", ".c.clr", ".c.nc" );
@sthint = ( "", ".nta" );
$i = 0;
# Integer Load
foreach $s ( "1", "2", "4", "8" ) {
foreach $e (@ldspec, ".bias", ".acq", ".c.clr.acq") {
foreach $l (@ldhint) {
print "\tld${s}${e}${l} r4 = [r5]\n";
print "\tld${s}${e}${l} r4 = [r5], r6\n";
print "\tld${s}${e}${l} r4 = [r5], ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
}
}
# Integer Fill
for $l (@ldhint) {
print "\tld8.fill${l} r4 = [r5]\n";
print "\tld8.fill${l} r4 = [r5], r6\n";
print "\tld8.fill${l} r4 = [r5], ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
# Integer Store
foreach $s ("1", "2", "4", "8", "1.rel", "2.rel", "4.rel", "8.rel", "8.spill") {
for $l (@sthint) {
print "\tst${s}${l} [r4] = r5\n";
print "\tst${s}${l} [r4] = r5, ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
}
# Floating Point Load
foreach $s ( "fs", "fd", "f8", "fe" ) {
foreach $e (@ldspec) {
foreach $l (@ldhint) {
print "\tld${s}${e}${l} f4 = [r5]\n";
print "\tld${s}${e}${l} f4 = [r5], r6\n";
print "\tld${s}${e}${l} f4 = [r5], ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
}
}
# Floating Point Fill
for $l (@ldhint) {
print "\tldf.fill${l} f4 = [r5]\n";
print "\tldf.fill${l} f4 = [r5], r6\n";
print "\tldf.fill${l} f4 = [r5], ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
# Floating Point Store
foreach $s ( "fs", "fd", "f8", "fe", "f.spill" ) {
for $l (@sthint) {
print "\tst${s}${l} [r4] = f5\n";
print "\tst${s}${l} [r4] = f5, ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
}
# Floating Point Load Pair
foreach $s ( "fps", "fpd", "fp8" ) {
foreach $e (@ldspec) {
foreach $l (@ldhint) {
print "\tld${s}${e}${l} f4, f5 = [r5]\n";
print "\tld${s}${e}${l} f4, f5 = [r5], ", ($s eq "fps" ? 8 : 16), "\n";
}
print "\n";
}
}
# Line Prefetch
@lfhint = ( "", ".nt1", ".nt2", ".nta" );
foreach $e ( "", ".excl" ) {
foreach $f ( "", ".fault" ) {
foreach $h (@lfhint) {
print "\tlfetch${f}${e}${h} [r4]\n";
print "\tlfetch${f}${e}${h} [r4], r5\n";
print "\tlfetch${f}${e}${h} [r4], ", $i - 256, "\n";
$i = ($i + 13) % 512;
}
print "\n";
}
}
# Compare and Exchange
foreach $s ( "1", "2", "4", "8" ) {
foreach $e ( ".acq", ".rel" ) {
foreach $h (@ldhint) {
print "\tcmpxchg${s}${e}${h} r4 = [r5], r6, ar.ccv\n";
}
print "\n";
}
}
# Exchange
foreach $s ( "1", "2", "4", "8" ) {
foreach $h (@ldhint) {
print "\txchg${s}${h} r4 = [r5], r6\n";
}
print "\n";
}
# Fetch and Add
$i = 0;
@inc3 = ( -16, -8, -4, -1, 1, 4, 8, 16 );
foreach $s ( "4.acq", "8.acq", "4.rel", "8.rel" ) {
foreach $h (@ldhint) {
print "\tfetchadd${s}${h} r4 = [r5], ", $inc3[$i], "\n";
$i = ($i + 1) % 8;
}
print "\n";
}
# Get/Set FR
foreach $e ( ".sig", ".exp", ".s", ".d" ) {
print "\tsetf${e} f4 = r5\n";
}
print "\n";
foreach $e ( ".sig", ".exp", ".s", ".d" ) {
print "\tgetf${e} r4 = f5\n";
}
print "\n";
# Speculation and Advanced Load Checkso
print <<END
chk.s.m r4, _start
chk.s f4, _start
chk.a.nc r4, _start
chk.a.clr r4, _start
chk.a.nc f4, _start
chk.a.clr f4, _start
invala
fwb
mf
mf.a
srlz.d
srlz.i
sync.i
nop.m 0
nop.i 0
{ .mii; alloc r4 = ar.pfs, 2, 10, 16, 16 }
{ .mii; flushrs }
{ .mii; loadrs }
invala.e r4
invala.e f4
fc r4
ptc.e r4
break.m 0
break.m 0x1ffff
nop.m 0
break.m 0x1ffff
probe.r r4 = r5, r6
probe.w r4 = r5, r6
probe.r r4 = r5, 0
probe.w r4 = r5, 1
probe.r.fault r3, 2
probe.w.fault r3, 3
probe.rw.fault r3, 0
itc.d r8
itc.i r9
sum 0x1234
rum 0x5aaaaa
ssm 0xffffff
rsm 0x400000
ptc.l r4, r5
ptc.g r4, r5
ptc.ga r4, r5
ptr.d r4, r5
ptr.i r4, r5
thash r4 = r5
ttag r4 = r5
tpa r4 = r5
tak r4 = r5
END
;

1009
gas/testsuite/gas/ia64/opc-m.s Normal file
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29
gas/testsuite/gas/ia64/opc-x.d Normal file
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@ -0,0 +1,29 @@
#objdump: -d
#name: ia64 opc-x
.*: +file format .*
Disassembly of section .text:
0000000000000000 <_start>:
0: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0
...
e: 00 00 04 00 break\.x 0x0
12: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0
18: ff ff 7f e0 ff ff break\.x 0x3fffffffffffffff
1e: 01 08 04 00
22: 00 00 01 00 00 00 \[MLX\] nop\.m 0x0
28: 00 00 00 00 00 00 nop\.x 0x0
2e: 04 00 04 00
32: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0
38: ff ff 7f e0 ff ff nop\.x 0x3fffffffffffffff
3e: 05 08 04 00
42: 00 00 01 00 00 00 \[MLX\] nop\.m 0x0
48: 00 00 00 80 00 00 movl r4=0x0
4e: 00 60 04 00
52: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0
58: ff ff 7f 80 f0 f7 movl r4=0xffffffffffffffff
5e: ff 6f 05 00
62: 00 00 01 80 90 78 \[MLX\] nop\.m 0x0
68: 56 34 12 80 f0 76 movl r4=0x1234567890abcdef;;
6e: 6d 66 00 00

14
gas/testsuite/gas/ia64/opc-x.s Normal file
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@ -0,0 +1,14 @@
.text
.type _start,@function
_start:
break.x 0
break.x 0x3fffffffffffffff
nop.x 0
nop.x 0x3fffffffffffffff
movl r4 = 0
movl r4 = 0xffffffffffffffff
movl r4 = 0x1234567890abcdef

2333
gas/testsuite/gas/ia64/regs.d Normal file
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150
gas/testsuite/gas/ia64/regs.pl Normal file
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@ -0,0 +1,150 @@
print ".text\n";
print "\t.type _start,@","function\n";
print "_start:\n\n";
print "// Fixed and stacked integer registers.\n";
for ($i = 1; $i < 128; ++$i) {
print "\t{ .mii; mov r$i = r0; nop.i 0; nop.i 0;; }\n";
}
print "\n";
print "// Alternate names for input registers\n";
print "\t.regstk 96, 0, 0, 0\n";
for ($i = 0; $i < 96; ++$i) {
print "\t{ .mii; mov in$i = r0; nop.i 0; nop.i 0;; }\n";
}
print "\n";
print "// Alternate names for output registers\n";
print "\t.regstk 0, 0, 96, 0\n";
for ($i = 0; $i < 96; ++$i) {
print "\t{ .mii; mov out$i = r0; nop.i 0; nop.i 0;; }\n";
}
print "\n";
print "// Alternate names for local registers\n";
print "\t.regstk 0, 96, 0, 0\n";
for ($i = 0; $i < 96; ++$i) {
print "\t{ .mii; mov loc$i = r0; nop.i 0; nop.i 0;; }\n";
}
print "\n";
print "// Return value registers\n";
for ($i = 0; $i < 4; ++$i) {
print "\t{ .mii; mov ret$i = r0; nop.i 0; nop.i 0;; }\n";
}
print "\n";
print "\t{ .mii;\n";
print "\tmov gp = r0\n";
print "\tmov sp = r0\n";
print "\tnop.i 0;; }\n\n";
print "// Floating point registers\n";
for ($i = 2; $i < 128; ++$i) {
print "\t{ .mfi; mov f$i = f0 ;; }\n";
}
print "\n";
print "// Floating point argument registers\n";
for ($i = 0; $i < 8; ++$i) {
print "\t{ .mfi; mov farg$i = f1 ;; }\n";
}
print "\n";
print "// Floating point return value registers\n";
for ($i = 0; $i < 8; ++$i) {
print "\t{ .mfi; mov fret$i = f1 ;; }\n";
}
print "\n";
print "// Predicate registers\n";
for ($i = 0; $i < 64; ++$i) {
print "\t{ .mii; (p$i)\tmov r", $i+1, " = r0; nop.i 0; nop.i 0;; }\n";
}
print "\n";
print "// Predicates as a unit\n";
print "\t{ .mmi; nop.m 0; mov r1 = pr ;; }\n";
print "//\tmov r2 = pr.rot\n";
print "\n";
print "// Branch registers.\n";
for ($i = 0; $i < 8; ++$i) {
print "\t{ .mmi; mov b$i = r0;; }\n";
}
print "\n";
print "\t{ .mmi; mov rp = r0;; }\n";
print "\n";
print "// Application registers\n";
@reserved = ( 8..15, 20, 22..23, 31, 33..35, 37..39, 41..47, 67..111 );
%reserved = ();
foreach $i (@reserved) {
$reserved{$i} = 1;
}
for ($i = 0; $i < 128; ++$i) {
print "//" if $reserved{$i};
print "\t{ .mmi; nop.m 0; mov r1 = ar$i ;; }";
print "\t\t// reserved" if $reserved{$i};
print "\n";
}
print "\n";
print "// Application registers by name\n";
for ($i = 0; $i < 8; ++$i) {
print "\t{ .mmi; nop.m 0; mov r1 = ar.k$i ;;}\n";
}
@regs = ( "rsc", "bsp", "bspstore", "rnat", "ccv", "unat", "fpsr", "itc",
"pfs", "lc", "ec" );
foreach $i (@regs) {
print "\t{ .mmi; nop.m 0; mov r1 = ar.$i ;; }\n";
}
print "\n";
print "// Control registers\n";
@reserved = ( 3..7, 10..15, 18, 26..63, 75..79, 82..127 );
%reserved = ();
foreach $i (@reserved) {
$reserved{$i} = 1;
}
for ($i = 0; $i < 128; ++$i) {
print "//" if $reserved{$i};
print "\t{ .mfb; mov r1 = cr$i ;; }";
print "\t\t// reserved" if $reserved{$i};
print "\n";
}
print "\n";
print "// Control registers by name\n";
@regs = ( "dcr", "itm", "iva", "pta", "ipsr", "isr", "iip",
"iipa", "ifs", "iim", "iha", "lid", "ivr",
"tpr", "eoi", "irr0", "irr1", "irr2", "irr3", "itv", "pmv",
"lrr0", "lrr1", "cmcv" );
# ias doesn't accept these, despite documentation to the contrary.
# push @regs, "ida", "idtr", "iitr"
foreach $i (@regs) {
print "\t{ .mfb; mov r1 = cr.$i ;; }\n";
}
print "\n";
print "// Other registers\n";
print "\t{ .mfb; mov r1 = psr ;; }\n";
print "//\t{ .mfb; mov r1 = psr.l ;; }\n";
print "\t{ .mfb; mov r1 = psr.um ;; }\n";
print "\t{ .mmi; mov r1 = ip ;; }\n";
print "\n";
print "// Indirect register files\n";
@regs = ("pmc", "pmd", "pkr", "rr", "ibr", "dbr", "CPUID", "cpuid");
# ias doesn't accept these, despite documentation to the contrary.
# push @regs, "itr", "dtr";
foreach $i (@regs) {
print "\t{ .mmi\n";
print "\tmov r1 = ${i}[r3]\n";
print "\tmov r2 = ${i}[r4]\n";
print "\tnop.i 0;; }\n";
}

1017
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4
gas/testsuite/gas/vtable/vtable.exp
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@ -20,6 +20,10 @@ if { ([istarget "*-*-elf*"]
&& ![istarget *-*-linux*aout*]
&& ![istarget *-*-linux*oldld*] } then {
if {[istarget "ia64-*"]} then {
return
}
# not supported by D30V
if {[istarget "d30v-*-*"]} {
return

5
include/ChangeLog
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@ -1,3 +1,8 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
* dis-asm.h (print_insn_ia64): Declare.
2000-04-05 Richard Henderson <rth@cygnus.com>
* splay-tree.h (splay_tree_remove): Declare.

1
include/dis-asm.h
View File

@ -157,6 +157,7 @@ extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_ia64 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));

5
include/elf/ChangeLog
View File

@ -1,3 +1,8 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
* ia64.h: New file.
2000-04-14 H.J. Lu <hjl@gnu.org>
* common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64.

167
include/elf/ia64.h Normal file
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@ -0,0 +1,167 @@
/* IA-64 ELF support for BFD.
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _ELF_IA64_H
#define _ELF_IA64_H
/* Bits in the e_flags field of the Elf64_Ehdr: */
#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */
#define EF_IA_64_ABI64 (1 << 4) /* 64-bit ABI */
#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */
/* ??? These four definitions are not part of the SVR4 ABI.
They were present in David's initial code drop, so it is probable
that they are used by HP/UX. */
#define EF_IA_64_TRAPNIL (1 << 0) /* trap NIL pointer dereferences */
#define EF_IA_64_EXT (1 << 2) /* program uses arch. extensions */
#define EF_IA_64_BE (1 << 3) /* PSR BE bit set (big-endian) */
#define EFA_IA_64_EAS2_3 0x23000000 /* ia64 EAS 2.3 */
#define ELF_STRING_ia64_archext ".IA_64.archext"
#define ELF_STRING_ia64_pltoff ".IA_64.pltoff"
#define ELF_STRING_ia64_unwind ".IA_64.unwind"
#define ELF_STRING_ia64_unwind_info ".IA_64.unwind_info"
/* Bits in the sh_flags field of Elf64_Shdr: */
#define SHF_IA_64_SHORT 0x10000000 /* section near gp */
#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */
/* Possible values for sh_type in Elf64_Shdr: */
#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */
#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */
/* Bits in the p_flags field of Elf64_Phdr: */
#define PF_IA_64_NORECOV 0x80000000
/* Possible values for p_type in Elf64_Phdr: */
#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */
#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */
/* Possible values for d_tag in Elf64_Dyn: */
#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0)
/* ia64-specific relocation types: */
/* Relocs apply to specific instructions within a bundle. The least
significant 2 bits of the address indicate which instruction in the
bundle the reloc refers to (0=first slot, 1=second slow, 2=third
slot, 3=undefined) and the remaining bits give the address of the
bundle (16 byte aligned).
The top 5 bits of the reloc code specifies the expression type, the
low 3 bits the format of the data word being relocated.
??? Relocations below marked ## are not part of the SVR4 processor
suppliment. They were present in David's initial code drop, so it
is possible that they are used by HP/UX. */
#include "elf/reloc-macros.h"
START_RELOC_NUMBERS (elf_ia64_reloc_type)
RELOC_NUMBER (R_IA64_NONE, 0x00) /* none */
RELOC_NUMBER (R_IA64_IMM14, 0x21) /* symbol + addend, add imm14 */
RELOC_NUMBER (R_IA64_IMM22, 0x22) /* symbol + addend, add imm22 */
RELOC_NUMBER (R_IA64_IMM64, 0x23) /* symbol + addend, mov imm64 */
RELOC_NUMBER (R_IA64_DIR32MSB, 0x24) /* symbol + addend, data4 MSB */
RELOC_NUMBER (R_IA64_DIR32LSB, 0x25) /* symbol + addend, data4 LSB */
RELOC_NUMBER (R_IA64_DIR64MSB, 0x26) /* symbol + addend, data8 MSB */
RELOC_NUMBER (R_IA64_DIR64LSB, 0x27) /* symbol + addend, data8 LSB */
RELOC_NUMBER (R_IA64_GPREL22, 0x2a) /* @gprel(sym + add), add imm22 */
RELOC_NUMBER (R_IA64_GPREL64I, 0x2b) /* @gprel(sym + add), mov imm64 */
RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym + add), data4 MSB ## */
RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym + add), data4 LSB ## */
RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym + add), data8 MSB */
RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym + add), data8 LSB */
RELOC_NUMBER (R_IA64_LTOFF22, 0x32) /* @ltoff(sym + add), add imm22 */
RELOC_NUMBER (R_IA64_LTOFF64I, 0x33) /* @ltoff(sym + add), mov imm64 */
RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a) /* @pltoff(sym + add), add imm22 */
RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b) /* @pltoff(sym + add), mov imm64 */
RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym + add), data8 MSB */
RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym + add), data8 LSB */
RELOC_NUMBER (R_IA64_FPTR64I, 0x43) /* @fptr(sym + add), mov imm64 */
RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44) /* @fptr(sym + add), data4 MSB */
RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45) /* @fptr(sym + add), data4 LSB */
RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46) /* @fptr(sym + add), data8 MSB */
RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47) /* @fptr(sym + add), data8 LSB */
RELOC_NUMBER (R_IA64_PCREL21B, 0x49) /* @pcrel(sym + add), ptb, call */
RELOC_NUMBER (R_IA64_PCREL21M, 0x4a) /* @pcrel(sym + add), chk.s */
RELOC_NUMBER (R_IA64_PCREL21F, 0x4b) /* @pcrel(sym + add), fchkf */
RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym + add), data4 MSB */
RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym + add), data4 LSB */
RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym + add), data8 MSB */
RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym + add), data8 LSB */
RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */
RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */
RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB ##*/
RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB ##*/
RELOC_NUMBER (R_IA64_SEGBASE, 0x58) /* set segment base for @segrel ## */
RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym + add), data4 MSB */
RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym + add), data4 LSB */
RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym + add), data8 MSB */
RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym + add), data8 LSB */
RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym + add), data4 MSB */
RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym + add), data4 LSB */
RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym + add), data8 MSB */
RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym + add), data8 LSB */
RELOC_NUMBER (R_IA64_REL32MSB, 0x6c) /* data 4 + REL */
RELOC_NUMBER (R_IA64_REL32LSB, 0x6d) /* data 4 + REL */
RELOC_NUMBER (R_IA64_REL64MSB, 0x6e) /* data 8 + REL */
RELOC_NUMBER (R_IA64_REL64LSB, 0x6f) /* data 8 + REL */
RELOC_NUMBER (R_IA64_LTV32MSB, 0x70) /* symbol + addend, data4 MSB */
RELOC_NUMBER (R_IA64_LTV32LSB, 0x71) /* symbol + addend, data4 LSB */
RELOC_NUMBER (R_IA64_LTV64MSB, 0x72) /* symbol + addend, data8 MSB */
RELOC_NUMBER (R_IA64_LTV64LSB, 0x73) /* symbol + addend, data8 LSB */
RELOC_NUMBER (R_IA64_IPLTMSB, 0x80) /* dynamic reloc, imported PLT, MSB */
RELOC_NUMBER (R_IA64_IPLTLSB, 0x81) /* dynamic reloc, imported PLT, LSB */
RELOC_NUMBER (R_IA64_EPLTMSB, 0x82) /* dynamic reloc, exported PLT, ## */
RELOC_NUMBER (R_IA64_EPLTLSB, 0x83) /* dynamic reloc, exported PLT, ## */
RELOC_NUMBER (R_IA64_COPY, 0x84) /* dynamic reloc, data copy ## */
RELOC_NUMBER (R_IA64_LTOFF22X, 0x86) /* LTOFF22, relaxable. */
RELOC_NUMBER (R_IA64_LDXMOV, 0x87) /* Use of LTOFF22X. */
RELOC_NUMBER (R_IA64_TPREL22, 0x92) /* sym-TP+add, add imm22 ## */
RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* sym-TP+add, data8 MSB ## */
RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* sym-TP+add, data8 LSB ## */
RELOC_NUMBER (R_IA64_LTOFF_TP22, 0x9a) /* @ltoff(sym-TP+add), add imm22 ## */
FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0x9a)
END_RELOC_NUMBERS
#endif /* _ELF_IA64_H */

7
include/opcode/ChangeLog
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@ -1,3 +1,10 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@cygnus.com>
Jim Wilson <wilson@cygnus.com>
* ia64.h: New file.
2000-03-27 Nick Clifton <nickc@cygnus.com>
* d30v.h (SHORT_A1): Fix value.

388
include/opcode/ia64.h Normal file
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@ -0,0 +1,388 @@
/* ia64.h -- Header file for ia64 opcode table
Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
See the file HP-COPYRIGHT for additional information. */
#ifndef opcode_ia64_h
#define opcode_ia64_h
#include <sys/types.h>
#include <bfd.h>
typedef BFD_HOST_U_64_BIT ia64_insn;
enum ia64_insn_type
{
IA64_TYPE_NIL = 0, /* illegal type */
IA64_TYPE_A, /* integer alu (I- or M-unit) */
IA64_TYPE_I, /* non-alu integer (I-unit) */
IA64_TYPE_M, /* memory (M-unit) */
IA64_TYPE_B, /* branch (B-unit) */
IA64_TYPE_F, /* floating-point (F-unit) */
IA64_TYPE_X, /* long encoding (X-unit) */
IA64_TYPE_DYN, /* Dynamic opcode */
IA64_NUM_TYPES
};
enum ia64_unit
{
IA64_UNIT_NIL = 0, /* illegal unit */
IA64_UNIT_I, /* integer unit */
IA64_UNIT_M, /* memory unit */
IA64_UNIT_B, /* branching unit */
IA64_UNIT_F, /* floating-point unit */
IA64_UNIT_L, /* long "unit" */
IA64_UNIT_X, /* may be integer or branch unit */
IA64_NUM_UNITS
};
/* Changes to this enumeration must be propagated to the operand table in
bfd/cpu-ia64-opc.c
*/
enum ia64_opnd
{
IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
/* constants */
IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
IA64_OPND_C1, /* the constant 1 */
IA64_OPND_C8, /* the constant 8 */
IA64_OPND_C16, /* the constant 16 */
IA64_OPND_GR0, /* gr0 */
IA64_OPND_IP, /* instruction pointer (ip) */
IA64_OPND_PR, /* predicate register (pr) */
IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
IA64_OPND_PSR, /* processor status register (psr) */
IA64_OPND_PSR_L, /* processor status register L (psr.l) */
IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
/* register operands: */
IA64_OPND_AR3, /* third application register # (bits 20-26) */
IA64_OPND_B1, /* branch register # (bits 6-8) */
IA64_OPND_B2, /* branch register # (bits 13-15) */
IA64_OPND_CR3, /* third control register # (bits 20-26) */
IA64_OPND_F1, /* first floating-point register # */
IA64_OPND_F2, /* second floating-point register # */
IA64_OPND_F3, /* third floating-point register # */
IA64_OPND_F4, /* fourth floating-point register # */
IA64_OPND_P1, /* first predicate # */
IA64_OPND_P2, /* second predicate # */
IA64_OPND_R1, /* first register # */
IA64_OPND_R2, /* second register # */
IA64_OPND_R3, /* third register # */
IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
/* indirect operands: */
IA64_OPND_CPUID_R3, /* cpuid[reg] */
IA64_OPND_DBR_R3, /* dbr[reg] */
IA64_OPND_DTR_R3, /* dtr[reg] */
IA64_OPND_ITR_R3, /* itr[reg] */
IA64_OPND_IBR_R3, /* ibr[reg] */
IA64_OPND_MR3, /* memory at addr of third register # */
IA64_OPND_MSR_R3, /* msr[reg] */
IA64_OPND_PKR_R3, /* pkr[reg] */
IA64_OPND_PMC_R3, /* pmc[reg] */
IA64_OPND_PMD_R3, /* pmd[reg] */
IA64_OPND_RR_R3, /* rr[reg] */
/* immediate operands: */
IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
IA64_OPND_SOF, /* 8-bit stack frame size */
IA64_OPND_SOL, /* 8-bit size of locals */
IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
};
enum ia64_dependency_mode
{
IA64_DV_RAW,
IA64_DV_WAW,
IA64_DV_WAR,
};
enum ia64_dependency_semantics
{
IA64_DVS_NONE,
IA64_DVS_IMPLIED,
IA64_DVS_IMPLIEDF,
IA64_DVS_DATA,
IA64_DVS_INSTR,
IA64_DVS_SPECIFIC,
IA64_DVS_OTHER,
};
enum ia64_resource_specifier
{
IA64_RS_ANY,
IA64_RS_AR_K,
IA64_RS_AR_UNAT,
IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
IA64_RS_ARb, /* 48-63, 112-127 */
IA64_RS_BR,
IA64_RS_CFM,
IA64_RS_CPUID,
IA64_RS_CR_IRR,
IA64_RS_CR_LRR,
IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
IA64_RS_DBR,
IA64_RS_FR,
IA64_RS_FRb,
IA64_RS_GR0,
IA64_RS_GR,
IA64_RS_IBR,
IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
IA64_RS_MSR,
IA64_RS_PKR,
IA64_RS_PMC,
IA64_RS_PMD,
IA64_RS_PR,
IA64_RS_PR63,
IA64_RS_RR,
IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
IA64_RS_CRX, /* CRs not in RS_CR */
IA64_RS_PSR, /* PSR bits */
IA64_RS_RSE, /* implementation-specific RSE resources */
IA64_RS_AR_FPSR,
};
enum ia64_rse_resource
{
IA64_RSE_N_STACKED_PHYS,
IA64_RSE_BOF,
IA64_RSE_STORE_REG,
IA64_RSE_LOAD_REG,
IA64_RSE_BSPLOAD,
IA64_RSE_RNATBITINDEX,
IA64_RSE_CFLE,
IA64_RSE_NDIRTY,
};
/* Information about a given resource dependency */
struct ia64_dependency
{
/* Name of the resource */
const char *name;
/* Does this dependency need further specification? */
enum ia64_resource_specifier specifier;
/* Mode of dependency */
enum ia64_dependency_mode mode;
/* Dependency semantics */
enum ia64_dependency_semantics semantics;
/* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
#define REG_NONE (-1)
int regindex;
/* Special info on semantics */
const char *info;
};
/* Two arrays of indexes into the ia64_dependency table.
chks are dependencies to check for conflicts when an opcode is
encountered; regs are dependencies to register (mark as used) when an
opcode is used. chks correspond to readers (RAW) or writers (WAW or
WAR) of a resource, while regs correspond to writers (RAW or WAW) and
readers (WAR) of a resource. */
struct ia64_opcode_dependency
{
int nchks;
const unsigned short *chks;
int nregs;
const unsigned short *regs;
};
/* encode/extract the note/index for a dependency */
#define RDEP(N,X) (((N)<<11)|(X))
#define NOTE(X) (((X)>>11)&0x1F)
#define DEP(X) ((X)&0x7FF)
/* A template descriptor describes the execution units that are active
for each of the three slots. It also specifies the location of
instruction group boundaries that may be present between two slots. */
struct ia64_templ_desc
{
int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
enum ia64_unit exec_unit[3];
const char *name;
};
/* The opcode table is an array of struct ia64_opcode. */
struct ia64_opcode
{
/* The opcode name. */
const char *name;
/* The type of the instruction: */
enum ia64_insn_type type;
/* Number of output operands: */
int num_outputs;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
ia64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
ia64_insn mask;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum ia64_opnd operands[5];
/* One bit flags for the opcode. These are primarily used to
indicate specific processors and environments support the
instructions. The defined values are listed below. */
unsigned int flags;
/* Used by ia64_find_next_opcode (). */
short ent_index;
/* Opcode dependencies. */
const struct ia64_opcode_dependency *dependencies;
};
/* Values defined for the flags field of a struct ia64_opcode. */
#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
/* A macro to extract the major opcode from an instruction. */
#define IA64_OP(i) (((i) >> 37) & 0xf)
enum ia64_operand_class
{
IA64_OPND_CLASS_CST, /* constant */
IA64_OPND_CLASS_REG, /* register */
IA64_OPND_CLASS_IND, /* indirect register */
IA64_OPND_CLASS_ABS, /* absolute value */
IA64_OPND_CLASS_REL, /* IP-relative value */
};
/* The operands table is an array of struct ia64_operand. */
struct ia64_operand
{
enum ia64_operand_class class;
/* Set VALUE as the operand bits for the operand of type SELF in the
instruction pointed to by CODE. If an error occurs, *CODE is not
modified and the returned string describes the cause of the
error. If no error occurs, NULL is returned. */
const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code);
/* Extract the operand bits for an operand of type SELF from
instruction CODE store them in *VALUE. If an error occurs, the
cause of the error is described by the string returned. If no
error occurs, NULL is returned. */
const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
ia64_insn *value);
/* A string whose meaning depends on the operand class. */
const char *str;
struct bit_field
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
}
field[4]; /* no operand has more than this many bit-fields */
unsigned int flags;
const char *desc; /* brief description */
};
/* Values defined for the flags field of a struct ia64_operand. */
/* Disassemble as signed decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
/* Disassemble as unsigned decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
extern const struct ia64_templ_desc ia64_templ_desc[16];
/* The tables are sorted by major opcode number and are otherwise in
the order in which the disassembler should consider instructions. */
extern struct ia64_opcode ia64_opcodes_a[];
extern struct ia64_opcode ia64_opcodes_i[];
extern struct ia64_opcode ia64_opcodes_m[];
extern struct ia64_opcode ia64_opcodes_b[];
extern struct ia64_opcode ia64_opcodes_f[];
extern struct ia64_opcode ia64_opcodes_d[];
extern struct ia64_opcode *ia64_find_opcode (const char *name);
extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
enum ia64_insn_type type);
extern void ia64_free_opcode (struct ia64_opcode *ent);
extern const struct ia64_dependency *ia64_find_dependency (int index);
/* To avoid circular library dependencies, this array is implemented
in bfd/cpu-ia64-opc.c: */
extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
#endif /* opcode_ia64_h */

9
ld/ChangeLog
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@ -1,3 +1,12 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
* Makefile.am (ALL_64_EMULATIONS): Add eelf64_ia64.o.
(eelf64_ia64.c): New rule.
* Makefile.in: Rebuild.
* configure.tgt (ia64-*-elf*, ia64-*-linux*): New targets.
* emulparams/elf64_ia64.sh: New file.
2000-04-21 Richard Henderson <rth@cygnus.com>
* scripttempl/elfd30v.sc: Place .gcc_except_table.

4
ld/Makefile.am
View File

@ -226,6 +226,7 @@ ALL_EMULATIONS = \
ez8002.o
ALL_64_EMULATIONS = \
eelf64_ia64.o \
eelf64_sparc.o \
eelf64alpha.o \
eelf64bmip.o
@ -449,6 +450,9 @@ eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
eelf64alpha.c: $(srcdir)/emulparams/elf64alpha.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64alpha "$(tdir_elf64alpha)"
eelf64_ia64.c: $(srcdir)/emulparams/elf64_ia64.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64_ia64 "$(tdir_elf64_ia64)"
eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64_sparc "$(tdir_elf64_sparc)"

5
ld/Makefile.in
View File

@ -175,7 +175,7 @@ LIBIBERTY = ../libiberty/libiberty.a
ALL_EMULATIONS = ea29k.o eaixppc.o eaixrs6.o ealpha.o earcelf.o earmelf.o earmelf_oabi.o earmelf_linux.o earmelf_linux26.o earmaoutb.o earmaoutl.o earmcoff.o earmnbsd.o earmpe.o earm_epoc_pe.o eavr1200.o eavr23xx.o eavr44x4.o eavr4433.o eavr85xx.o eavrmega603.o eavrmega103.o eavrmega161.o ecoff_sparc.o ed10velf.o ed30velf.o ed30v_e.o ed30v_o.o edelta68.o eebmon29k.o eelf32_sparc.o eelf32_i960.o eelf32b4300.o eelf32bmip.o eelf32ebmip.o eelf32elmip.o eelf32bmipn32.o eelf32i370.o eelf32l4300.o eelf32lmip.o eelf32lppc.o eelf32lppcsim.o eelf32ppc.o eelf32ppcsim.o eelf32ppclinux.o eelf_i386.o eelf_i386_be.o egld960.o egld960coff.o eelf32fr30.o eelf32mcore.o eh8300.o eh8300h.o eh8300s.o eh8500.o eh8500b.o eh8500c.o eh8500m.o eh8500s.o ehp300bsd.o ehp3hpux.o ei386aout.o ei386beos.o ei386bsd.o ei386coff.o ei386go32.o ei386linux.o ei386lynx.o ei386mach.o ei386moss.o ei386msdos.o ei386nbsd.o ei386nw.o ei386pe.o ei386pe_posix.o elnk960.o em68k4knbsd.o em68kaout.o em68kaux.o em68kcoff.o em68kelf.o em68klinux.o em68klynx.o em68knbsd.o em68kpsos.o em88kbcs.o emcorepe.o emipsbig.o emipsbsd.o emipsidt.o emipsidtl.o emipslit.o emipslnews.o emipspe.o enews.o epjelf.o epjlelf.o ens32knbsd.o epc532macha.o eppcmacos.o eppcnw.o eppcpe.o eriscix.o esa29200.o esh.o eshelf.o eshlelf.o eshl.o eshpe.o esparcaout.o esparclinux.o esparclynx.o esparcnbsd.o est2000.o esun3.o esun4.o etic30aout.o etic30coff.o etic80coff.o evanilla.o evax.o evsta.o ew65.o ez8001.o ez8002.o
ALL_64_EMULATIONS = eelf64_sparc.o eelf64alpha.o eelf64bmip.o
ALL_64_EMULATIONS = eelf64_ia64.o eelf64_sparc.o eelf64alpha.o eelf64bmip.o
ALL_EMUL_EXTRA_OFILES = pe-dll.o deffilep.o
@ -981,6 +981,9 @@ eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
eelf64alpha.c: $(srcdir)/emulparams/elf64alpha.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64alpha "$(tdir_elf64alpha)"
eelf64_ia64.c: $(srcdir)/emulparams/elf64_ia64.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64_ia64 "$(tdir_elf64_ia64)"
eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64_sparc "$(tdir_elf64_sparc)"

2
ld/configure.tgt
View File

@ -79,6 +79,8 @@ i960-*-coff) targ_emul=gld960coff ;;
i960-intel-nindy) targ_emul=gld960 ;;
i960-*-rtems*) targ_emul=gld960coff ;;
i960-*-elf*) targ_emul=elf32_i960 ;;
ia64-*-elf*) targ_emul=elf64_ia64 ;;
ia64-*-linux*) targ_emul=elf64_ia64 ;;
m32r-*-*) targ_emul=m32relf ;;
m68*-sun-sunos[34]*) targ_emul=sun3 ;;
m68*-wrs-vxworks*) targ_emul=sun3 ;;

16
ld/emulparams/elf64_ia64.sh Normal file
View File

@ -0,0 +1,16 @@
# See genscripts.sh and ../scripttempl/elf.sc for the meaning of these.
SCRIPT_NAME=elf
ELFSIZE=64
TEMPLATE_NAME=elf32
OUTPUT_FORMAT="elf64-ia64-little"
ARCH=ia64
MACHINE=
MAXPAGESIZE=0x10000
TEXT_START_ADDR="0x4000000000000000"
DATA_ADDR="0x6000000000000000 + (. & (${MAXPAGESIZE} - 1))"
GENERATE_SHLIB_SCRIPT=yes
NOP=0x00300000010070000002000001000400 # a bundle full of nops
OTHER_GOT_SYMBOLS='. = ALIGN (8); PROVIDE (__gp = . + 0x200000);'
OTHER_GOT_SECTIONS='.IA_64.pltoff : { *(.IA_64.pltoff) }'
OTHER_PLT_RELOC_SECTIONS='.rela.IA_64.pltoff : { *(.rela.IA_64.pltoff) }'
OTHER_READONLY_SECTIONS='.opd : { *(.opd) }'

23
opcodes/ChangeLog
View File

@ -1,3 +1,26 @@
Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com>
David Mosberger <davidm@hpl.hp.com>
Timothy Wall <twall@cygnus.com>
Bob Manson <manson@charmed.cygnus.com>
Jim Wilson <wilson@cygnus.com>
* Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h.
(CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c,
ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c,
ia64-asmtab.c.
(ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo.
(ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen,
ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules.
* Makefile.in: Rebuild.
* configure Rebuild.
* configure.in (bfd_ia64_arch): New target.
* disassemble.c (ARCH_ia64): Define.
(disassembler): Support ARCH_ia64.
* ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl,
ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c,
ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl,
ia64-war.tbl, ia64-waw.tbl): New files.
2000-04-20 Alexandre Oliva <aoliva@cygnus.com>
* m10300-dis.c (HAVE_AM30, HAVE_AM33): Define.

34
opcodes/Makefile.am
View File

@ -25,6 +25,8 @@ HFILES = \
mcore-opc.h \
sh-opc.h \
sysdep.h \
ia64-asmtab.h \
ia64-opc.h \
w65-opc.h \
z8k-opc.h
@ -58,6 +60,16 @@ CFILES = \
i370-opc.c \
i386-dis.c \
i960-dis.c \
ia64-dis.c \
ia64-opc-a.c \
ia64-opc-b.c \
ia64-opc-f.c \
ia64-opc-i.c \
ia64-opc-m.c \
ia64-opc-d.c \
ia64-opc.c \
ia64-gen.c \
ia64-asmtab.c \
m32r-asm.c \
m32r-desc.c \
m32r-dis.c \
@ -120,6 +132,8 @@ ALL_MACHINES = \
i370-dis.lo \
i370-opc.lo \
i960-dis.lo \
ia64-dis.lo \
ia64-opc.lo \
m32r-asm.lo \
m32r-desc.lo \
m32r-dis.lo \
@ -202,6 +216,23 @@ CLEANFILES = \
ia64-ic.tbl: $(srcdir)/ia64-ic.tbl
$(LN_S) -f $(srcdir)/ia64-ic.tbl
ia64-raw.tbl: $(srcdir)/ia64-raw.tbl
$(LN_S) -f $(srcdir)/ia64-raw.tbl
ia64-waw.tbl: $(srcdir)/ia64-waw.tbl
$(LN_S) -f $(srcdir)/ia64-waw.tbl
ia64-war.tbl: $(srcdir)/ia64-war.tbl
$(LN_S) -f $(srcdir)/ia64-war.tbl
ia64-gen: ia64-gen.o
$(LINK) ia64-gen.o $(LIBIBERTY)
ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
./ia64-gen > $(srcdir)/ia64-asmtab.c
# This dependency stuff is copied from BFD.
@ -315,6 +346,9 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H)
ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H)
ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \
$(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c
m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
m32r-opc.h opintl.h

34
opcodes/Makefile.in
View File

@ -128,6 +128,8 @@ HFILES = \
mcore-opc.h \
sh-opc.h \
sysdep.h \
ia64-asmtab.h \
ia64-opc.h \
w65-opc.h \
z8k-opc.h
@ -162,6 +164,16 @@ CFILES = \
i370-opc.c \
i386-dis.c \
i960-dis.c \
ia64-dis.c \
ia64-opc-a.c \
ia64-opc-b.c \
ia64-opc-f.c \
ia64-opc-i.c \
ia64-opc-m.c \
ia64-opc-d.c \
ia64-opc.c \
ia64-gen.c \
ia64-asmtab.c \
m32r-asm.c \
m32r-desc.c \
m32r-dis.c \
@ -225,6 +237,8 @@ ALL_MACHINES = \
i370-dis.lo \
i370-opc.lo \
i960-dis.lo \
ia64-dis.lo \
ia64-opc.lo \
m32r-asm.lo \
m32r-desc.lo \
m32r-dis.lo \
@ -676,6 +690,23 @@ all-redirect all-am all installdirs-am installdirs mostlyclean-generic \
distclean-generic clean-generic maintainer-clean-generic clean \
mostlyclean distclean maintainer-clean
ia64-ic.tbl: $(srcdir)/ia64-ic.tbl
$(LN_S) -f $(srcdir)/ia64-ic.tbl
ia64-raw.tbl: $(srcdir)/ia64-raw.tbl
$(LN_S) -f $(srcdir)/ia64-raw.tbl
ia64-waw.tbl: $(srcdir)/ia64-waw.tbl
$(LN_S) -f $(srcdir)/ia64-waw.tbl
ia64-war.tbl: $(srcdir)/ia64-war.tbl
$(LN_S) -f $(srcdir)/ia64-war.tbl
ia64-gen: ia64-gen.o
$(LINK) ia64-gen.o $(LIBIBERTY)
ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \
ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h
ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl
./ia64-gen > $(srcdir)/ia64-asmtab.c
disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h
$(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c
@ -812,6 +843,9 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h sysdep.h config.h opintl.h
i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H)
ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H)
ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \
$(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c
m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \
m32r-opc.h opintl.h

1
opcodes/configure vendored
View File

@ -3955,6 +3955,7 @@ if test x${all_targets} = xfalse ; then
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
bfd_i860_arch) ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;

1
opcodes/configure.in
View File

@ -166,6 +166,7 @@ if test x${all_targets} = xfalse ; then
bfd_i386_arch) ta="$ta i386-dis.lo" ;;
bfd_i860_arch) ;;
bfd_i960_arch) ta="$ta i960-dis.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;
bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;;
bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;;
bfd_m88k_arch) ta="$ta m88k-dis.lo" ;;

6
opcodes/disassemble.c
View File

@ -33,6 +33,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define ARCH_i370
#define ARCH_i386
#define ARCH_i960
#define ARCH_ia64
#define ARCH_fr30
#define ARCH_m32r
#define ARCH_m68k
@ -147,6 +148,11 @@ disassembler (abfd)
disassemble = print_insn_i960;
break;
#endif
#ifdef ARCH_ia64
case bfd_arch_ia64:
disassemble = print_insn_ia64;
break;
#endif
#ifdef ARCH_fr30
case bfd_arch_fr30:
disassemble = print_insn_fr30;

5580
opcodes/ia64-asmtab.c Normal file
View File

File diff suppressed because it is too large Load Diff

145
opcodes/ia64-asmtab.h Normal file
View File

@ -0,0 +1,145 @@
/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
Copyright (C) 1999 Free Software Foundation, Inc.
Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#ifndef IA64_ASMTAB_H
#define IA64_ASMTAB_H
#include "opcode/ia64.h"
/* The primary opcode table is made up of the following: */
struct ia64_main_table
{
/* The entry in the string table that corresponds to the name of this
opcode. */
unsigned short name_index;
/* The type of opcode; corresponds to the TYPE field in
struct ia64_opcode. */
unsigned char opcode_type;
/* The number of outputs for this opcode. */
unsigned char num_outputs;
/* The base insn value for this opcode. It may be modified by completers. */
ia64_insn opcode;
/* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
ia64_insn mask;
/* The operands of this instruction. Corresponds to the OPERANDS field
in struct ia64_opcode. */
unsigned char operands[5];
/* The flags for this instruction. Corresponds to the FLAGS field in
struct ia64_opcode. */
short flags;
/* The tree of completers for this instruction; this is an offset into
completer_table. */
short completers;
};
/* Each instruction has a set of possible "completers", or additional
suffixes that can alter the instruction's behavior, and which has
potentially different dependencies.
The completer entries modify certain bits in the instruction opcode.
Which bits are to be modified are marked by the BITS, MASK and
OFFSET fields. The completer entry may also note dependencies for the
opcode.
These completers are arranged in a DAG; the pointers are indexes
into the completer_table array. The completer DAG is searched by
find_completer () and ia64_find_matching_opcode ().
Note that each completer needs to be applied in turn, so that if we
have the instruction
cmp.lt.unc
the completer entries for both "lt" and "unc" would need to be applied
to the opcode's value.
Some instructions do not require any completers; these contain an
empty completer entry. Instructions that require a completer do
not contain an empty entry.
Terminal completers (those completers that validly complete an
instruction) are marked by having the TERMINAL_COMPLETER flag set.
Only dependencies listed in the terminal completer for an opcode are
considered to apply to that opcode instance. */
struct ia64_completer_table
{
/* The bit value that this completer sets. */
unsigned int bits;
/* And its mask. 1s are bits that are to be modified in the
instruction. */
unsigned int mask;
/* The entry in the string table that corresponds to the name of this
completer. */
unsigned short name_index;
/* An alternative completer, or -1 if this is the end of the chain. */
short alternative;
/* A pointer to the DAG of completers that can potentially follow
this one, or -1. */
short subentries;
/* The bit offset in the instruction where BITS and MASK should be
applied. */
unsigned char offset : 7;
unsigned char terminal_completer : 1;
/* Index into the dependency list table */
short dependencies;
};
/* This contains sufficient information for the disassembler to resolve
the complete name of the original instruction. */
struct ia64_dis_names
{
/* COMPLETER_INDEX represents the tree of completers that make up
the instruction. The LSB represents the top of the tree for the
specified instruction.
A 0 bit indicates to go to the next alternate completer via the
alternative field; a 1 bit indicates that the current completer
is part of the instruction, and to go down the subentries index.
We know we've reached the final completer when we run out of 1
bits.
There is always at least one 1 bit. */
unsigned int completer_index : 20;
/* The index in the main_table[] array for the instruction. */
unsigned short insn_index : 11;
/* If set, the next entry in this table is an alternate possibility
for this instruction encoding. Which one to use is determined by
the instruction type and other factors (see opcode_verify ()). */
unsigned int next_flag : 1;
};
#endif

264
opcodes/ia64-dis.c Normal file
View File

@ -0,0 +1,264 @@
/* ia64-dis.c -- Disassemble ia64 instructions
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include <assert.h>
#include <string.h>
#include "dis-asm.h"
#include "opcode/ia64.h"
#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
/* Disassemble ia64 instruction. */
/* Return the instruction type for OPCODE found in unit UNIT. */
static enum ia64_insn_type
unit_to_type (ia64_insn opcode, enum ia64_unit unit)
{
enum ia64_insn_type type;
int op;
op = IA64_OP (opcode);
if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
{
type = IA64_TYPE_A;
}
else
{
switch (unit)
{
case IA64_UNIT_I:
type = IA64_TYPE_I; break;
case IA64_UNIT_M:
type = IA64_TYPE_M; break;
case IA64_UNIT_B:
type = IA64_TYPE_B; break;
case IA64_UNIT_F:
type = IA64_TYPE_F; break;
case IA64_UNIT_L:
case IA64_UNIT_X:
type = IA64_TYPE_X; break;
default:
type = -1;
}
}
return type;
}
int
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
{
ia64_insn t0, t1, slot[3], template, s_bit, insn;
int slotnum, j, status, need_comma, retval, slot_multiplier;
const struct ia64_operand *odesc;
const struct ia64_opcode *idesc;
const char *err, *str, *tname;
BFD_HOST_U_64_BIT value;
bfd_byte bundle[16];
enum ia64_unit unit;
char regname[16];
if (info->bytes_per_line == 0)
info->bytes_per_line = 6;
info->display_endian = info->endian;
slot_multiplier = info->bytes_per_line;
retval = slot_multiplier;
slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
if (slotnum > 2)
return -1;
memaddr -= (memaddr & 0xf);
status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* bundles are always in little-endian byte order */
t0 = bfd_getl64 (bundle);
t1 = bfd_getl64 (bundle + 8);
s_bit = t0 & 1;
template = (t0 >> 1) & 0xf;
slot[0] = (t0 >> 5) & 0x1ffffffffffLL;
slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
tname = ia64_templ_desc[template].name;
if (slotnum == 0)
(*info->fprintf_func) (info->stream, "[%s] ", tname);
else
(*info->fprintf_func) (info->stream, " ", tname);
unit = ia64_templ_desc[template].exec_unit[slotnum];
if (template == 2 && slotnum == 1)
{
/* skip L slot in MLI template: */
slotnum = 2;
retval += slot_multiplier;
}
insn = slot[slotnum];
if (unit == IA64_UNIT_NIL)
goto decoding_failed;
idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
if (idesc == NULL)
goto decoding_failed;
/* print predicate, if any: */
if ((idesc->flags & IA64_OPCODE_NO_PRED)
|| (insn & 0x3f) == 0)
(*info->fprintf_func) (info->stream, " ");
else
(*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
/* now the actual instruction: */
(*info->fprintf_func) (info->stream, "%s", idesc->name);
if (idesc->operands[0])
(*info->fprintf_func) (info->stream, " ");
need_comma = 0;
for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
{
odesc = elf64_ia64_operands + idesc->operands[j];
if (need_comma)
(*info->fprintf_func) (info->stream, ",");
if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
{
/* special case of 64 bit immediate load: */
value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
| (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
| (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
}
else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
{
/* 62-bit immediate for nop.x/break.x */
value = ((slot[1] & 0x1ffffffffffLL) << 21)
| (((insn >> 36) & 0x1) << 20)
| ((insn >> 6) & 0xfffff);
}
else
{
err = (*odesc->extract) (odesc, insn, &value);
if (err)
{
(*info->fprintf_func) (info->stream, "%s", err);
goto done;
}
}
switch (odesc->class)
{
case IA64_OPND_CLASS_CST:
(*info->fprintf_func) (info->stream, "%s", odesc->str);
break;
case IA64_OPND_CLASS_REG:
if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
{
switch (value)
{
case 0: case 1: case 2: case 3:
case 4: case 5: case 6: case 7:
sprintf (regname, "ar.k%u", (unsigned int) value);
break;
case 16: strcpy (regname, "ar.rsc"); break;
case 17: strcpy (regname, "ar.bsp"); break;
case 18: strcpy (regname, "ar.bspstore"); break;
case 19: strcpy (regname, "ar.rnat"); break;
case 32: strcpy (regname, "ar.ccv"); break;
case 36: strcpy (regname, "ar.unat"); break;
case 40: strcpy (regname, "ar.fpsr"); break;
case 44: strcpy (regname, "ar.itc"); break;
case 64: strcpy (regname, "ar.pfs"); break;
case 65: strcpy (regname, "ar.lc"); break;
case 66: strcpy (regname, "ar.ec"); break;
default:
sprintf (regname, "ar%u", (unsigned int) value);
break;
}
(*info->fprintf_func) (info->stream, "%s", regname);
}
else
(*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
break;
case IA64_OPND_CLASS_IND:
(*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
break;
case IA64_OPND_CLASS_ABS:
str = 0;
if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
switch (value)
{
case 0x0: str = "@brcst"; break;
case 0x8: str = "@mix"; break;
case 0x9: str = "@shuf"; break;
case 0xa: str = "@alt"; break;
case 0xb: str = "@rev"; break;
}
if (str)
(*info->fprintf_func) (info->stream, "%s", str);
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
(*info->fprintf_func) (info->stream, "%lld", value);
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
(*info->fprintf_func) (info->stream, "%llu", value);
else
(*info->fprintf_func) (info->stream, "0x%llx", value);
break;
case IA64_OPND_CLASS_REL:
(*info->print_address_func) (memaddr + value, info);
break;
}
need_comma = 1;
if (j + 1 == idesc->num_outputs)
{
(*info->fprintf_func) (info->stream, "=");
need_comma = 0;
}
}
if (slotnum + 1 == ia64_templ_desc[template].group_boundary
|| ((slotnum == 2) && s_bit))
(*info->fprintf_func) (info->stream, ";;");
done:
if (slotnum == 2)
retval += 16 - 3*slot_multiplier;
return retval;
decoding_failed:
(*info->fprintf_func) (info->stream, " data8 %#011llx", insn);
goto done;
}

2723
opcodes/ia64-gen.c Normal file
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205
opcodes/ia64-ic.tbl Normal file
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@ -0,0 +1,205 @@
Class; Events/Instructions
all; IC:predicatable-instructions, IC:unpredicatable-instructions
branches; IC:indirect-brs, IC:ip-rel-brs
cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e
chk-a; chk.a.clr, chk.a.nc
cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8
czx; czx1, czx2
fcmp-s0; fcmp[Field(sf)==s0]
fcmp-s1; fcmp[Field(sf)==s1]
fcmp-s2; fcmp[Field(sf)==s2]
fcmp-s3; fcmp[Field(sf)==s3]
fetchadd; fetchadd4, fetchadd8
fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub
fp-arith-s0; IC:fp-arith[Field(sf)==s0]
fp-arith-s1; IC:fp-arith[Field(sf)==s1]
fp-arith-s2; IC:fp-arith[Field(sf)==s2]
fp-arith-s3; IC:fp-arith[Field(sf)==s3]
fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma
fpcmp-s0; fpcmp[Field(sf)==s0]
fpcmp-s1; fpcmp[Field(sf)==s1]
fpcmp-s2; fpcmp[Field(sf)==s2]
fpcmp-s3; fpcmp[Field(sf)==s3]
fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf
fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp
gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat
gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt
gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-immediate, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl
indirect-brp; brp[Format in {B7}]
indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret
invala-all; invala[Format in {M24}], invala.e
ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop
ld; ld1, ld2, ld4, ld8, ld8.fill
ld-a; ld1.a, ld2.a, ld4.a, ld8.a
ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}]
ld-c; IC:ld-c-nc, IC:ld-c-clr
ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq
ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq
ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc
ld-s; ld1.s, ld2.s, ld4.s, ld8.s
ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa
ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill
ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a
ldf-c; IC:ldf-c-nc, IC:ldf-c-clr
ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr
ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc
ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s
ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa
ldfp; ldfps, ldfpd, ldfp8
ldfp-a; ldfps.a, ldfpd.a, ldfp8.a
ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr
ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr
ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc
ldfp-s; ldfps.s, ldfpd.s, ldfp8.s
ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa
lfetch-all; lfetch
lfetch-fault; lfetch[Field(lftype)==fault]
lfetch-nofault; lfetch[Field(lftype)==]
lfetch-postinc; lfetch[Format in {M14 M15}]
mem-readers; IC:mem-readers-fp, IC:mem-readers-int
mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c
mem-readers-fp; IC:ldf, IC:ldfp
mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld
mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa
mem-writers; IC:mem-writers-fp, IC:mem-writers-int
mem-writers-fp; IC:stf
mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st
mix; mix1, mix2, mix4
mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop
mod-sched-brs-counted; br.cexit, br.cloop, br.ctop
mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC]
mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR]
mov-from-AR-I; mov_ar[Format in {I28}]
mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}]
mov-from-AR-IM; mov_ar[Format in {I28 M31}]
mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC]
mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC]
mov-from-AR-M; mov_ar[Format in {M31}]
mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS]
mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT]
mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC]
mov-from-AR-rv; IC:none
mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT]
mov-from-BR; mov_br[Format in {I22}]
mov-from-CR; mov_cr[Format in {M33}]
mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV]
mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR]
mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI]
mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA]
mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA]
mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS]
mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA]
mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM]
mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP]
mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA]
mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR]
mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR]
mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR]
mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM]
mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV]
mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA]
mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR]
mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID]
mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}]
mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV]
mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA]
mov-from-CR-rv; IC:none
mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR]
mov-from-IND; mov_indirect[Format in {M43}]
mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid]
mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr]
mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr]
mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr]
mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr]
mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc]
mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd]
mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}]
mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr]
mov-from-PR; mov_pr[Format in {I25}]
mov-from-PSR; mov_psr[Format in {M36}]
mov-from-PSR-um; mov_um[Format in {M36}]
mov-immediate; addl[Format in {A5}]
mov-ip; mov_ip[Format in {I25}]
mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I
mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP]
mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE]
mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV]
mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC]
mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR]
mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}]
mov-to-AR-I; mov_ar[Format in {I26 I27}]
mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}]
mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}]
mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC]
mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC]
mov-to-AR-M; mov_ar[Format in {M29 M30}]
mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS]
mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT]
mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC]
mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT]
mov-to-BR; mov_br[Format in {I21}]
mov-to-CR; mov_cr[Format in {M32}]
mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV]
mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR]
mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI]
mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA]
mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA]
mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS]
mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA]
mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM]
mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP]
mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA]
mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR]
mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR]
mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR]
mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM]
mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV]
mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA]
mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR]
mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID]
mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}]
mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV]
mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA]
mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR]
mov-to-IND; mov_indirect[Format in {M42}]
mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid]
mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr]
mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr]
mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr]
mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr]
mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc]
mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd]
mov-to-IND-priv; IC:mov-to-IND
mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr]
mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg
mov-to-PR-allreg; mov_pr[Format in {I23}]
mov-to-PR-rotreg; mov_pr[Format in {I24}]
mov-to-PSR-l; mov_psr[Format in {M35}]
mov-to-PSR-um; mov_um[Format in {M35}]
mux; mux1, mux2
none; -
pack; pack2, pack4
padd; padd1, padd2, padd4
pavg; pavg1, pavg2
pavgsub; pavgsub1, pavgsub2
pcmp; pcmp1, pcmp2, pcmp4
pmax; pmax1, pmax2
pmin; pmin1, pmin2
pmpy; pmpy2
pmpyshr; pmpyshr2
pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
pr-gen-writers-fp; fclass, fcmp
pr-gen-writers-int; cmp, cmp4, tbit, tnat
pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==]
pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==]
pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, break, nop.b, nop, IC:ReservedBQP
pr-readers-nobr-nomovpr; add, addp4, and, andcm, break.f, break.i, break.m, break.x, break, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-immediate, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, nop, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak,

364
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/* ia64-opc-a.c -- IA-64 `A' opcode table.
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
#define A IA64_TYPE_A, 1
#define A2 IA64_TYPE_A, 2
/* instruction bit fields: */
#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \
(((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \
(((ia64_insn) (((x) >> 13) & 0x01)) << 36))
#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20)
#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20)
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27)
#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29)
#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
/* instruction bit masks: */
#define mC bC (-1)
#define mImm14 bImm14 (-1)
#define mR3a bR3a (-1)
#define mR3b bR3b (-1)
#define mTa bTa (-1)
#define mTb bTb (-1)
#define mVe bVe (-1)
#define mX bX (-1)
#define mX2 bX2 (-1)
#define mX2a bX2a (-1)
#define mX2b bX2b (-1)
#define mX4 bX4 (-1)
#define mZa bZa (-1)
#define mZb bZb (-1)
#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b)
#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \
(mOp | mX2a | mVe)
#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
(mOp | mX2a | mVe | mR3a)
#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
(mOp | mX2a | mVe | mImm14)
#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
(mOp | mX2a | mVe | mX4)
#define OpX2aVeX4X2b(a,b,c,d,e) \
(bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
(mOp | mX2a | mVe | mX4 | mX2b)
#define OpX2TbTaC(a,b,c,d,e) \
(bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
(mOp | mX2 | mTb | mTa | mC)
#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
(mOp | mX2 | mTa | mC)
#define OpX2aZaZbX4(a,b,c,d,e) \
(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
(mOp | mX2a | mZa | mZb | mX4)
#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
(mOp | mX2a | mZa | mZb | mX4 | mX2b)
struct ia64_opcode ia64_opcodes_a[] =
{
/* A-type instruction encodings (sorted according to major opcode) */
{"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}},
{"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}},
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}},
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}},
{"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}},
{"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}},
{"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}},
{"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}},
{"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}},
{"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}},
{"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}},
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}},
{"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}},
{"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}},
{"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}},
{"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}},
{"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}},
{"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO},
{"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}},
{"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}},
{"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}},
{"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}},
{"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}},
{"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}},
{"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}},
{"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}},
{"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}},
{"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}},
{"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}},
{"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}},
{"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}},
{"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}},
{"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}},
{"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}},
{"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}},
{"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}},
{"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}},
{"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}},
{"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}},
{"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}},
{"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}},
{"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}},
{"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}},
{"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}},
{"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}},
{"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}},
{"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}},
{"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}},
{"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}},
{"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}},
{"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}},
{"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}},
{"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO},
{"addl", A, Op (9), {R1, IMM22, R3_2}},
{"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}},
{"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}},
{"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}},
{"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}},
{"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}},
{"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}},
{"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}},
{"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}},
{"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}},
{"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}},
{"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}},
{"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}},
{"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}},
{"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}},
{"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}},
{"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}},
{"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}},
{"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}},
{"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}},
{"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}},
{"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}},
{"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}},
{"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}},
{"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}},
{"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}},
{"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}},
{"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}},
{"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}},
{"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}},
{"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}},
{"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}},
{"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}},
{"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}},
{"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}},
{"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}},
{"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}},
{"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}},
{"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}},
{"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
{"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
{"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
{"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
{"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}},
{"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}},
{"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}},
{"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}},
{"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}},
{"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
{"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}},
{"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
{"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}},
{"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}},
{"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}},
{"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
{"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}},
{"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
{0}
};
#undef A
#undef A2
#undef bC
#undef bImm14
#undef bR3a
#undef bR3b
#undef bTa
#undef bTb
#undef bVe
#undef bX
#undef bX2
#undef bX2a
#undef bX2b
#undef bX4
#undef bZa
#undef bZb
#undef mC
#undef mImm14
#undef mR3a
#undef mR3b
#undef mTa
#undef mTb
#undef mVe
#undef mX
#undef mX2
#undef mX2a
#undef mX2b
#undef mX4
#undef mZa
#undef mZb
#undef OpR3a
#undef OpR3b
#undef OpX2aVe
#undef OpX2aVeImm14
#undef OpX2aVeX4
#undef OpX2aVeX4X2b
#undef OpX2TbTaC
#undef OpX2TaC
#undef OpX2aZaZbX4
#undef OpX2aZaZbX4X2b

486
opcodes/ia64-opc-b.c Normal file
View File

@ -0,0 +1,486 @@
/* ia64-opc-b.c -- IA-64 `B' opcode table.
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
#define B0 IA64_TYPE_B, 0
#define B IA64_TYPE_B, 1
/* instruction bit fields: */
#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35)
#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define mBtype bBtype (-1)
#define mD bD (-1)
#define mIh bIh (-1)
#define mPa bPa (-1)
#define mPr bPr (-1)
#define mWha bWha (-1)
#define mWhb bWhb (-1)
#define mX6 bX6 (-1)
#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6)
#define OpPaWhaD(a,b,c,d) \
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
#define OpBtypePaWhaD(a,b,c,d,e) \
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
(mOp | mBtype | mPa | mWha | mD)
#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
(mOp | mBtype | mPa | mWha | mD | mPr)
#define OpX6BtypePaWhaD(a,b,c,d,e,f) \
(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \
(mOp | mX6 | mBtype | mPa | mWha | mD)
#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \
(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \
(mOp | mX6 | mBtype | mPa | mWha | mD | mPr)
#define OpIhWhb(a,b,c) \
(bOp (a) | bIh (b) | bWhb (c)), \
(mOp | mIh | mWhb)
#define OpX6IhWhb(a,b,c,d) \
(bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \
(mOp | mX6 | mIh | mWhb)
struct ia64_opcode ia64_opcodes_b[] =
{
/* B-type instruction encodings (sorted according to major opcode) */
#define BR(a,b) \
B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO
{"br.few", BR (0, 0)},
{"br", BR (0, 0)},
{"br.few.clr", BR (0, 1)},
{"br.clr", BR (0, 1)},
{"br.many", BR (1, 0)},
{"br.many.clr", BR (1, 1)},
#undef BR
#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}
{"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)},
{"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO},
{"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
{"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO},
{"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)},
{"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO},
{"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
{"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO},
{"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)},
{"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO},
{"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
{"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO},
{"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)},
{"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO},
{"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
{"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO},
{"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)},
{"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
{"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)},
{"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
{"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)},
{"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
{"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)},
{"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
{"br.sptk.few", BR (0x20, 0, 0, 0, 0)},
{"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO},
{"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
{"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO},
{"br.spnt.few", BR (0x20, 0, 0, 1, 0)},
{"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO},
{"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
{"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO},
{"br.dptk.few", BR (0x20, 0, 0, 2, 0)},
{"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO},
{"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
{"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO},
{"br.dpnt.few", BR (0x20, 0, 0, 3, 0)},
{"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO},
{"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
{"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO},
{"br.sptk.many", BR (0x20, 0, 1, 0, 0)},
{"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
{"br.spnt.many", BR (0x20, 0, 1, 1, 0)},
{"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
{"br.dptk.many", BR (0x20, 0, 1, 2, 0)},
{"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
{"br.dpnt.many", BR (0x20, 0, 1, 3, 0)},
{"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
{"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)},
{"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO},
{"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)},
{"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO},
{"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)},
{"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO},
{"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)},
{"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO},
{"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)},
{"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO},
{"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)},
{"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO},
{"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)},
{"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO},
{"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)},
{"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO},
{"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)},
{"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)},
{"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)},
{"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)},
{"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)},
{"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)},
{"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)},
{"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)},
{"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS},
{"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS},
{"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS},
{"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS},
{"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS},
{"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS},
{"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS},
{"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS},
{"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS},
{"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS},
{"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS},
{"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS},
{"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS},
{"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS},
{"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS},
{"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS},
{"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS},
{"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS},
{"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS},
{"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS},
{"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS},
{"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS},
{"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS},
{"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS},
#undef BR
{"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS},
{"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS},
{"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS},
{"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS},
{"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV},
{"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV},
{"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED},
{"break.b", B0, OpX6 (0, 0x00), {IMMU21}},
{"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}},
{"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO},
{"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}},
{"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO},
{"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}},
{"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO},
{"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}},
{"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO},
{"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}},
{"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO},
{"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}},
{"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO},
{"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}},
{"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO},
{"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}},
{"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO},
{"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}},
{"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}},
{"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}},
{"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}},
{"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}},
{"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}},
{"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}},
{"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}},
#define BRP(a,b,c) \
B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED
{"brp.sptk", BRP (0x10, 0, 0)},
{"brp.dptk", BRP (0x10, 0, 2)},
{"brp.sptk.imp", BRP (0x10, 1, 0)},
{"brp.dptk.imp", BRP (0x10, 1, 2)},
{"brp.ret.sptk", BRP (0x11, 0, 0)},
{"brp.ret.dptk", BRP (0x11, 0, 2)},
{"brp.ret.sptk.imp", BRP (0x11, 1, 0)},
{"brp.ret.dptk.imp", BRP (0x11, 1, 2)},
#undef BRP
{"nop.b", B0, OpX6 (2, 0x00), {IMMU21}},
#define BR(a,b) \
B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO
{"br.few", BR (0, 0)},
{"br", BR (0, 0)},
{"br.few.clr", BR (0, 1)},
{"br.clr", BR (0, 1)},
{"br.many", BR (1, 0)},
{"br.many.clr", BR (1, 1)},
#undef BR
{"br.cond.sptk.few", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}},
{"br.cond.sptk", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO},
{"br.cond.sptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}},
{"br.cond.sptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO},
{"br.cond.spnt.few", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}},
{"br.cond.spnt", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO},
{"br.cond.spnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}},
{"br.cond.spnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO},
{"br.cond.dptk.few", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}},
{"br.cond.dptk", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO},
{"br.cond.dptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}},
{"br.cond.dptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO},
{"br.cond.dpnt.few", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}},
{"br.cond.dpnt", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO},
{"br.cond.dpnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}},
{"br.cond.dpnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO},
{"br.cond.sptk.many", B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}},
{"br.cond.sptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}},
{"br.cond.spnt.many", B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}},
{"br.cond.spnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}},
{"br.cond.dptk.many", B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}},
{"br.cond.dptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}},
{"br.cond.dpnt.many", B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}},
{"br.cond.dpnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}},
{"br.sptk.few", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}},
{"br.sptk", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO},
{"br.sptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}},
{"br.sptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO},
{"br.spnt.few", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}},
{"br.spnt", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO},
{"br.spnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}},
{"br.spnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO},
{"br.dptk.few", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}},
{"br.dptk", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO},
{"br.dptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}},
{"br.dptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO},
{"br.dpnt.few", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}},
{"br.dpnt", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO},
{"br.dpnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}},
{"br.dpnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO},
{"br.sptk.many", B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}},
{"br.sptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}},
{"br.spnt.many", B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}},
{"br.spnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}},
{"br.dptk.many", B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}},
{"br.dptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}},
{"br.dpnt.many", B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}},
{"br.dpnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}},
#define BR(a,b,c,d) \
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
{"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS},
{"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS},
{"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS},
{"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS},
{"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS},
{"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS},
{"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS},
{"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS},
{"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS},
{"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS},
{"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS},
{"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS},
{"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS},
{"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS},
{"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS},
{"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS},
{"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS},
{"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS},
{"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS},
{"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS},
{"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS},
{"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS},
{"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS},
{"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS},
{"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS},
{"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS},
{"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS},
{"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS},
{"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS},
{"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS},
{"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS},
{"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS},
#undef BR
#define BR(a,b,c,d) \
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED
{"br.cloop.sptk.few", BR (5, 0, 0, 0)},
{"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO},
{"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)},
{"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO},
{"br.cloop.spnt.few", BR (5, 0, 1, 0)},
{"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO},
{"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)},
{"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO},
{"br.cloop.dptk.few", BR (5, 0, 2, 0)},
{"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO},
{"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)},
{"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO},
{"br.cloop.dpnt.few", BR (5, 0, 3, 0)},
{"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO},
{"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)},
{"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO},
{"br.cloop.sptk.many", BR (5, 1, 0, 0)},
{"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)},
{"br.cloop.spnt.many", BR (5, 1, 1, 0)},
{"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)},
{"br.cloop.dptk.many", BR (5, 1, 2, 0)},
{"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)},
{"br.cloop.dpnt.many", BR (5, 1, 3, 0)},
{"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)},
{"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS},
{"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS},
{"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS},
{"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS},
{"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS},
{"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS},
{"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS},
{"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS},
{"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS},
{"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS},
{"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS},
{"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS},
{"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS},
{"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS},
{"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS},
{"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS},
{"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS},
{"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS},
{"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS},
{"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS},
{"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS},
{"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS},
{"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS},
{"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS},
{"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS},
{"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS},
{"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS},
{"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS},
{"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS},
{"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS},
{"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS},
{"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS},
#undef BR
#define BR(a,b,c,d) \
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
{"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}},
{"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO},
{"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}},
{"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO},
{"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}},
{"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO},
{"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}},
{"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO},
{"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}},
{"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO},
{"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}},
{"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO},
{"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}},
{"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO},
{"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}},
{"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO},
{"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}},
{"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}},
{"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}},
{"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}},
{"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}},
{"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}},
{"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}},
{"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}},
#undef BR
/* branch predict */
#define BRP(a,b) \
B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED
{"brp.sptk", BRP (0, 0)},
{"brp.loop", BRP (0, 1)},
{"brp.dptk", BRP (0, 2)},
{"brp.exit", BRP (0, 3)},
{"brp.sptk.imp", BRP (1, 0)},
{"brp.loop.imp", BRP (1, 1)},
{"brp.dptk.imp", BRP (1, 2)},
{"brp.exit.imp", BRP (1, 3)},
#undef BRP
{0}
};
#undef B0
#undef B
#undef bBtype
#undef bD
#undef bIh
#undef bPa
#undef bPr
#undef bWha
#undef bWhb
#undef bX6
#undef mBtype
#undef mD
#undef mIh
#undef mPa
#undef mPr
#undef mWha
#undef mWhb
#undef mX6
#undef OpX6
#undef OpPaWhaD
#undef OpBtypePaWhaD
#undef OpBtypePaWhaDPr
#undef OpX6BtypePaWhaD
#undef OpX6BtypePaWhaDPr
#undef OpIhWhb
#undef OpX6IhWhb

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