Add Intel MCU support to gas
-march=iamcu must be passed to i386 assembler to generate Intel MCU object file. gas/ * config/tc-i386.c (cpu_arch): Add iamcu. (i386_align_code): Handle PROCESSOR_IAMCU. (i386_arch): Likewise. (i386_mach): Likewise. (i386_target_format): Likewise. (valid_iamcu_cpu_flags): New function. (check_cpu_arch_compatible): Only allow Intel MCU instructions when targeting Intel MCU. (set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags are valid for Intel MCU. (md_parse_option): Likewise. * tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New. (processor_type): Add PROCESSOR_IAMCU. * doc/c-i386.texi: Document iamcu. gas/testsuite/ * gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1, iamcu-inval-2 and iamcu-inval-3. * gas/i386/iamcu-1.d: New file. * gas/i386/iamcu-1.s: Likewise. * gas/i386/iamcu-2.d: Likewise. * gas/i386/iamcu-2.s: Likewise. * gas/i386/iamcu-3.d: Likewise. * gas/i386/iamcu-3.s: Likewise. * gas/i386/iamcu-inval-1.l: Likewise. * gas/i386/iamcu-inval-1.s: Likewise. * gas/i386/iamcu-inval-2.l: Likewise. * gas/i386/iamcu-inval-2.s: Likewise. * gas/i386/iamcu-inval-3.l: Likewise. * gas/i386/iamcu-inval-3.s: Likewise.
This commit is contained in:
H.J. Lu
parent
7b6d09fbc6
commit
814860358c
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@ -1,3 +1,20 @@
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2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add iamcu.
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(i386_align_code): Handle PROCESSOR_IAMCU.
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(i386_arch): Likewise.
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(i386_mach): Likewise.
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(i386_target_format): Likewise.
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(valid_iamcu_cpu_flags): New function.
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(check_cpu_arch_compatible): Only allow Intel MCU instructions
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when targeting Intel MCU.
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(set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags
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are valid for Intel MCU.
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(md_parse_option): Likewise.
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* tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New.
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(processor_type): Add PROCESSOR_IAMCU.
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* doc/c-i386.texi: Document iamcu.
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2015-05-08 Nick Clifton <nickc@redhat.com>
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PR gas/18347
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@ -772,6 +772,8 @@ static const arch_entry cpu_arch[] =
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CPU_L1OM_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
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CPU_K1OM_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
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CPU_IAMCU_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
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CPU_K6_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
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@ -1218,6 +1220,7 @@ i386_align_code (fragS *fragP, int count)
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case PROCESSOR_I486:
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case PROCESSOR_PENTIUM:
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case PROCESSOR_PENTIUMPRO:
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case PROCESSOR_IAMCU:
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case PROCESSOR_GENERIC32:
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patt = f32_patt;
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break;
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@ -1236,6 +1239,7 @@ i386_align_code (fragS *fragP, int count)
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case PROCESSOR_I386:
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case PROCESSOR_I486:
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case PROCESSOR_PENTIUM:
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case PROCESSOR_IAMCU:
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case PROCESSOR_K6:
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case PROCESSOR_ATHLON:
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case PROCESSOR_K8:
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@ -1469,6 +1473,20 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
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return x;
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}
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static int
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valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
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{
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if (cpu_arch_isa == PROCESSOR_IAMCU)
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{
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static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
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i386_cpu_flags compat_flags;
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compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
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return cpu_flags_all_zero (&compat_flags);
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}
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else
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return 1;
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}
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#define CPU_FLAGS_ARCH_MATCH 0x1
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#define CPU_FLAGS_64BIT_MATCH 0x2
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#define CPU_FLAGS_AES_MATCH 0x4
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@ -2278,6 +2296,11 @@ check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
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arch = default_arch;
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}
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/* If we are targeting Intel MCU, we must enable it. */
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if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
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|| new_flag.bitfield.cpuiamcu)
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return;
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/* If we are targeting Intel L1OM, we must enable it. */
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if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
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|| new_flag.bitfield.cpul1om)
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@ -2341,7 +2364,11 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
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else
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flags = cpu_flags_and_not (cpu_arch_flags,
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cpu_arch[j].flags);
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if (!cpu_flags_equal (&flags, &cpu_arch_flags))
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if (!valid_iamcu_cpu_flags (&flags))
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as_fatal (_("`%s' isn't valid for Intel MCU"),
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cpu_arch[j].name);
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else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
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{
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if (cpu_sub_arch_name)
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{
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@ -2406,6 +2433,13 @@ i386_arch (void)
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as_fatal (_("Intel K1OM is 64bit ELF only"));
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return bfd_arch_k1om;
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}
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else if (cpu_arch_isa == PROCESSOR_IAMCU)
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{
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if (OUTPUT_FLAVOR != bfd_target_elf_flavour
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|| flag_code == CODE_64BIT)
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as_fatal (_("Intel MCU is 32bit ELF only"));
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return bfd_arch_iamcu;
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}
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else
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return bfd_arch_i386;
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}
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@ -2435,7 +2469,16 @@ i386_mach (void)
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return bfd_mach_x64_32;
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}
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else if (!strcmp (default_arch, "i386"))
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return bfd_mach_i386_i386;
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{
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if (cpu_arch_isa == PROCESSOR_IAMCU)
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{
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if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
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as_fatal (_("Intel MCU is 32bit ELF only"));
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return bfd_mach_i386_iamcu;
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}
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else
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return bfd_mach_i386_i386;
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}
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else
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as_fatal (_("unknown architecture"));
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}
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@ -9678,7 +9721,10 @@ md_parse_option (int c, char *arg)
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else
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flags = cpu_flags_and_not (cpu_arch_flags,
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cpu_arch[j].flags);
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if (!cpu_flags_equal (&flags, &cpu_arch_flags))
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if (!valid_iamcu_cpu_flags (&flags))
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as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
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else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
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{
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if (cpu_sub_arch_name)
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{
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@ -10088,6 +10134,12 @@ i386_target_format (void)
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as_fatal (_("Intel K1OM is 64bit only"));
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return ELF_TARGET_K1OM_FORMAT;
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}
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else if (cpu_arch_isa == PROCESSOR_IAMCU)
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{
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if (x86_elf_abi != I386_ABI)
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as_fatal (_("Intel MCU is 32bit only"));
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return ELF_TARGET_IAMCU_FORMAT;
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}
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else
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return format;
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}
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@ -90,6 +90,10 @@ extern unsigned long i386_mach (void);
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#define ELF_TARGET_K1OM_FORMAT "elf64-k1om"
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#endif
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#ifndef ELF_TARGET_IAMCU_FORMAT
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#define ELF_TARGET_IAMCU_FORMAT "elf32-iamcu"
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#endif
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#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
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|| defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
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|| defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
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@ -233,6 +237,7 @@ enum processor_type
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PROCESSOR_COREI7,
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PROCESSOR_L1OM,
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PROCESSOR_K1OM,
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PROCESSOR_IAMCU,
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PROCESSOR_K6,
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PROCESSOR_ATHLON,
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PROCESSOR_K8,
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@ -110,6 +110,7 @@ processor names are recognized:
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@code{corei7},
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@code{l1om},
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@code{k1om},
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@code{iamcu},
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@code{k6},
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@code{k6_2},
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@code{athlon},
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@ -1082,7 +1083,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
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@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
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@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
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@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
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@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @samp{iamcu}
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@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
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@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
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@item @samp{bdver4} @tab @samp{znver1} @tab @samp{btver1} @tab @samp{btver2}
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@ -1,3 +1,20 @@
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2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run iamcu-1, iamcu-2, iamcu-3, iamcu-inval-1,
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iamcu-inval-2 and iamcu-inval-3.
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* gas/i386/iamcu-1.d: New file.
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* gas/i386/iamcu-1.s: Likewise.
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* gas/i386/iamcu-2.d: Likewise.
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* gas/i386/iamcu-2.s: Likewise.
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* gas/i386/iamcu-3.d: Likewise.
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* gas/i386/iamcu-3.s: Likewise.
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* gas/i386/iamcu-inval-1.l: Likewise.
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* gas/i386/iamcu-inval-1.s: Likewise.
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* gas/i386/iamcu-inval-2.l: Likewise.
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* gas/i386/iamcu-inval-2.s: Likewise.
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* gas/i386/iamcu-inval-3.l: Likewise.
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* gas/i386/iamcu-inval-3.s: Likewise.
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2015-05-08 Nick Clifton <nickc@redhat.com>
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PR gas/18347
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@ -397,6 +397,15 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "relax-3"
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run_dump_test "relax-4"
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if {![istarget "*-*-nacl*"]} then {
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run_dump_test "iamcu-1"
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run_dump_test "iamcu-2"
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run_dump_test "iamcu-3"
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run_list_test "iamcu-inval-1" "-march=iamcu -al"
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run_list_test "iamcu-inval-2" "-march=iamcu -al"
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run_list_test "iamcu-inval-3" "-march=iamcu+sse4 -al"
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}
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}
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# This is a PE specific test.
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@ -414,8 +423,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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# Common tests
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if [expr [istarget "i*86-*-*"] || [istarget "x86_64-*-*"]] then {
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run_dump_test "intel-expr"
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run_dump_test "string-ok"
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if {![istarget "i*86-*-elfiamcu"]} then {
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run_dump_test "intel-expr"
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run_dump_test "string-ok"
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}
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run_list_test "string-bad" ""
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run_list_test "reg-bad" ""
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run_list_test "space1" "-al"
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@ -0,0 +1,52 @@
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#as: -J -march=iamcu
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#objdump: -dw
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#not-target: *-*-nacl*
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.*: +file format elf32-iamcu.*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
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[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
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[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
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[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
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[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
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[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
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[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
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[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
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[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%eax\),%ax
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[ ]*[a-f0-9]+: 0f be 00 movsbl \(%eax\),%eax
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[ ]*[a-f0-9]+: 0f bf 00 movswl \(%eax\),%eax
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[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%eax\),%ax
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[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%eax\),%eax
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[ ]*[a-f0-9]+: 0f b7 00 movzwl \(%eax\),%eax
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#pass
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@ -0,0 +1,51 @@
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# IAMCU instructions
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.text
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movsx %al, %si
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movsx %al, %esi
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movsx %ax, %esi
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movsx (%eax), %edx
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movsx (%eax), %dx
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movsxb (%eax), %dx
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movsxb (%eax), %edx
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movsxw (%eax), %edx
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movsbl (%eax), %edx
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movsbw (%eax), %dx
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movswl (%eax), %edx
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movzx %al, %si
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movzx %al, %esi
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movzx %ax, %esi
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movzx (%eax), %edx
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movzx (%eax), %dx
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movzxb (%eax), %dx
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movzxb (%eax), %edx
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movzxw (%eax), %edx
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movzb (%eax), %edx
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movzb (%eax), %dx
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movzbl (%eax), %edx
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movzbw (%eax), %dx
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movzwl (%eax), %edx
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.intel_syntax noprefix
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movsx si,al
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movsx esi,al
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movsx esi,ax
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movsx edx,BYTE PTR [eax]
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movsx dx,BYTE PTR [eax]
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movsx edx,WORD PTR [eax]
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movzx si,al
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movzx esi,al
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movzx esi,ax
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movzx edx,BYTE PTR [eax]
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movzx dx,BYTE PTR [eax]
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movzx edx,WORD PTR [eax]
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movsx ax, byte ptr [eax]
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movsx eax, byte ptr [eax]
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movsx eax, word ptr [eax]
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movzx ax, byte ptr [eax]
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movzx eax, byte ptr [eax]
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movzx eax, word ptr [eax]
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@ -0,0 +1,11 @@
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#as: -J -march=iamcu
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#objdump: -dw
|
||||
#not-target: *-*-nacl*
|
||||
|
||||
.*: +file format elf32-iamcu.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 66 0f 1f 00 nopw \(%eax\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
.text
|
||||
.arch .nop
|
||||
|
||||
nopw (%eax)
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#as: -J -march=iamcu+nop
|
||||
#objdump: -dw
|
||||
#not-target: *-*-nacl*
|
||||
|
||||
.*: +file format elf32-iamcu.*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <.text>:
|
||||
[ ]*[a-f0-9]+: 66 0f 1f 00 nopw \(%eax\)
|
||||
#pass
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
.text
|
||||
nopw (%eax)
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
.*: Assembler messages:
|
||||
.*:4: Error: .*
|
||||
.*:5: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:10: Error: .*
|
||||
.*:11: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Invalid Intel MCU instructions
|
||||
[ ]*2[ ]+\.text
|
||||
[ ]*3[ ]+
|
||||
[ ]*4[ ]+fnstsw
|
||||
[ ]*5[ ]+fstsw %ax
|
||||
[ ]*6[ ]+
|
||||
[ ]*7[ ]+cmove %eax,%ebx
|
||||
[ ]*8[ ]+nopw \(%eax\)
|
||||
[ ]*9[ ]+
|
||||
[ ]*10[ ]+movq %xmm1, \(%eax\)
|
||||
[ ]*11[ ]+movnti %eax, \(%eax\)
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# Invalid Intel MCU instructions
|
||||
.text
|
||||
|
||||
fnstsw
|
||||
fstsw %ax
|
||||
|
||||
cmove %eax,%ebx
|
||||
nopw (%eax)
|
||||
|
||||
movq %xmm1, (%eax)
|
||||
movnti %eax, (%eax)
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
.*: Assembler messages:
|
||||
.*:2: Fatal error: `.sse4.1' isn't valid for Intel MCU
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
# Invalid .arch for Intel MCU
|
||||
.arch .sse4.1
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
Assembler messages:
|
||||
Fatal error: `sse4' isn't valid for Intel MCU
|
||||
|
|
@ -0,0 +1 @@
|
|||
.include "iamcu-1.s"
|
||||
Loading…
Reference in New Issue