Improve HC11 simulator to support HC12
This commit is contained in:
Stephane Carrez
parent
11115521f6
commit
81e09ed832
|
|
@ -1,3 +1,62 @@
|
|||
2001-05-20 Stephane Carrez <Stephane.Carrez@worldnet.fr>
|
||||
|
||||
* Makefile.in (M68HC11_OBJS): Add m68hc12int.o.
|
||||
(m68hc12int.c): Generate using gencode -m6812.
|
||||
(m68hc11int.c): Likewise with -m6811.
|
||||
|
||||
* gencode.c (m6811_opcode_patterns): New patterns for 68HC12.
|
||||
(m6811_page1_opcodes): Remove duplicate entries.
|
||||
(m6811_page2_opcodes): Likewise.
|
||||
(m6811_page3_opcodes): Likewise.
|
||||
(m6811_page4_opcodes): Likewise.
|
||||
(m6812_page1_opcodes): New table for 68HC12 instructions.
|
||||
(m6812_page2_opcodes): Likewise.
|
||||
(gen_fetch_operands): New modes [] and &[] for 68HC12 operands.
|
||||
(gen_save_result): Likewise.
|
||||
(gen_interpreter_for_table): Handle 68HC11 and 68HC12 opcodes.
|
||||
(cmp_opcode): New function for opcode comparision.
|
||||
(prepare_table): Sort the opcodes.
|
||||
(gen_interpreter): Prepare all the tables and generate either
|
||||
a 68HC11 or a 68HC12 simulator.
|
||||
(main): New options -m6811 and -m6812.
|
||||
|
||||
* m68hc11_sim.c (cpu_single_step): Use pointer to cpu interpretor.
|
||||
(cpu_special): Simulation of some 68HC12 instructions.
|
||||
(cpu_exg): New function.
|
||||
(cpu_dbcc): Likewise.
|
||||
(cpu_fetch_relbranch16): Likewise.
|
||||
(cpu_push_all): Push according to 68HC11 or 68HC12.
|
||||
(cpu_move16): Likewise.
|
||||
(cpu_move8): Likewise.
|
||||
(cpu_get_indexed_operand16): Likewise.
|
||||
(cpu_get_indexed_operand8): Likewise.
|
||||
(cpu_get_indexed_operand_addr): Likewise.
|
||||
(cpu_set_reg, cpu_set_dst_reg, cpu_get_src_reg, cpu_get_reg): Likewise.
|
||||
(cpu_reset): Setup INIT register according to architecture.
|
||||
|
||||
* sim-main.h (M6811_Special): Add 68HC12 specific instructions.
|
||||
(_sim_cpu): Keep track of the cpu being simulated.
|
||||
(cpu_get_tmp3, cpu_get_tmp2, cpu_set_tmp3, cpu_set_tmp2): New.
|
||||
(cpu_m68hc11_push_uintxx): Rename of cpu_push_uintxx.
|
||||
(cpu_m68hc11_pop_uint8): Likewise.
|
||||
(cpu_m68hc12_push_uintxx): New functions for 68HC12.
|
||||
(cpu_m68hc12_pop_uintxx): Likewise.
|
||||
(cpu_exg, cpu_dbcc, cpu_move8, cpu_move16): Likewise,
|
||||
(cpu_fetch_relbranch16): Likewise.
|
||||
(cpu_interp_m6811): Rename of cpu_interp.
|
||||
(cpu_interp_m6812): New function.
|
||||
* interp.c (free_state): New function.
|
||||
(dev_list_68hc12): New table.
|
||||
(sim_board_reset): Reset depending on the cpu (HC11 or HC12).
|
||||
(sim_hw_configure): New function.
|
||||
(sim_prepare_for_program): New function.
|
||||
(sim_open): Use above new functions.
|
||||
(sim_close): Call free_state().
|
||||
(sim_info): Print info according to cpu.
|
||||
(sim_create_inferior): Use sim_prepare_for_program.
|
||||
(sim_do_command): Configure the hardware after a change of the
|
||||
architecture.
|
||||
|
||||
2001-05-20 Stephane Carrez <Stephane.Carrez@worldnet.fr>
|
||||
|
||||
* dv-m68hc11sio.c (m68hc11sio_tx_poll): Always check for
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# Makefile template for Configure for the 68HC11 sim library.
|
||||
# Copyright (C) 1999, 2000 Free Software Foundation, Inc.
|
||||
# Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
|
||||
# Written by Cygnus Support.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
|
|
@ -18,7 +18,8 @@
|
|||
|
||||
## COMMON_PRE_CONFIG_FRAG
|
||||
|
||||
M68HC11_OBJS = interp.o m68hc11int.o emulos.o interrupts.o m68hc11_sim.o
|
||||
M68HC11_OBJS = interp.o m68hc11int.o m68hc12int.o \
|
||||
emulos.o interrupts.o m68hc11_sim.o
|
||||
|
||||
# List of main object files for `run'.
|
||||
SIM_RUN_OBJS = nrun.o
|
||||
|
|
@ -49,10 +50,13 @@ INCLUDE = $(srcdir)/../../include/callback.h \
|
|||
## COMMON_POST_CONFIG_FRAG
|
||||
|
||||
m68hc11int.c: gencode
|
||||
./gencode > $@
|
||||
./gencode -m6811 > $@
|
||||
|
||||
m68hc12int.c: gencode
|
||||
./gencode -m6812 > $@
|
||||
|
||||
gencode: gencode.c
|
||||
$(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode $<
|
||||
$(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.c
|
||||
|
||||
interp.o: interp.c $(INCLUDE)
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
/* interp.c -- Simulator for Motorola 68HC11
|
||||
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
|
||||
Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
|
||||
Written by Stephane Carrez (stcarrez@worldnet.fr)
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
|
@ -55,7 +55,7 @@ struct sim_info_list
|
|||
const char *device;
|
||||
};
|
||||
|
||||
struct sim_info_list dev_list[] = {
|
||||
struct sim_info_list dev_list_68hc11[] = {
|
||||
{"cpu", "/m68hc11"},
|
||||
{"timer", "/m68hc11/m68hc11tim"},
|
||||
{"sio", "/m68hc11/m68hc11sio"},
|
||||
|
|
@ -64,18 +64,48 @@ struct sim_info_list dev_list[] = {
|
|||
{0, 0}
|
||||
};
|
||||
|
||||
struct sim_info_list dev_list_68hc12[] = {
|
||||
{"cpu", "/m68hc12"},
|
||||
{"timer", "/m68hc12/m68hc12tim"},
|
||||
{"sio", "/m68hc12/m68hc12sio"},
|
||||
{"spi", "/m68hc12/m68hc12spi"},
|
||||
{"eeprom", "/m68hc12/m68hc12eepr"},
|
||||
{0, 0}
|
||||
};
|
||||
|
||||
/* Cover function of sim_state_free to free the cpu buffers as well. */
|
||||
|
||||
static void
|
||||
free_state (SIM_DESC sd)
|
||||
{
|
||||
if (STATE_MODULES (sd) != NULL)
|
||||
sim_module_uninstall (sd);
|
||||
|
||||
sim_state_free (sd);
|
||||
}
|
||||
|
||||
/* Give some information about the simulator. */
|
||||
static void
|
||||
sim_get_info (SIM_DESC sd, char *cmd)
|
||||
{
|
||||
sim_cpu *cpu;
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
if (cmd != 0 && (cmd[0] == ' ' || cmd[0] == '-'))
|
||||
{
|
||||
int i;
|
||||
struct hw *hw_dev;
|
||||
struct sim_info_list *dev_list;
|
||||
const struct bfd_arch_info *arch;
|
||||
|
||||
arch = STATE_ARCHITECTURE (sd);
|
||||
cmd++;
|
||||
|
||||
if (arch->arch == bfd_arch_m68hc11)
|
||||
dev_list = dev_list_68hc11;
|
||||
else
|
||||
dev_list = dev_list_68hc12;
|
||||
|
||||
for (i = 0; dev_list[i].name; i++)
|
||||
if (strcmp (cmd, dev_list[i].name) == 0)
|
||||
break;
|
||||
|
|
@ -96,7 +126,6 @@ sim_get_info (SIM_DESC sd, char *cmd)
|
|||
return;
|
||||
}
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
cpu_info (sd, cpu);
|
||||
interrupts_info (sd, &cpu->cpu_interrupts);
|
||||
}
|
||||
|
|
@ -107,13 +136,28 @@ sim_board_reset (SIM_DESC sd)
|
|||
{
|
||||
struct hw *hw_cpu;
|
||||
sim_cpu *cpu;
|
||||
const struct bfd_arch_info *arch;
|
||||
const char *cpu_type;
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
arch = STATE_ARCHITECTURE (sd);
|
||||
|
||||
/* hw_cpu = sim_hw_parse (sd, "/"); */
|
||||
hw_cpu = sim_hw_parse (sd, "/m68hc11");
|
||||
if (arch->arch == bfd_arch_m68hc11)
|
||||
{
|
||||
cpu->cpu_type = CPU_M6811;
|
||||
cpu_type = "/m68hc11";
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu->cpu_type = CPU_M6812;
|
||||
cpu_type = "/m68hc12";
|
||||
}
|
||||
|
||||
hw_cpu = sim_hw_parse (sd, cpu_type);
|
||||
if (hw_cpu == 0)
|
||||
{
|
||||
sim_io_eprintf (sd, "m68hc11 cpu not found in device tree.");
|
||||
sim_io_eprintf (sd, "%s cpu not found in device tree.", cpu_type);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -122,6 +166,144 @@ sim_board_reset (SIM_DESC sd)
|
|||
cpu_restart (cpu);
|
||||
}
|
||||
|
||||
int
|
||||
sim_hw_configure (SIM_DESC sd)
|
||||
{
|
||||
const struct bfd_arch_info *arch;
|
||||
struct hw *device_tree;
|
||||
int m6811_mode;
|
||||
sim_cpu *cpu;
|
||||
|
||||
arch = STATE_ARCHITECTURE (sd);
|
||||
if (arch == 0)
|
||||
return 0;
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
cpu->cpu_configured_arch = arch;
|
||||
device_tree = sim_hw_parse (sd, "/");
|
||||
if (arch->arch == bfd_arch_m68hc11)
|
||||
{
|
||||
cpu->cpu_interpretor = cpu_interp_m6811;
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
|
||||
{
|
||||
/* Allocate core managed memory */
|
||||
|
||||
/* the monitor */
|
||||
sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
|
||||
/* MONITOR_BASE, MONITOR_SIZE */
|
||||
0x8000, M6811_RAM_LEVEL, 0x8000);
|
||||
sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
|
||||
M6811_RAM_LEVEL);
|
||||
sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
|
||||
}
|
||||
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
|
||||
{
|
||||
/* M68hc11 Timer configuration. */
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
|
||||
}
|
||||
|
||||
/* Create the SPI device. */
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/nvram/reg") == 0)
|
||||
{
|
||||
/* M68hc11 persistent ram configuration. */
|
||||
sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
|
||||
sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
|
||||
sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
|
||||
/*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu->cpu_interpretor = cpu_interp_m6812;
|
||||
if (hw_tree_find_property (device_tree, "/m68hc12/reg") == 0)
|
||||
{
|
||||
/* Allocate core external memory. */
|
||||
sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
|
||||
0x8000, M6811_RAM_LEVEL, 0x8000);
|
||||
sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
|
||||
M6811_RAM_LEVEL);
|
||||
|
||||
sim_hw_parse (sd, "/m68hc12/reg 0x0 0x3FF");
|
||||
}
|
||||
|
||||
if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@1/reg"))
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12sio@1/backend stdio");
|
||||
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
|
||||
}
|
||||
if (!hw_tree_find_property (device_tree, "/m68hc12/m68hc12sio@2/reg"))
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12sio@2/reg 0xC8 0x8");
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12sio@2/backend tcp");
|
||||
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@2");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12tim/reg") == 0)
|
||||
{
|
||||
/* M68hc11 Timer configuration. */
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
|
||||
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
|
||||
}
|
||||
|
||||
/* Create the SPI device. */
|
||||
if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12spi/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12spi/reg 0x28 0x3");
|
||||
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc12/nvram/reg") == 0)
|
||||
{
|
||||
/* M68hc11 persistent ram configuration. */
|
||||
sim_hw_parse (sd, "/m68hc12/nvram/reg 0x2000 8192");
|
||||
sim_hw_parse (sd, "/m68hc12/nvram/file m68hc12.ram");
|
||||
sim_hw_parse (sd, "/m68hc12/nvram/mode save-modified");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc12/m68hc12eepr/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
|
||||
sim_hw_parse (sd, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
sim_prepare_for_program (SIM_DESC sd, struct _bfd* abfd)
|
||||
{
|
||||
sim_cpu *cpu;
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
|
||||
sim_hw_configure (sd);
|
||||
if (abfd != NULL)
|
||||
{
|
||||
cpu->cpu_elf_start = bfd_get_start_address (abfd);
|
||||
}
|
||||
|
||||
/* reset all state information */
|
||||
sim_board_reset (sd);
|
||||
|
||||
return SIM_RC_OK;
|
||||
}
|
||||
|
||||
SIM_DESC
|
||||
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
|
||||
struct _bfd *abfd, char **argv)
|
||||
|
|
@ -144,7 +326,10 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
|
|||
|
||||
cpu->cpu_use_elf_start = 1;
|
||||
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
|
||||
return 0;
|
||||
{
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* getopt will print the error message so we just have to exit if this fails.
|
||||
FIXME: Hmmm... in the case of gdb we need getopt to call
|
||||
|
|
@ -153,72 +338,24 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
|
|||
{
|
||||
/* Uninstall the modules to avoid memory leaks,
|
||||
file descriptor leaks, etc. */
|
||||
sim_module_uninstall (sd);
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_tree = sim_hw_parse (sd, "/");
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/reg") == 0)
|
||||
{
|
||||
/* Allocate core managed memory */
|
||||
|
||||
/* the monitor */
|
||||
sim_do_commandf (sd, "memory region 0x%lx@%d,0x%lx",
|
||||
/* MONITOR_BASE, MONITOR_SIZE */
|
||||
0x8000, M6811_RAM_LEVEL, 0x8000);
|
||||
sim_do_commandf (sd, "memory region 0x000@%d,0x8000",
|
||||
M6811_RAM_LEVEL);
|
||||
sim_hw_parse (sd, "/m68hc11/reg 0x1000 0x03F");
|
||||
}
|
||||
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11sio/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11sio/backend stdio");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11tim/reg") == 0)
|
||||
{
|
||||
/* M68hc11 Timer configuration. */
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
|
||||
}
|
||||
|
||||
/* Create the SPI device. */
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11spi/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11spi/reg 0x28 0x3");
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/pram/reg") == 0)
|
||||
{
|
||||
/* M68hc11 persistent ram configuration. */
|
||||
sim_hw_parse (sd, "/m68hc11/nvram/reg 0x0 256");
|
||||
sim_hw_parse (sd, "/m68hc11/nvram/file m68hc11.ram");
|
||||
sim_hw_parse (sd, "/m68hc11/nvram/mode save-modified");
|
||||
/*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
|
||||
}
|
||||
if (hw_tree_find_property (device_tree, "/m68hc11/m68hc11eepr/reg") == 0)
|
||||
{
|
||||
sim_hw_parse (sd, "/m68hc11/m68hc11eepr/reg 0xb000 512");
|
||||
/* Connect the CPU reset to all devices. */
|
||||
sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
|
||||
}
|
||||
|
||||
/* Check for/establish the a reference program image. */
|
||||
if (sim_analyze_program (sd,
|
||||
(STATE_PROG_ARGV (sd) != NULL
|
||||
? *STATE_PROG_ARGV (sd)
|
||||
: NULL), abfd) != SIM_RC_OK)
|
||||
{
|
||||
sim_module_uninstall (sd);
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Establish any remaining configuration options. */
|
||||
if (sim_config (sd) != SIM_RC_OK)
|
||||
{
|
||||
sim_module_uninstall (sd);
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -226,16 +363,11 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
|
|||
{
|
||||
/* Uninstall the modules to avoid memory leaks,
|
||||
file descriptor leaks, etc. */
|
||||
sim_module_uninstall (sd);
|
||||
free_state (sd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (abfd != NULL)
|
||||
{
|
||||
cpu->cpu_elf_start = bfd_get_start_address (abfd);
|
||||
}
|
||||
|
||||
sim_board_reset (sd);
|
||||
sim_hw_configure (sd);
|
||||
|
||||
/* Fudge our descriptor. */
|
||||
return sd;
|
||||
|
|
@ -253,7 +385,7 @@ sim_close (SIM_DESC sd, int quitting)
|
|||
sim_io_shutdown (sd);
|
||||
|
||||
/* FIXME - free SD */
|
||||
|
||||
sim_state_free (sd);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -302,8 +434,17 @@ sim_trace (SIM_DESC sd)
|
|||
void
|
||||
sim_info (SIM_DESC sd, int verbose)
|
||||
{
|
||||
const char *cpu_type;
|
||||
const struct bfd_arch_info *arch;
|
||||
|
||||
arch = STATE_ARCHITECTURE (sd);
|
||||
if (arch->arch == bfd_arch_m68hc11)
|
||||
cpu_type = "68HC11";
|
||||
else
|
||||
cpu_type = "68HC12";
|
||||
|
||||
sim_io_eprintf (sd, "Simulator info:\n");
|
||||
sim_io_eprintf (sd, " CPU Motorola 68HC11\n");
|
||||
sim_io_eprintf (sd, " CPU Motorola %s\n", cpu_type);
|
||||
sim_get_info (sd, 0);
|
||||
sim_module_info (sd, verbose || STATE_VERBOSE_P (sd));
|
||||
}
|
||||
|
|
@ -312,20 +453,7 @@ SIM_RC
|
|||
sim_create_inferior (SIM_DESC sd, struct _bfd *abfd,
|
||||
char **argv, char **env)
|
||||
{
|
||||
sim_cpu *cpu;
|
||||
int i;
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
|
||||
if (abfd != NULL)
|
||||
{
|
||||
cpu->cpu_elf_start = bfd_get_start_address (abfd);
|
||||
}
|
||||
|
||||
/* reset all state information */
|
||||
sim_board_reset (sd);
|
||||
|
||||
return SIM_RC_OK;
|
||||
return sim_prepare_for_program (sd, abfd);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -450,7 +578,9 @@ sim_do_command (SIM_DESC sd, char *cmd)
|
|||
{
|
||||
char *mm_cmd = "memory-map";
|
||||
char *int_cmd = "interrupt";
|
||||
sim_cpu *cpu;
|
||||
|
||||
cpu = STATE_CPU (sd, 0);
|
||||
/* Commands available from GDB: */
|
||||
if (sim_args_command (sd, cmd) != SIM_RC_OK)
|
||||
{
|
||||
|
|
@ -466,4 +596,8 @@ sim_do_command (SIM_DESC sd, char *cmd)
|
|||
else
|
||||
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
|
||||
}
|
||||
|
||||
/* If the architecture changed, re-configure. */
|
||||
if (STATE_ARCHITECTURE (sd) != cpu->cpu_configured_arch)
|
||||
sim_hw_configure (sd);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* m6811_cpu.c -- 68HC11 CPU Emulation
|
||||
Copyright 1999, 2000 Free Software Foundation, Inc.
|
||||
/* m6811_cpu.c -- 68HC11&68HC12 CPU Emulation
|
||||
Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
|
||||
Written by Stephane Carrez (stcarrez@worldnet.fr)
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
|
@ -305,6 +305,341 @@ cpu_set_sp (sim_cpu *cpu, uint16 val)
|
|||
cpu_update_frame (cpu, 0);
|
||||
}
|
||||
|
||||
uint16
|
||||
cpu_get_reg (sim_cpu* cpu, uint8 reg)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
case 0:
|
||||
return cpu_get_x (cpu);
|
||||
|
||||
case 1:
|
||||
return cpu_get_y (cpu);
|
||||
|
||||
case 2:
|
||||
return cpu_get_sp (cpu);
|
||||
|
||||
case 3:
|
||||
return cpu_get_pc (cpu);
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
uint16
|
||||
cpu_get_src_reg (sim_cpu* cpu, uint8 reg)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
case 0:
|
||||
return cpu_get_a (cpu);
|
||||
|
||||
case 1:
|
||||
return cpu_get_b (cpu);
|
||||
|
||||
case 2:
|
||||
return cpu_get_ccr (cpu);
|
||||
|
||||
case 3:
|
||||
return cpu_get_tmp3 (cpu);
|
||||
|
||||
case 4:
|
||||
return cpu_get_d (cpu);
|
||||
|
||||
case 5:
|
||||
return cpu_get_x (cpu);
|
||||
|
||||
case 6:
|
||||
return cpu_get_y (cpu);
|
||||
|
||||
case 7:
|
||||
return cpu_get_sp (cpu);
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
cpu_set_dst_reg (sim_cpu* cpu, uint8 reg, uint16 val)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
case 0:
|
||||
cpu_set_a (cpu, val);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
cpu_set_b (cpu, val);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
cpu_set_ccr (cpu, val);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
cpu_set_tmp2 (cpu, val);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
cpu_set_d (cpu, val);
|
||||
break;
|
||||
|
||||
case 5:
|
||||
cpu_set_x (cpu, val);
|
||||
break;
|
||||
|
||||
case 6:
|
||||
cpu_set_y (cpu, val);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
cpu_set_sp (cpu, val);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val)
|
||||
{
|
||||
switch (reg)
|
||||
{
|
||||
case 0:
|
||||
cpu_set_x (cpu, val);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
cpu_set_y (cpu, val);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
cpu_set_sp (cpu, val);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
cpu_set_pc (cpu, val);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Returns the address of a 68HC12 indexed operand.
|
||||
Pre and post modifications are handled on the source register. */
|
||||
uint16
|
||||
cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
|
||||
{
|
||||
uint8 reg;
|
||||
uint16 sval;
|
||||
uint16 addr;
|
||||
uint8 code;
|
||||
|
||||
code = cpu_fetch8 (cpu);
|
||||
|
||||
/* n,r with 5-bit signed constant. */
|
||||
if ((code & 0x20) == 0)
|
||||
{
|
||||
reg = (code >> 6) & 3;
|
||||
sval = (code & 0x1f);
|
||||
if (code & 0x10)
|
||||
sval |= 0xfff0;
|
||||
|
||||
addr = cpu_get_reg (cpu, reg);
|
||||
addr += sval;
|
||||
}
|
||||
|
||||
/* Auto pre/post increment/decrement. */
|
||||
else if ((code & 0xc0) != 0xc0)
|
||||
{
|
||||
reg = (code >> 6) & 3;
|
||||
sval = (code & 0x0f);
|
||||
if (sval & 0x8)
|
||||
{
|
||||
sval |= 0xfff0;
|
||||
}
|
||||
else
|
||||
{
|
||||
sval = sval + 1;
|
||||
}
|
||||
addr = cpu_get_reg (cpu, reg);
|
||||
cpu_set_reg (cpu, reg, addr + sval);
|
||||
if ((code & 0x10) == 0)
|
||||
{
|
||||
addr += sval;
|
||||
}
|
||||
}
|
||||
|
||||
/* [n,r] 16-bits offset indexed indirect. */
|
||||
else if ((code & 0x07) == 3)
|
||||
{
|
||||
if (restrict)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
reg = (code >> 3) & 0x03;
|
||||
addr = cpu_get_reg (cpu, reg);
|
||||
addr += cpu_fetch16 (cpu);
|
||||
addr = memory_read16 (cpu, addr);
|
||||
cpu_add_cycles (cpu, 1);
|
||||
}
|
||||
else if ((code & 0x4) == 0)
|
||||
{
|
||||
if (restrict)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
reg = (code >> 3) & 0x03;
|
||||
addr = cpu_get_reg (cpu, reg);
|
||||
if (code & 0x2)
|
||||
{
|
||||
sval = cpu_fetch16 (cpu);
|
||||
cpu_add_cycles (cpu, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
sval = cpu_fetch8 (cpu);
|
||||
if (code & 0x1)
|
||||
sval |= 0xff00;
|
||||
cpu_add_cycles (cpu, 1);
|
||||
}
|
||||
addr += sval;
|
||||
}
|
||||
else
|
||||
{
|
||||
reg = (code >> 3) & 0x03;
|
||||
addr = cpu_get_reg (cpu, reg);
|
||||
switch (code & 3)
|
||||
{
|
||||
case 0:
|
||||
addr += cpu_get_a (cpu);
|
||||
break;
|
||||
case 1:
|
||||
addr += cpu_get_b (cpu);
|
||||
break;
|
||||
case 2:
|
||||
addr += cpu_get_d (cpu);
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
addr += cpu_get_d (cpu);
|
||||
addr = memory_read16 (cpu, addr);
|
||||
cpu_add_cycles (cpu, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
uint8
|
||||
cpu_get_indexed_operand8 (sim_cpu* cpu, int restrict)
|
||||
{
|
||||
uint16 addr;
|
||||
|
||||
addr = cpu_get_indexed_operand_addr (cpu, restrict);
|
||||
return memory_read8 (cpu, addr);
|
||||
}
|
||||
|
||||
uint16
|
||||
cpu_get_indexed_operand16 (sim_cpu* cpu, int restrict)
|
||||
{
|
||||
uint16 addr;
|
||||
|
||||
addr = cpu_get_indexed_operand_addr (cpu, restrict);
|
||||
return memory_read16 (cpu, addr);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_move8 (sim_cpu *cpu, uint8 code)
|
||||
{
|
||||
uint8 src;
|
||||
uint16 addr;
|
||||
|
||||
switch (code)
|
||||
{
|
||||
case 0x0b:
|
||||
src = cpu_fetch8 (cpu);
|
||||
addr = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
addr = cpu_get_indexed_operand_addr (cpu, 1);
|
||||
src = cpu_fetch8 (cpu);
|
||||
break;
|
||||
|
||||
case 0x0c:
|
||||
addr = cpu_fetch16 (cpu);
|
||||
src = memory_read8 (cpu, addr);
|
||||
addr = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x09:
|
||||
addr = cpu_get_indexed_operand_addr (cpu, 1);
|
||||
src = memory_read8 (cpu, cpu_fetch16 (cpu));
|
||||
break;
|
||||
|
||||
case 0x0d:
|
||||
src = cpu_get_indexed_operand8 (cpu, 1);
|
||||
addr = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x0a:
|
||||
src = cpu_get_indexed_operand8 (cpu, 1);
|
||||
addr = cpu_get_indexed_operand_addr (cpu, 1);
|
||||
break;
|
||||
|
||||
}
|
||||
memory_write8 (cpu, addr, src);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_move16 (sim_cpu *cpu, uint8 code)
|
||||
{
|
||||
uint16 src;
|
||||
uint16 addr;
|
||||
|
||||
switch (code)
|
||||
{
|
||||
case 0x03:
|
||||
src = cpu_fetch16 (cpu);
|
||||
addr = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x00:
|
||||
addr = cpu_get_indexed_operand_addr (cpu, 1);
|
||||
src = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x04:
|
||||
addr = cpu_fetch16 (cpu);
|
||||
src = memory_read16 (cpu, addr);
|
||||
addr = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
addr = cpu_get_indexed_operand_addr (cpu, 1);
|
||||
src = memory_read16 (cpu, cpu_fetch16 (cpu));
|
||||
break;
|
||||
|
||||
case 0x05:
|
||||
src = cpu_get_indexed_operand16 (cpu, 1);
|
||||
addr = cpu_fetch16 (cpu);
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
src = cpu_get_indexed_operand16 (cpu, 1);
|
||||
addr = cpu_get_indexed_operand_addr (cpu, 1);
|
||||
break;
|
||||
|
||||
}
|
||||
memory_write16 (cpu, addr, src);
|
||||
}
|
||||
|
||||
int
|
||||
cpu_initialize (SIM_DESC sd, sim_cpu *cpu)
|
||||
{
|
||||
|
|
@ -346,7 +681,10 @@ cpu_reset (sim_cpu *cpu)
|
|||
/* Initialize the config register.
|
||||
It is only initialized at reset time. */
|
||||
memset (cpu->ios, 0, sizeof (cpu->ios));
|
||||
cpu->ios[M6811_INIT] = 0x1;
|
||||
if (cpu->cpu_configured_arch->arch == bfd_arch_m68hc11)
|
||||
cpu->ios[M6811_INIT] = 0x1;
|
||||
else
|
||||
cpu->ios[M6811_INIT] = 0;
|
||||
|
||||
/* Output compare registers set to 0xFFFF. */
|
||||
cpu->ios[M6811_TOC1_H] = 0xFF;
|
||||
|
|
@ -463,18 +801,109 @@ cpu_fetch_relbranch (sim_cpu *cpu)
|
|||
return addr;
|
||||
}
|
||||
|
||||
uint16
|
||||
cpu_fetch_relbranch16 (sim_cpu *cpu)
|
||||
{
|
||||
uint16 addr = cpu_fetch16 (cpu);
|
||||
|
||||
addr += cpu->cpu_regs.pc;
|
||||
return addr;
|
||||
}
|
||||
|
||||
/* Push all the CPU registers (when an interruption occurs). */
|
||||
void
|
||||
cpu_push_all (sim_cpu *cpu)
|
||||
{
|
||||
cpu_push_uint16 (cpu, cpu->cpu_regs.pc);
|
||||
cpu_push_uint16 (cpu, cpu->cpu_regs.iy);
|
||||
cpu_push_uint16 (cpu, cpu->cpu_regs.ix);
|
||||
cpu_push_uint16 (cpu, cpu->cpu_regs.d);
|
||||
cpu_push_uint8 (cpu, cpu->cpu_regs.ccr);
|
||||
if (cpu->cpu_configured_arch->arch == bfd_arch_m68hc11)
|
||||
{
|
||||
cpu_m68hc11_push_uint16 (cpu, cpu->cpu_regs.pc);
|
||||
cpu_m68hc11_push_uint16 (cpu, cpu->cpu_regs.iy);
|
||||
cpu_m68hc11_push_uint16 (cpu, cpu->cpu_regs.ix);
|
||||
cpu_m68hc11_push_uint16 (cpu, cpu->cpu_regs.d);
|
||||
cpu_m68hc11_push_uint8 (cpu, cpu->cpu_regs.ccr);
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu_m68hc12_push_uint16 (cpu, cpu->cpu_regs.pc);
|
||||
cpu_m68hc12_push_uint16 (cpu, cpu->cpu_regs.iy);
|
||||
cpu_m68hc12_push_uint16 (cpu, cpu->cpu_regs.ix);
|
||||
cpu_m68hc12_push_uint16 (cpu, cpu->cpu_regs.d);
|
||||
cpu_m68hc12_push_uint8 (cpu, cpu->cpu_regs.ccr);
|
||||
}
|
||||
}
|
||||
|
||||
/* Simulation of the dbcc/ibcc/tbcc 68HC12 conditional branch operations. */
|
||||
void
|
||||
cpu_dbcc (sim_cpu* cpu)
|
||||
{
|
||||
uint8 code;
|
||||
uint16 addr;
|
||||
uint16 inc;
|
||||
uint16 reg;
|
||||
|
||||
code = cpu_fetch8 (cpu);
|
||||
switch (code & 0xc0)
|
||||
{
|
||||
case 0x80: /* ibcc */
|
||||
inc = 1;
|
||||
break;
|
||||
case 0x40: /* tbcc */
|
||||
inc = 0;
|
||||
break;
|
||||
case 0: /* dbcc */
|
||||
inc = -1;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
break;
|
||||
}
|
||||
|
||||
addr = cpu_fetch8 (cpu);
|
||||
if (code & 0x10)
|
||||
addr |= 0xff00;
|
||||
|
||||
addr += cpu_get_pc (cpu);
|
||||
reg = cpu_get_src_reg (cpu, code & 0x07);
|
||||
reg += inc;
|
||||
|
||||
/* Branch according to register value. */
|
||||
if ((reg != 0 && (code & 0x20)) || (reg == 0 && !(code & 0x20)))
|
||||
{
|
||||
cpu_set_pc (cpu, addr);
|
||||
}
|
||||
cpu_set_dst_reg (cpu, code & 0x07, reg);
|
||||
}
|
||||
|
||||
void
|
||||
cpu_exg (sim_cpu* cpu, uint8 code)
|
||||
{
|
||||
uint8 r1, r2;
|
||||
uint16 src1;
|
||||
uint16 src2;
|
||||
|
||||
r1 = (code >> 4) & 0x07;
|
||||
r2 = code & 0x07;
|
||||
if (code & 0x80)
|
||||
{
|
||||
src1 = cpu_get_src_reg (cpu, r1);
|
||||
src2 = cpu_get_src_reg (cpu, r2);
|
||||
if (r2 == 1 || r2 == 2)
|
||||
src2 |= 0xff00;
|
||||
|
||||
cpu_set_dst_reg (cpu, r2, src1);
|
||||
cpu_set_dst_reg (cpu, r1, src2);
|
||||
}
|
||||
else
|
||||
{
|
||||
src1 = cpu_get_src_reg (cpu, r1);
|
||||
|
||||
/* Sign extend the 8-bit registers (A, B, CCR). */
|
||||
if ((r1 == 0 || r1 == 1 || r1 == 2) && (src1 & 0x80))
|
||||
src1 |= 0xff00;
|
||||
|
||||
cpu_set_dst_reg (cpu, r2, src1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle special instructions. */
|
||||
void
|
||||
|
|
@ -486,12 +915,26 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
|||
{
|
||||
uint8 ccr;
|
||||
|
||||
ccr = cpu_pop_uint8 (cpu);
|
||||
ccr = cpu_m68hc11_pop_uint8 (cpu);
|
||||
cpu_set_ccr (cpu, ccr);
|
||||
cpu_set_d (cpu, cpu_pop_uint16 (cpu));
|
||||
cpu_set_x (cpu, cpu_pop_uint16 (cpu));
|
||||
cpu_set_y (cpu, cpu_pop_uint16 (cpu));
|
||||
cpu_set_pc (cpu, cpu_pop_uint16 (cpu));
|
||||
cpu_set_d (cpu, cpu_m68hc11_pop_uint16 (cpu));
|
||||
cpu_set_x (cpu, cpu_m68hc11_pop_uint16 (cpu));
|
||||
cpu_set_y (cpu, cpu_m68hc11_pop_uint16 (cpu));
|
||||
cpu_set_pc (cpu, cpu_m68hc11_pop_uint16 (cpu));
|
||||
cpu_return (cpu);
|
||||
break;
|
||||
}
|
||||
|
||||
case M6812_RTI:
|
||||
{
|
||||
uint8 ccr;
|
||||
|
||||
ccr = cpu_m68hc12_pop_uint8 (cpu);
|
||||
cpu_set_ccr (cpu, ccr);
|
||||
cpu_set_d (cpu, cpu_m68hc12_pop_uint16 (cpu));
|
||||
cpu_set_x (cpu, cpu_m68hc12_pop_uint16 (cpu));
|
||||
cpu_set_y (cpu, cpu_m68hc12_pop_uint16 (cpu));
|
||||
cpu_set_pc (cpu, cpu_m68hc12_pop_uint16 (cpu));
|
||||
cpu_return (cpu);
|
||||
break;
|
||||
}
|
||||
|
|
@ -542,6 +985,7 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
|||
break;
|
||||
|
||||
case M6811_TEST:
|
||||
case M6812_BGND:
|
||||
{
|
||||
SIM_DESC sd;
|
||||
|
||||
|
|
@ -558,6 +1002,115 @@ cpu_special (sim_cpu *cpu, enum M6811_Special special)
|
|||
/* else this is a nop but not in test factory mode. */
|
||||
break;
|
||||
}
|
||||
|
||||
case M6812_IDIVS:
|
||||
{
|
||||
int32 src1 = (int16) cpu_get_d (cpu);
|
||||
int32 src2 = (int16) cpu_get_x (cpu);
|
||||
|
||||
if (src2 == 0)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu_set_d (cpu, src1 % src2);
|
||||
src1 = src1 / src2;
|
||||
cpu_set_x (cpu, src1);
|
||||
cpu_set_ccr_C (cpu, 0);
|
||||
cpu_set_ccr_Z (cpu, src1 == 0);
|
||||
cpu_set_ccr_N (cpu, src1 & 0x8000);
|
||||
cpu_set_ccr_V (cpu, src1 >= 32768 || src1 < -32768);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case M6812_EDIV:
|
||||
{
|
||||
uint32 src1 = (uint32) cpu_get_x (cpu);
|
||||
uint32 src2 = (uint32) (cpu_get_y (cpu) << 16)
|
||||
| (uint32) (cpu_get_d (cpu));
|
||||
|
||||
if (src1 == 0)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu_set_ccr_C (cpu, 0);
|
||||
cpu_set_d (cpu, src2 % src1);
|
||||
src2 = src2 / src1;
|
||||
cpu_set_y (cpu, src2);
|
||||
cpu_set_ccr_Z (cpu, src2 == 0);
|
||||
cpu_set_ccr_N (cpu, (src2 & 0x8000) != 0);
|
||||
cpu_set_ccr_V (cpu, (src2 & 0xffff0000) != 0);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case M6812_EDIVS:
|
||||
{
|
||||
int32 src1 = (int16) cpu_get_x (cpu);
|
||||
int32 src2 = (uint32) (cpu_get_y (cpu) << 16)
|
||||
| (uint32) (cpu_get_d (cpu));
|
||||
|
||||
if (src1 == 0)
|
||||
{
|
||||
cpu_set_ccr_C (cpu, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
cpu_set_ccr_C (cpu, 0);
|
||||
cpu_set_d (cpu, src2 % src1);
|
||||
src2 = src2 / src1;
|
||||
cpu_set_y (cpu, src2);
|
||||
cpu_set_ccr_Z (cpu, src2 == 0);
|
||||
cpu_set_ccr_N (cpu, (src2 & 0x8000) != 0);
|
||||
cpu_set_ccr_V (cpu, src2 > 32767 || src2 < -32768);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case M6812_EMULS:
|
||||
{
|
||||
int32 src1, src2;
|
||||
|
||||
src1 = (int16) cpu_get_d (cpu);
|
||||
src2 = (int16) cpu_get_y (cpu);
|
||||
src1 = src1 * src2;
|
||||
cpu_set_d (cpu, src1 & 0x0ffff);
|
||||
cpu_set_y (cpu, src1 >> 16);
|
||||
cpu_set_ccr_Z (cpu, src1 == 0);
|
||||
cpu_set_ccr_N (cpu, (src1 & 0x80000000) != 0);
|
||||
cpu_set_ccr_C (cpu, (src1 & 0x00008000) != 0);
|
||||
}
|
||||
break;
|
||||
|
||||
case M6812_EMACS:
|
||||
{
|
||||
int32 src1, src2;
|
||||
uint16 addr;
|
||||
|
||||
addr = cpu_fetch16 (cpu);
|
||||
src1 = (int16) memory_read16 (cpu, cpu_get_x (cpu));
|
||||
src2 = (int16) memory_read16 (cpu, cpu_get_y (cpu));
|
||||
src1 = src1 * src2;
|
||||
src2 = (((uint32) memory_read16 (cpu, addr)) << 16)
|
||||
| (uint32) memory_read16 (cpu, addr + 2);
|
||||
|
||||
memory_write16 (cpu, addr, (src1 + src2) >> 16);
|
||||
memory_write16 (cpu, addr + 2, (src1 + src2));
|
||||
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
case M6812_ETBL:
|
||||
default:
|
||||
sim_engine_halt (CPU_STATE (cpu), cpu, NULL,
|
||||
cpu_get_pc (cpu), sim_stopped,
|
||||
SIM_SIGILL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -577,7 +1130,7 @@ cpu_single_step (sim_cpu *cpu)
|
|||
}
|
||||
|
||||
/* printf("PC = 0x%04x\n", cpu_get_pc (cpu));*/
|
||||
cpu_interp (cpu);
|
||||
cpu->cpu_interpretor (cpu);
|
||||
cpu->cpu_absolute_cycle += cpu->cpu_current_cycle;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* sim-main.h -- Simulator for Motorola 68HC11
|
||||
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
|
||||
/* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
|
||||
Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
|
||||
Written by Stephane Carrez (stcarrez@worldnet.fr)
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
|
@ -65,6 +65,11 @@ enum m68hc11_map_level
|
|||
M6811_RAM_LEVEL
|
||||
};
|
||||
|
||||
enum cpu_type
|
||||
{
|
||||
CPU_M6811,
|
||||
CPU_M6812
|
||||
};
|
||||
|
||||
#define X_REGNUM 0
|
||||
#define D_REGNUM 1
|
||||
|
|
@ -103,23 +108,45 @@ extern void print_io_byte (SIM_DESC sd, const char *name,
|
|||
io_reg_desc *desc, uint8 val, uint16 addr);
|
||||
|
||||
|
||||
/* List of special 68HC11 instructions that are not handled by the
|
||||
/* List of special 68HC11&68HC12 instructions that are not handled by the
|
||||
'gencode.c' generator. These complex instructions are implemented
|
||||
by 'cpu_special'. */
|
||||
enum M6811_Special
|
||||
{
|
||||
/* 68HC11 instructions. */
|
||||
M6811_DAA,
|
||||
M6811_EMUL_SYSCALL,
|
||||
M6811_ILLEGAL,
|
||||
M6811_RTI,
|
||||
M6811_WAI,
|
||||
M6811_STOP,
|
||||
M6811_SWI,
|
||||
M6811_TEST,
|
||||
M6811_ILLEGAL,
|
||||
M6811_EMUL_SYSCALL
|
||||
M6811_WAI,
|
||||
|
||||
/* 68HC12 instructions. */
|
||||
M6812_BGND,
|
||||
M6812_CALL,
|
||||
M6812_IDIVS,
|
||||
M6812_EDIV,
|
||||
M6812_EDIVS,
|
||||
M6812_EMACS,
|
||||
M6812_EMUL,
|
||||
M6812_EMULS,
|
||||
M6812_ETBL,
|
||||
M6812_MEM,
|
||||
M6812_REV,
|
||||
M6812_REVW,
|
||||
M6812_RTC,
|
||||
M6812_RTI,
|
||||
M6812_WAV
|
||||
};
|
||||
|
||||
#define CPU_POP 1
|
||||
#define CPU_PUSH 2
|
||||
|
||||
#define MAX_PORTS 0x40
|
||||
#define M6811_MAX_PORTS (0x03f+1)
|
||||
#define M6812_MAX_PORTS (0x3ff+1)
|
||||
#define MAX_PORTS (M6812_MAX_PORTS)
|
||||
|
||||
/* Tentative to keep track of the stack frame.
|
||||
The frame is updated each time a call or a return are made.
|
||||
|
|
@ -141,6 +168,10 @@ struct cpu_frame_list
|
|||
struct cpu_frame *frame;
|
||||
};
|
||||
|
||||
struct _sim_cpu;
|
||||
|
||||
typedef void (* cpu_interp) (struct _sim_cpu*);
|
||||
|
||||
struct _sim_cpu {
|
||||
/* CPU registers. */
|
||||
struct m6811_regs cpu_regs;
|
||||
|
|
@ -152,6 +183,12 @@ struct _sim_cpu {
|
|||
struct cpu_frame_list *cpu_current_frame;
|
||||
int cpu_need_update_frame;
|
||||
|
||||
/* Pointer to the interpretor routine. */
|
||||
cpu_interp cpu_interpretor;
|
||||
|
||||
/* Pointer to the architecture currently configured in the simulator. */
|
||||
const struct bfd_arch_info *cpu_configured_arch;
|
||||
|
||||
/* CPU absolute cycle time. The cycle time is updated after
|
||||
each instruction, by the number of cycles taken by the instruction.
|
||||
It is cleared only when reset occurs. */
|
||||
|
|
@ -186,11 +223,14 @@ struct _sim_cpu {
|
|||
/* The mode in which the CPU is configured (MODA and MODB pins). */
|
||||
unsigned int cpu_mode;
|
||||
|
||||
/* The cpu being configured. */
|
||||
enum cpu_type cpu_type;
|
||||
|
||||
/* Initial value of the CONFIG register. */
|
||||
uint8 cpu_config;
|
||||
uint8 cpu_use_local_config;
|
||||
|
||||
uint8 ios[0x3F];
|
||||
uint8 ios[MAX_PORTS];
|
||||
|
||||
/* ... base type ... */
|
||||
sim_cpu_base base;
|
||||
|
|
@ -218,10 +258,18 @@ struct _sim_cpu {
|
|||
#define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
|
||||
#define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
|
||||
|
||||
/* 68HC12 specific and Motorola internal registers. */
|
||||
#define cpu_get_tmp3(PROC) (0)
|
||||
#define cpu_get_tmp2(PROC) (0)
|
||||
|
||||
#define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
|
||||
#define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
|
||||
#define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
|
||||
|
||||
/* 68HC12 specific and Motorola internal registers. */
|
||||
#define cpu_set_tmp3(PROC,VAL) (0)
|
||||
#define cpu_set_tmp2(PROC,VAL) (0)
|
||||
|
||||
#if 0
|
||||
/* This is a function in m68hc11_sim.c to keep track of the frame. */
|
||||
#define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
|
||||
|
|
@ -377,9 +425,9 @@ cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
|
|||
cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
|
||||
}
|
||||
|
||||
|
||||
/* Push and pop instructions for 68HC11 (next-available stack mode). */
|
||||
inline void
|
||||
cpu_push_uint8 (sim_cpu *proc, uint8 val)
|
||||
cpu_m68hc11_push_uint8 (sim_cpu *proc, uint8 val)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
|
||||
|
|
@ -389,7 +437,7 @@ cpu_push_uint8 (sim_cpu *proc, uint8 val)
|
|||
}
|
||||
|
||||
inline void
|
||||
cpu_push_uint16 (sim_cpu *proc, uint16 val)
|
||||
cpu_m68hc11_push_uint16 (sim_cpu *proc, uint16 val)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp - 1;
|
||||
|
||||
|
|
@ -399,7 +447,7 @@ cpu_push_uint16 (sim_cpu *proc, uint16 val)
|
|||
}
|
||||
|
||||
inline uint8
|
||||
cpu_pop_uint8 (sim_cpu *proc)
|
||||
cpu_m68hc11_pop_uint8 (sim_cpu *proc)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
uint8 val;
|
||||
|
|
@ -411,7 +459,7 @@ cpu_pop_uint8 (sim_cpu *proc)
|
|||
}
|
||||
|
||||
inline uint16
|
||||
cpu_pop_uint16 (sim_cpu *proc)
|
||||
cpu_m68hc11_pop_uint16 (sim_cpu *proc)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
uint16 val;
|
||||
|
|
@ -422,6 +470,54 @@ cpu_pop_uint16 (sim_cpu *proc)
|
|||
return val;
|
||||
}
|
||||
|
||||
/* Push and pop instructions for 68HC12 (last-used stack mode). */
|
||||
inline void
|
||||
cpu_m68hc12_push_uint8 (sim_cpu *proc, uint8 val)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
|
||||
addr --;
|
||||
memory_write8 (proc, addr, val);
|
||||
proc->cpu_regs.sp = addr;
|
||||
proc->cpu_need_update_frame |= CPU_PUSH;
|
||||
}
|
||||
|
||||
inline void
|
||||
cpu_m68hc12_push_uint16 (sim_cpu *proc, uint16 val)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
|
||||
addr -= 2;
|
||||
memory_write16 (proc, addr, val);
|
||||
proc->cpu_regs.sp = addr;
|
||||
proc->cpu_need_update_frame |= CPU_PUSH;
|
||||
}
|
||||
|
||||
inline uint8
|
||||
cpu_m68hc12_pop_uint8 (sim_cpu *proc)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
uint8 val;
|
||||
|
||||
val = memory_read8 (proc, addr);
|
||||
proc->cpu_regs.sp = addr + 1;
|
||||
proc->cpu_need_update_frame |= CPU_POP;
|
||||
return val;
|
||||
}
|
||||
|
||||
inline uint16
|
||||
cpu_m68hc12_pop_uint16 (sim_cpu *proc)
|
||||
{
|
||||
uint16 addr = proc->cpu_regs.sp;
|
||||
uint16 val;
|
||||
|
||||
val = memory_read16 (proc, addr);
|
||||
proc->cpu_regs.sp = addr + 2;
|
||||
proc->cpu_need_update_frame |= CPU_POP;
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Fetch a 8/16 bit value and update the PC. */
|
||||
inline uint8
|
||||
cpu_fetch8 (sim_cpu *proc)
|
||||
{
|
||||
|
|
@ -445,9 +541,14 @@ cpu_fetch16 (sim_cpu *proc)
|
|||
}
|
||||
|
||||
extern void cpu_call (sim_cpu* proc, uint16 addr);
|
||||
extern void cpu_exg (sim_cpu* proc, uint8 code);
|
||||
extern void cpu_dbcc (sim_cpu* proc);
|
||||
extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
|
||||
extern void cpu_move8 (sim_cpu *proc, uint8 op);
|
||||
extern void cpu_move16 (sim_cpu *proc, uint8 op);
|
||||
|
||||
extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
|
||||
extern uint16 cpu_fetch_relbranch16 (sim_cpu *proc);
|
||||
extern void cpu_push_all (sim_cpu *proc);
|
||||
extern void cpu_single_step (sim_cpu *proc);
|
||||
|
||||
|
|
@ -463,7 +564,8 @@ extern int cpu_restart (sim_cpu *cpu);
|
|||
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
|
||||
uint16 addr, const char *message, ...);
|
||||
extern void emul_os (int op, sim_cpu *cpu);
|
||||
extern void cpu_interp (sim_cpu *cpu);
|
||||
extern void cpu_interp_m6811 (sim_cpu *cpu);
|
||||
extern void cpu_interp_m6812 (sim_cpu *cpu);
|
||||
|
||||
/* The current state of the processor; registers, memory, etc. */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue